1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc.cls 3 * 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 29 30 #include "stream_encoder.h" 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dce120_resource.h" 34 35 #include "dce112/dce112_resource.h" 36 37 #include "dce110/dce110_resource.h" 38 #include "../virtual/virtual_stream_encoder.h" 39 #include "dce120_timing_generator.h" 40 #include "irq/dce120/irq_service_dce120.h" 41 #include "dce/dce_opp.h" 42 #include "dce/dce_clock_source.h" 43 #include "dce/dce_ipp.h" 44 #include "dce/dce_mem_input.h" 45 46 #include "dce110/dce110_hw_sequencer.h" 47 #include "dce120/dce120_hw_sequencer.h" 48 #include "dce/dce_transform.h" 49 50 #include "dce/dce_clk_mgr.h" 51 #include "dce/dce_audio.h" 52 #include "dce/dce_link_encoder.h" 53 #include "dce/dce_stream_encoder.h" 54 #include "dce/dce_hwseq.h" 55 #include "dce/dce_abm.h" 56 #include "dce/dce_dmcu.h" 57 #include "dce/dce_aux.h" 58 #include "dce/dce_i2c.h" 59 60 #include "dce/dce_12_0_offset.h" 61 #include "dce/dce_12_0_sh_mask.h" 62 #include "soc15_hw_ip.h" 63 #include "vega10_ip_offset.h" 64 #include "nbio/nbio_6_1_offset.h" 65 #include "mmhub/mmhub_9_4_0_offset.h" 66 #include "mmhub/mmhub_9_4_0_sh_mask.h" 67 #include "reg_helper.h" 68 69 #include "dce100/dce100_resource.h" 70 71 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 72 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 73 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 74 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 75 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 76 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 77 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 78 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 79 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 80 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 81 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 82 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 83 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 84 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 85 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 86 #endif 87 88 enum dce120_clk_src_array_id { 89 DCE120_CLK_SRC_PLL0, 90 DCE120_CLK_SRC_PLL1, 91 DCE120_CLK_SRC_PLL2, 92 DCE120_CLK_SRC_PLL3, 93 DCE120_CLK_SRC_PLL4, 94 DCE120_CLK_SRC_PLL5, 95 96 DCE120_CLK_SRC_TOTAL 97 }; 98 99 static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = { 100 { 101 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 102 }, 103 { 104 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 105 }, 106 { 107 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 108 }, 109 { 110 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 111 }, 112 { 113 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 114 }, 115 { 116 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 117 } 118 }; 119 120 /* begin ********************* 121 * macros to expend register list macro defined in HW object header file */ 122 123 #define BASE_INNER(seg) \ 124 DCE_BASE__INST0_SEG ## seg 125 126 #define NBIO_BASE_INNER(seg) \ 127 NBIF_BASE__INST0_SEG ## seg 128 129 #define NBIO_BASE(seg) \ 130 NBIO_BASE_INNER(seg) 131 132 /* compile time expand base address. */ 133 #define BASE(seg) \ 134 BASE_INNER(seg) 135 136 #define SR(reg_name)\ 137 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 138 mm ## reg_name 139 140 #define SRI(reg_name, block, id)\ 141 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 142 mm ## block ## id ## _ ## reg_name 143 144 /* MMHUB */ 145 #define MMHUB_BASE_INNER(seg) \ 146 MMHUB_BASE__INST0_SEG ## seg 147 148 #define MMHUB_BASE(seg) \ 149 MMHUB_BASE_INNER(seg) 150 151 #define MMHUB_SR(reg_name)\ 152 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 153 mm ## reg_name 154 155 /* macros to expend register list macro defined in HW object header file 156 * end *********************/ 157 158 159 static const struct dce_dmcu_registers dmcu_regs = { 160 DMCU_DCE110_COMMON_REG_LIST() 161 }; 162 163 static const struct dce_dmcu_shift dmcu_shift = { 164 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 165 }; 166 167 static const struct dce_dmcu_mask dmcu_mask = { 168 DMCU_MASK_SH_LIST_DCE110(_MASK) 169 }; 170 171 static const struct dce_abm_registers abm_regs = { 172 ABM_DCE110_COMMON_REG_LIST() 173 }; 174 175 static const struct dce_abm_shift abm_shift = { 176 ABM_MASK_SH_LIST_DCE110(__SHIFT) 177 }; 178 179 static const struct dce_abm_mask abm_mask = { 180 ABM_MASK_SH_LIST_DCE110(_MASK) 181 }; 182 183 #define ipp_regs(id)\ 184 [id] = {\ 185 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 186 } 187 188 static const struct dce_ipp_registers ipp_regs[] = { 189 ipp_regs(0), 190 ipp_regs(1), 191 ipp_regs(2), 192 ipp_regs(3), 193 ipp_regs(4), 194 ipp_regs(5) 195 }; 196 197 static const struct dce_ipp_shift ipp_shift = { 198 IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT) 199 }; 200 201 static const struct dce_ipp_mask ipp_mask = { 202 IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK) 203 }; 204 205 #define transform_regs(id)\ 206 [id] = {\ 207 XFM_COMMON_REG_LIST_DCE110(id)\ 208 } 209 210 static const struct dce_transform_registers xfm_regs[] = { 211 transform_regs(0), 212 transform_regs(1), 213 transform_regs(2), 214 transform_regs(3), 215 transform_regs(4), 216 transform_regs(5) 217 }; 218 219 static const struct dce_transform_shift xfm_shift = { 220 XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT) 221 }; 222 223 static const struct dce_transform_mask xfm_mask = { 224 XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK) 225 }; 226 227 #define aux_regs(id)\ 228 [id] = {\ 229 AUX_REG_LIST(id)\ 230 } 231 232 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 233 aux_regs(0), 234 aux_regs(1), 235 aux_regs(2), 236 aux_regs(3), 237 aux_regs(4), 238 aux_regs(5) 239 }; 240 241 #define hpd_regs(id)\ 242 [id] = {\ 243 HPD_REG_LIST(id)\ 244 } 245 246 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 247 hpd_regs(0), 248 hpd_regs(1), 249 hpd_regs(2), 250 hpd_regs(3), 251 hpd_regs(4), 252 hpd_regs(5) 253 }; 254 255 #define link_regs(id)\ 256 [id] = {\ 257 LE_DCE120_REG_LIST(id), \ 258 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 259 } 260 261 static const struct dce110_link_enc_registers link_enc_regs[] = { 262 link_regs(0), 263 link_regs(1), 264 link_regs(2), 265 link_regs(3), 266 link_regs(4), 267 link_regs(5), 268 link_regs(6), 269 }; 270 271 272 #define stream_enc_regs(id)\ 273 [id] = {\ 274 SE_COMMON_REG_LIST(id),\ 275 .TMDS_CNTL = 0,\ 276 } 277 278 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 279 stream_enc_regs(0), 280 stream_enc_regs(1), 281 stream_enc_regs(2), 282 stream_enc_regs(3), 283 stream_enc_regs(4), 284 stream_enc_regs(5) 285 }; 286 287 static const struct dce_stream_encoder_shift se_shift = { 288 SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT) 289 }; 290 291 static const struct dce_stream_encoder_mask se_mask = { 292 SE_COMMON_MASK_SH_LIST_DCE120(_MASK) 293 }; 294 295 #define opp_regs(id)\ 296 [id] = {\ 297 OPP_DCE_120_REG_LIST(id),\ 298 } 299 300 static const struct dce_opp_registers opp_regs[] = { 301 opp_regs(0), 302 opp_regs(1), 303 opp_regs(2), 304 opp_regs(3), 305 opp_regs(4), 306 opp_regs(5) 307 }; 308 309 static const struct dce_opp_shift opp_shift = { 310 OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT) 311 }; 312 313 static const struct dce_opp_mask opp_mask = { 314 OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK) 315 }; 316 #define aux_engine_regs(id)\ 317 [id] = {\ 318 AUX_COMMON_REG_LIST(id), \ 319 .AUX_RESET_MASK = 0 \ 320 } 321 322 static const struct dce110_aux_registers aux_engine_regs[] = { 323 aux_engine_regs(0), 324 aux_engine_regs(1), 325 aux_engine_regs(2), 326 aux_engine_regs(3), 327 aux_engine_regs(4), 328 aux_engine_regs(5) 329 }; 330 331 #define audio_regs(id)\ 332 [id] = {\ 333 AUD_COMMON_REG_LIST(id)\ 334 } 335 336 static const struct dce_audio_registers audio_regs[] = { 337 audio_regs(0), 338 audio_regs(1), 339 audio_regs(2), 340 audio_regs(3), 341 audio_regs(4), 342 audio_regs(5) 343 }; 344 345 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 346 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 347 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 348 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 349 350 static const struct dce_audio_shift audio_shift = { 351 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 352 }; 353 354 static const struct dce_aduio_mask audio_mask = { 355 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 356 }; 357 358 #define clk_src_regs(index, id)\ 359 [index] = {\ 360 CS_COMMON_REG_LIST_DCE_112(id),\ 361 } 362 363 static const struct dce110_clk_src_regs clk_src_regs[] = { 364 clk_src_regs(0, A), 365 clk_src_regs(1, B), 366 clk_src_regs(2, C), 367 clk_src_regs(3, D), 368 clk_src_regs(4, E), 369 clk_src_regs(5, F) 370 }; 371 372 static const struct dce110_clk_src_shift cs_shift = { 373 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 374 }; 375 376 static const struct dce110_clk_src_mask cs_mask = { 377 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) 378 }; 379 380 struct output_pixel_processor *dce120_opp_create( 381 struct dc_context *ctx, 382 uint32_t inst) 383 { 384 struct dce110_opp *opp = 385 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 386 387 if (!opp) 388 return NULL; 389 390 dce110_opp_construct(opp, 391 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 392 return &opp->base; 393 } 394 struct dce_aux *dce120_aux_engine_create( 395 struct dc_context *ctx, 396 uint32_t inst) 397 { 398 struct aux_engine_dce110 *aux_engine = 399 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 400 401 if (!aux_engine) 402 return NULL; 403 404 dce110_aux_engine_construct(aux_engine, ctx, inst, 405 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 406 &aux_engine_regs[inst]); 407 408 return &aux_engine->base; 409 } 410 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 411 412 static const struct dce_i2c_registers i2c_hw_regs[] = { 413 i2c_inst_regs(1), 414 i2c_inst_regs(2), 415 i2c_inst_regs(3), 416 i2c_inst_regs(4), 417 i2c_inst_regs(5), 418 i2c_inst_regs(6), 419 }; 420 421 static const struct dce_i2c_shift i2c_shifts = { 422 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 423 }; 424 425 static const struct dce_i2c_mask i2c_masks = { 426 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 427 }; 428 429 struct dce_i2c_hw *dce120_i2c_hw_create( 430 struct dc_context *ctx, 431 uint32_t inst) 432 { 433 struct dce_i2c_hw *dce_i2c_hw = 434 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 435 436 if (!dce_i2c_hw) 437 return NULL; 438 439 dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst, 440 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 441 442 return dce_i2c_hw; 443 } 444 static const struct bios_registers bios_regs = { 445 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + NBIO_BASE(mmBIOS_SCRATCH_3_BASE_IDX), 446 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX) 447 }; 448 449 static const struct resource_caps res_cap = { 450 .num_timing_generator = 6, 451 .num_audio = 7, 452 .num_stream_encoder = 6, 453 .num_pll = 6, 454 .num_ddc = 6, 455 }; 456 457 static const struct dc_plane_cap plane_cap = { 458 .type = DC_PLANE_TYPE_DCE_RGB, 459 .supports_argb8888 = true, 460 }; 461 462 static const struct dc_debug_options debug_defaults = { 463 .disable_clock_gate = true, 464 }; 465 466 struct clock_source *dce120_clock_source_create( 467 struct dc_context *ctx, 468 struct dc_bios *bios, 469 enum clock_source_id id, 470 const struct dce110_clk_src_regs *regs, 471 bool dp_clk_src) 472 { 473 struct dce110_clk_src *clk_src = 474 kzalloc(sizeof(*clk_src), GFP_KERNEL); 475 476 if (!clk_src) 477 return NULL; 478 479 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 480 regs, &cs_shift, &cs_mask)) { 481 clk_src->base.dp_clk_src = dp_clk_src; 482 return &clk_src->base; 483 } 484 485 BREAK_TO_DEBUGGER(); 486 return NULL; 487 } 488 489 void dce120_clock_source_destroy(struct clock_source **clk_src) 490 { 491 kfree(TO_DCE110_CLK_SRC(*clk_src)); 492 *clk_src = NULL; 493 } 494 495 496 bool dce120_hw_sequencer_create(struct dc *dc) 497 { 498 /* All registers used by dce11.2 match those in dce11 in offset and 499 * structure 500 */ 501 dce120_hw_sequencer_construct(dc); 502 503 /*TODO Move to separate file and Override what is needed */ 504 505 return true; 506 } 507 508 static struct timing_generator *dce120_timing_generator_create( 509 struct dc_context *ctx, 510 uint32_t instance, 511 const struct dce110_timing_generator_offsets *offsets) 512 { 513 struct dce110_timing_generator *tg110 = 514 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 515 516 if (!tg110) 517 return NULL; 518 519 dce120_timing_generator_construct(tg110, ctx, instance, offsets); 520 return &tg110->base; 521 } 522 523 static void dce120_transform_destroy(struct transform **xfm) 524 { 525 kfree(TO_DCE_TRANSFORM(*xfm)); 526 *xfm = NULL; 527 } 528 529 static void destruct(struct dce110_resource_pool *pool) 530 { 531 unsigned int i; 532 533 for (i = 0; i < pool->base.pipe_count; i++) { 534 if (pool->base.opps[i] != NULL) 535 dce110_opp_destroy(&pool->base.opps[i]); 536 537 if (pool->base.transforms[i] != NULL) 538 dce120_transform_destroy(&pool->base.transforms[i]); 539 540 if (pool->base.ipps[i] != NULL) 541 dce_ipp_destroy(&pool->base.ipps[i]); 542 543 if (pool->base.mis[i] != NULL) { 544 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 545 pool->base.mis[i] = NULL; 546 } 547 548 if (pool->base.irqs != NULL) { 549 dal_irq_service_destroy(&pool->base.irqs); 550 } 551 552 if (pool->base.timing_generators[i] != NULL) { 553 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 554 pool->base.timing_generators[i] = NULL; 555 } 556 } 557 558 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 559 if (pool->base.engines[i] != NULL) 560 dce110_engine_destroy(&pool->base.engines[i]); 561 if (pool->base.hw_i2cs[i] != NULL) { 562 kfree(pool->base.hw_i2cs[i]); 563 pool->base.hw_i2cs[i] = NULL; 564 } 565 if (pool->base.sw_i2cs[i] != NULL) { 566 kfree(pool->base.sw_i2cs[i]); 567 pool->base.sw_i2cs[i] = NULL; 568 } 569 } 570 571 for (i = 0; i < pool->base.audio_count; i++) { 572 if (pool->base.audios[i]) 573 dce_aud_destroy(&pool->base.audios[i]); 574 } 575 576 for (i = 0; i < pool->base.stream_enc_count; i++) { 577 if (pool->base.stream_enc[i] != NULL) 578 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 579 } 580 581 for (i = 0; i < pool->base.clk_src_count; i++) { 582 if (pool->base.clock_sources[i] != NULL) 583 dce120_clock_source_destroy( 584 &pool->base.clock_sources[i]); 585 } 586 587 if (pool->base.dp_clock_source != NULL) 588 dce120_clock_source_destroy(&pool->base.dp_clock_source); 589 590 if (pool->base.abm != NULL) 591 dce_abm_destroy(&pool->base.abm); 592 593 if (pool->base.dmcu != NULL) 594 dce_dmcu_destroy(&pool->base.dmcu); 595 596 if (pool->base.clk_mgr != NULL) 597 dce_clk_mgr_destroy(&pool->base.clk_mgr); 598 } 599 600 static void read_dce_straps( 601 struct dc_context *ctx, 602 struct resource_straps *straps) 603 { 604 uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0); 605 606 straps->audio_stream_number = get_reg_field_value(reg_val, 607 CC_DC_MISC_STRAPS, 608 AUDIO_STREAM_NUMBER); 609 straps->hdmi_disable = get_reg_field_value(reg_val, 610 CC_DC_MISC_STRAPS, 611 HDMI_DISABLE); 612 613 reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0); 614 straps->dc_pinstraps_audio = get_reg_field_value(reg_val, 615 DC_PINSTRAPS, 616 DC_PINSTRAPS_AUDIO); 617 } 618 619 static struct audio *create_audio( 620 struct dc_context *ctx, unsigned int inst) 621 { 622 return dce_audio_create(ctx, inst, 623 &audio_regs[inst], &audio_shift, &audio_mask); 624 } 625 626 static const struct encoder_feature_support link_enc_feature = { 627 .max_hdmi_deep_color = COLOR_DEPTH_121212, 628 .max_hdmi_pixel_clock = 600000, 629 .hdmi_ycbcr420_supported = true, 630 .dp_ycbcr420_supported = false, 631 .flags.bits.IS_HBR2_CAPABLE = true, 632 .flags.bits.IS_HBR3_CAPABLE = true, 633 .flags.bits.IS_TPS3_CAPABLE = true, 634 .flags.bits.IS_TPS4_CAPABLE = true, 635 }; 636 637 static struct link_encoder *dce120_link_encoder_create( 638 const struct encoder_init_data *enc_init_data) 639 { 640 struct dce110_link_encoder *enc110 = 641 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 642 643 if (!enc110) 644 return NULL; 645 646 dce110_link_encoder_construct(enc110, 647 enc_init_data, 648 &link_enc_feature, 649 &link_enc_regs[enc_init_data->transmitter], 650 &link_enc_aux_regs[enc_init_data->channel - 1], 651 &link_enc_hpd_regs[enc_init_data->hpd_source]); 652 653 return &enc110->base; 654 } 655 656 static struct input_pixel_processor *dce120_ipp_create( 657 struct dc_context *ctx, uint32_t inst) 658 { 659 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 660 661 if (!ipp) { 662 BREAK_TO_DEBUGGER(); 663 return NULL; 664 } 665 666 dce_ipp_construct(ipp, ctx, inst, 667 &ipp_regs[inst], &ipp_shift, &ipp_mask); 668 return &ipp->base; 669 } 670 671 static struct stream_encoder *dce120_stream_encoder_create( 672 enum engine_id eng_id, 673 struct dc_context *ctx) 674 { 675 struct dce110_stream_encoder *enc110 = 676 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 677 678 if (!enc110) 679 return NULL; 680 681 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 682 &stream_enc_regs[eng_id], 683 &se_shift, &se_mask); 684 return &enc110->base; 685 } 686 687 #define SRII(reg_name, block, id)\ 688 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 689 mm ## block ## id ## _ ## reg_name 690 691 static const struct dce_hwseq_registers hwseq_reg = { 692 HWSEQ_DCE120_REG_LIST() 693 }; 694 695 static const struct dce_hwseq_shift hwseq_shift = { 696 HWSEQ_DCE12_MASK_SH_LIST(__SHIFT) 697 }; 698 699 static const struct dce_hwseq_mask hwseq_mask = { 700 HWSEQ_DCE12_MASK_SH_LIST(_MASK) 701 }; 702 703 /* HWSEQ regs for VG20 */ 704 static const struct dce_hwseq_registers dce121_hwseq_reg = { 705 HWSEQ_VG20_REG_LIST() 706 }; 707 708 static const struct dce_hwseq_shift dce121_hwseq_shift = { 709 HWSEQ_VG20_MASK_SH_LIST(__SHIFT) 710 }; 711 712 static const struct dce_hwseq_mask dce121_hwseq_mask = { 713 HWSEQ_VG20_MASK_SH_LIST(_MASK) 714 }; 715 716 static struct dce_hwseq *dce120_hwseq_create( 717 struct dc_context *ctx) 718 { 719 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 720 721 if (hws) { 722 hws->ctx = ctx; 723 hws->regs = &hwseq_reg; 724 hws->shifts = &hwseq_shift; 725 hws->masks = &hwseq_mask; 726 } 727 return hws; 728 } 729 730 static struct dce_hwseq *dce121_hwseq_create( 731 struct dc_context *ctx) 732 { 733 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 734 735 if (hws) { 736 hws->ctx = ctx; 737 hws->regs = &dce121_hwseq_reg; 738 hws->shifts = &dce121_hwseq_shift; 739 hws->masks = &dce121_hwseq_mask; 740 } 741 return hws; 742 } 743 744 static const struct resource_create_funcs res_create_funcs = { 745 .read_dce_straps = read_dce_straps, 746 .create_audio = create_audio, 747 .create_stream_encoder = dce120_stream_encoder_create, 748 .create_hwseq = dce120_hwseq_create, 749 }; 750 751 static const struct resource_create_funcs dce121_res_create_funcs = { 752 .read_dce_straps = read_dce_straps, 753 .create_audio = create_audio, 754 .create_stream_encoder = dce120_stream_encoder_create, 755 .create_hwseq = dce121_hwseq_create, 756 }; 757 758 759 #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) } 760 static const struct dce_mem_input_registers mi_regs[] = { 761 mi_inst_regs(0), 762 mi_inst_regs(1), 763 mi_inst_regs(2), 764 mi_inst_regs(3), 765 mi_inst_regs(4), 766 mi_inst_regs(5), 767 }; 768 769 static const struct dce_mem_input_shift mi_shifts = { 770 MI_DCE12_MASK_SH_LIST(__SHIFT) 771 }; 772 773 static const struct dce_mem_input_mask mi_masks = { 774 MI_DCE12_MASK_SH_LIST(_MASK) 775 }; 776 777 static struct mem_input *dce120_mem_input_create( 778 struct dc_context *ctx, 779 uint32_t inst) 780 { 781 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 782 GFP_KERNEL); 783 784 if (!dce_mi) { 785 BREAK_TO_DEBUGGER(); 786 return NULL; 787 } 788 789 dce120_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 790 return &dce_mi->base; 791 } 792 793 static struct transform *dce120_transform_create( 794 struct dc_context *ctx, 795 uint32_t inst) 796 { 797 struct dce_transform *transform = 798 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 799 800 if (!transform) 801 return NULL; 802 803 dce_transform_construct(transform, ctx, inst, 804 &xfm_regs[inst], &xfm_shift, &xfm_mask); 805 transform->lb_memory_size = 0x1404; /*5124*/ 806 return &transform->base; 807 } 808 809 static void dce120_destroy_resource_pool(struct resource_pool **pool) 810 { 811 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 812 813 destruct(dce110_pool); 814 kfree(dce110_pool); 815 *pool = NULL; 816 } 817 818 static const struct resource_funcs dce120_res_pool_funcs = { 819 .destroy = dce120_destroy_resource_pool, 820 .link_enc_create = dce120_link_encoder_create, 821 .validate_bandwidth = dce112_validate_bandwidth, 822 .validate_plane = dce100_validate_plane, 823 .add_stream_to_ctx = dce112_add_stream_to_ctx 824 }; 825 826 static void bw_calcs_data_update_from_pplib(struct dc *dc) 827 { 828 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 829 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 830 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; 831 int i; 832 unsigned int clk; 833 unsigned int latency; 834 835 /*do system clock*/ 836 if (!dm_pp_get_clock_levels_by_type_with_latency( 837 dc->ctx, 838 DM_PP_CLOCK_TYPE_ENGINE_CLK, 839 &eng_clks) || eng_clks.num_levels == 0) { 840 841 eng_clks.num_levels = 8; 842 clk = 300000; 843 844 for (i = 0; i < eng_clks.num_levels; i++) { 845 eng_clks.data[i].clocks_in_khz = clk; 846 clk += 100000; 847 } 848 } 849 850 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ 851 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 852 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); 853 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 854 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); 855 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 856 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); 857 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 858 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); 859 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 860 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); 861 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 862 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); 863 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 864 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); 865 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 866 eng_clks.data[0].clocks_in_khz, 1000); 867 868 /*do memory clock*/ 869 if (!dm_pp_get_clock_levels_by_type_with_latency( 870 dc->ctx, 871 DM_PP_CLOCK_TYPE_MEMORY_CLK, 872 &mem_clks) || mem_clks.num_levels == 0) { 873 874 mem_clks.num_levels = 3; 875 clk = 250000; 876 latency = 45; 877 878 for (i = 0; i < eng_clks.num_levels; i++) { 879 mem_clks.data[i].clocks_in_khz = clk; 880 mem_clks.data[i].latency_in_us = latency; 881 clk += 500000; 882 latency -= 5; 883 } 884 885 } 886 887 /* we don't need to call PPLIB for validation clock since they 888 * also give us the highest sclk and highest mclk (UMA clock). 889 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): 890 * YCLK = UMACLK*m_memoryTypeMultiplier 891 */ 892 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 893 mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 1000); 894 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 895 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 896 1000); 897 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 898 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 899 1000); 900 901 /* Now notify PPLib/SMU about which Watermarks sets they should select 902 * depending on DPM state they are in. And update BW MGR GFX Engine and 903 * Memory clock member variables for Watermarks calculations for each 904 * Watermark Set 905 */ 906 clk_ranges.num_wm_sets = 4; 907 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; 908 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = 909 eng_clks.data[0].clocks_in_khz; 910 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = 911 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 912 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz = 913 mem_clks.data[0].clocks_in_khz; 914 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = 915 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 916 917 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; 918 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = 919 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 920 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 921 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; 922 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz = 923 mem_clks.data[0].clocks_in_khz; 924 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = 925 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 926 927 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; 928 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = 929 eng_clks.data[0].clocks_in_khz; 930 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = 931 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 932 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz = 933 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 934 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 935 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; 936 937 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; 938 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = 939 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 940 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 941 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; 942 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz = 943 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 944 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 945 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; 946 947 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 948 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); 949 } 950 951 static uint32_t read_pipe_fuses(struct dc_context *ctx) 952 { 953 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); 954 /* VG20 support max 6 pipes */ 955 value = value & 0x3f; 956 return value; 957 } 958 959 static bool construct( 960 uint8_t num_virtual_links, 961 struct dc *dc, 962 struct dce110_resource_pool *pool) 963 { 964 unsigned int i; 965 int j; 966 struct dc_context *ctx = dc->ctx; 967 struct irq_service_init_data irq_init_data; 968 static const struct resource_create_funcs *res_funcs; 969 bool is_vg20 = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev); 970 uint32_t pipe_fuses; 971 972 ctx->dc_bios->regs = &bios_regs; 973 974 pool->base.res_cap = &res_cap; 975 pool->base.funcs = &dce120_res_pool_funcs; 976 977 /* TODO: Fill more data from GreenlandAsicCapability.cpp */ 978 pool->base.pipe_count = res_cap.num_timing_generator; 979 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 980 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 981 982 dc->caps.max_downscale_ratio = 200; 983 dc->caps.i2c_speed_in_khz = 100; 984 dc->caps.max_cursor_size = 128; 985 dc->caps.dual_link_dvi = true; 986 dc->caps.psp_setup_panel_mode = true; 987 988 dc->debug = debug_defaults; 989 990 /************************************************* 991 * Create resources * 992 *************************************************/ 993 994 pool->base.clock_sources[DCE120_CLK_SRC_PLL0] = 995 dce120_clock_source_create(ctx, ctx->dc_bios, 996 CLOCK_SOURCE_COMBO_PHY_PLL0, 997 &clk_src_regs[0], false); 998 pool->base.clock_sources[DCE120_CLK_SRC_PLL1] = 999 dce120_clock_source_create(ctx, ctx->dc_bios, 1000 CLOCK_SOURCE_COMBO_PHY_PLL1, 1001 &clk_src_regs[1], false); 1002 pool->base.clock_sources[DCE120_CLK_SRC_PLL2] = 1003 dce120_clock_source_create(ctx, ctx->dc_bios, 1004 CLOCK_SOURCE_COMBO_PHY_PLL2, 1005 &clk_src_regs[2], false); 1006 pool->base.clock_sources[DCE120_CLK_SRC_PLL3] = 1007 dce120_clock_source_create(ctx, ctx->dc_bios, 1008 CLOCK_SOURCE_COMBO_PHY_PLL3, 1009 &clk_src_regs[3], false); 1010 pool->base.clock_sources[DCE120_CLK_SRC_PLL4] = 1011 dce120_clock_source_create(ctx, ctx->dc_bios, 1012 CLOCK_SOURCE_COMBO_PHY_PLL4, 1013 &clk_src_regs[4], false); 1014 pool->base.clock_sources[DCE120_CLK_SRC_PLL5] = 1015 dce120_clock_source_create(ctx, ctx->dc_bios, 1016 CLOCK_SOURCE_COMBO_PHY_PLL5, 1017 &clk_src_regs[5], false); 1018 pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL; 1019 1020 pool->base.dp_clock_source = 1021 dce120_clock_source_create(ctx, ctx->dc_bios, 1022 CLOCK_SOURCE_ID_DP_DTO, 1023 &clk_src_regs[0], true); 1024 1025 for (i = 0; i < pool->base.clk_src_count; i++) { 1026 if (pool->base.clock_sources[i] == NULL) { 1027 dm_error("DC: failed to create clock sources!\n"); 1028 BREAK_TO_DEBUGGER(); 1029 goto clk_src_create_fail; 1030 } 1031 } 1032 1033 if (is_vg20) 1034 pool->base.clk_mgr = dce121_clk_mgr_create(ctx); 1035 else 1036 pool->base.clk_mgr = dce120_clk_mgr_create(ctx); 1037 1038 if (pool->base.clk_mgr == NULL) { 1039 dm_error("DC: failed to create display clock!\n"); 1040 BREAK_TO_DEBUGGER(); 1041 goto dccg_create_fail; 1042 } 1043 1044 pool->base.dmcu = dce_dmcu_create(ctx, 1045 &dmcu_regs, 1046 &dmcu_shift, 1047 &dmcu_mask); 1048 if (pool->base.dmcu == NULL) { 1049 dm_error("DC: failed to create dmcu!\n"); 1050 BREAK_TO_DEBUGGER(); 1051 goto res_create_fail; 1052 } 1053 1054 pool->base.abm = dce_abm_create(ctx, 1055 &abm_regs, 1056 &abm_shift, 1057 &abm_mask); 1058 if (pool->base.abm == NULL) { 1059 dm_error("DC: failed to create abm!\n"); 1060 BREAK_TO_DEBUGGER(); 1061 goto res_create_fail; 1062 } 1063 1064 1065 irq_init_data.ctx = dc->ctx; 1066 pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data); 1067 if (!pool->base.irqs) 1068 goto irqs_create_fail; 1069 1070 /* VG20: Pipe harvesting enabled, retrieve valid pipe fuses */ 1071 if (is_vg20) 1072 pipe_fuses = read_pipe_fuses(ctx); 1073 1074 /* index to valid pipe resource */ 1075 j = 0; 1076 for (i = 0; i < pool->base.pipe_count; i++) { 1077 if (is_vg20) { 1078 if ((pipe_fuses & (1 << i)) != 0) { 1079 dm_error("DC: skip invalid pipe %d!\n", i); 1080 continue; 1081 } 1082 } 1083 1084 pool->base.timing_generators[j] = 1085 dce120_timing_generator_create( 1086 ctx, 1087 i, 1088 &dce120_tg_offsets[i]); 1089 if (pool->base.timing_generators[j] == NULL) { 1090 BREAK_TO_DEBUGGER(); 1091 dm_error("DC: failed to create tg!\n"); 1092 goto controller_create_fail; 1093 } 1094 1095 pool->base.mis[j] = dce120_mem_input_create(ctx, i); 1096 1097 if (pool->base.mis[j] == NULL) { 1098 BREAK_TO_DEBUGGER(); 1099 dm_error( 1100 "DC: failed to create memory input!\n"); 1101 goto controller_create_fail; 1102 } 1103 1104 pool->base.ipps[j] = dce120_ipp_create(ctx, i); 1105 if (pool->base.ipps[i] == NULL) { 1106 BREAK_TO_DEBUGGER(); 1107 dm_error( 1108 "DC: failed to create input pixel processor!\n"); 1109 goto controller_create_fail; 1110 } 1111 1112 pool->base.transforms[j] = dce120_transform_create(ctx, i); 1113 if (pool->base.transforms[i] == NULL) { 1114 BREAK_TO_DEBUGGER(); 1115 dm_error( 1116 "DC: failed to create transform!\n"); 1117 goto res_create_fail; 1118 } 1119 1120 pool->base.opps[j] = dce120_opp_create( 1121 ctx, 1122 i); 1123 if (pool->base.opps[j] == NULL) { 1124 BREAK_TO_DEBUGGER(); 1125 dm_error( 1126 "DC: failed to create output pixel processor!\n"); 1127 } 1128 1129 /* check next valid pipe */ 1130 j++; 1131 } 1132 1133 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1134 pool->base.engines[i] = dce120_aux_engine_create(ctx, i); 1135 if (pool->base.engines[i] == NULL) { 1136 BREAK_TO_DEBUGGER(); 1137 dm_error( 1138 "DC:failed to create aux engine!!\n"); 1139 goto res_create_fail; 1140 } 1141 pool->base.hw_i2cs[i] = dce120_i2c_hw_create(ctx, i); 1142 if (pool->base.hw_i2cs[i] == NULL) { 1143 BREAK_TO_DEBUGGER(); 1144 dm_error( 1145 "DC:failed to create i2c engine!!\n"); 1146 goto res_create_fail; 1147 } 1148 pool->base.sw_i2cs[i] = NULL; 1149 } 1150 1151 /* valid pipe num */ 1152 pool->base.pipe_count = j; 1153 pool->base.timing_generator_count = j; 1154 1155 if (is_vg20) 1156 res_funcs = &dce121_res_create_funcs; 1157 else 1158 res_funcs = &res_create_funcs; 1159 1160 if (!resource_construct(num_virtual_links, dc, &pool->base, res_funcs)) 1161 goto res_create_fail; 1162 1163 /* 1164 * This is a bit of a hack. The xGMI enabled info is used to determine 1165 * if audio and display clocks need to be adjusted with the WAFL link's 1166 * SS info. This is a responsiblity of the clk_mgr. But since MMHUB is 1167 * under hwseq, and the relevant register is in MMHUB, we have to do it 1168 * here. 1169 */ 1170 if (is_vg20 && dce121_xgmi_enabled(dc->hwseq)) 1171 dce121_clock_patch_xgmi_ss_info(pool->base.clk_mgr); 1172 1173 /* Create hardware sequencer */ 1174 if (!dce120_hw_sequencer_create(dc)) 1175 goto controller_create_fail; 1176 1177 dc->caps.max_planes = pool->base.pipe_count; 1178 1179 for (i = 0; i < dc->caps.max_planes; ++i) 1180 dc->caps.planes[i] = plane_cap; 1181 1182 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1183 1184 bw_calcs_data_update_from_pplib(dc); 1185 1186 return true; 1187 1188 irqs_create_fail: 1189 controller_create_fail: 1190 dccg_create_fail: 1191 clk_src_create_fail: 1192 res_create_fail: 1193 1194 destruct(pool); 1195 1196 return false; 1197 } 1198 1199 struct resource_pool *dce120_create_resource_pool( 1200 uint8_t num_virtual_links, 1201 struct dc *dc) 1202 { 1203 struct dce110_resource_pool *pool = 1204 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1205 1206 if (!pool) 1207 return NULL; 1208 1209 if (construct(num_virtual_links, dc, pool)) 1210 return &pool->base; 1211 1212 BREAK_TO_DEBUGGER(); 1213 return NULL; 1214 } 1215