1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc.cls 3 * 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 29 30 #include "stream_encoder.h" 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dce120_resource.h" 34 35 #include "dce112/dce112_resource.h" 36 37 #include "dce110/dce110_resource.h" 38 #include "../virtual/virtual_stream_encoder.h" 39 #include "dce120_timing_generator.h" 40 #include "irq/dce120/irq_service_dce120.h" 41 #include "dce/dce_opp.h" 42 #include "dce/dce_clock_source.h" 43 #include "dce/dce_ipp.h" 44 #include "dce/dce_mem_input.h" 45 #include "dce/dce_panel_cntl.h" 46 47 #include "dce110/dce110_hw_sequencer.h" 48 #include "dce120/dce120_hw_sequencer.h" 49 #include "dce/dce_transform.h" 50 #include "clk_mgr.h" 51 #include "dce/dce_audio.h" 52 #include "dce/dce_link_encoder.h" 53 #include "dce/dce_stream_encoder.h" 54 #include "dce/dce_hwseq.h" 55 #include "dce/dce_abm.h" 56 #include "dce/dce_dmcu.h" 57 #include "dce/dce_aux.h" 58 #include "dce/dce_i2c.h" 59 60 #include "dce/dce_12_0_offset.h" 61 #include "dce/dce_12_0_sh_mask.h" 62 #include "soc15_hw_ip.h" 63 #include "vega10_ip_offset.h" 64 #include "nbio/nbio_6_1_offset.h" 65 #include "mmhub/mmhub_1_0_offset.h" 66 #include "mmhub/mmhub_1_0_sh_mask.h" 67 #include "reg_helper.h" 68 69 #include "dce100/dce100_resource.h" 70 71 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 72 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 73 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 74 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 75 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 76 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 77 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 78 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 79 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 80 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 81 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 82 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 83 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 84 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 85 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 86 #endif 87 88 enum dce120_clk_src_array_id { 89 DCE120_CLK_SRC_PLL0, 90 DCE120_CLK_SRC_PLL1, 91 DCE120_CLK_SRC_PLL2, 92 DCE120_CLK_SRC_PLL3, 93 DCE120_CLK_SRC_PLL4, 94 DCE120_CLK_SRC_PLL5, 95 96 DCE120_CLK_SRC_TOTAL 97 }; 98 99 static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = { 100 { 101 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 102 }, 103 { 104 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 105 }, 106 { 107 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 108 }, 109 { 110 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 111 }, 112 { 113 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 114 }, 115 { 116 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 117 } 118 }; 119 120 /* begin ********************* 121 * macros to expend register list macro defined in HW object header file */ 122 123 #define BASE_INNER(seg) \ 124 DCE_BASE__INST0_SEG ## seg 125 126 #define NBIO_BASE_INNER(seg) \ 127 NBIF_BASE__INST0_SEG ## seg 128 129 #define NBIO_BASE(seg) \ 130 NBIO_BASE_INNER(seg) 131 132 /* compile time expand base address. */ 133 #define BASE(seg) \ 134 BASE_INNER(seg) 135 136 #define SR(reg_name)\ 137 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 138 mm ## reg_name 139 140 #define SRI(reg_name, block, id)\ 141 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 142 mm ## block ## id ## _ ## reg_name 143 144 /* MMHUB */ 145 #define MMHUB_BASE_INNER(seg) \ 146 MMHUB_BASE__INST0_SEG ## seg 147 148 #define MMHUB_BASE(seg) \ 149 MMHUB_BASE_INNER(seg) 150 151 #define MMHUB_SR(reg_name)\ 152 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 153 mm ## reg_name 154 155 /* macros to expend register list macro defined in HW object header file 156 * end *********************/ 157 158 159 static const struct dce_dmcu_registers dmcu_regs = { 160 DMCU_DCE110_COMMON_REG_LIST() 161 }; 162 163 static const struct dce_dmcu_shift dmcu_shift = { 164 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 165 }; 166 167 static const struct dce_dmcu_mask dmcu_mask = { 168 DMCU_MASK_SH_LIST_DCE110(_MASK) 169 }; 170 171 static const struct dce_abm_registers abm_regs = { 172 ABM_DCE110_COMMON_REG_LIST() 173 }; 174 175 static const struct dce_abm_shift abm_shift = { 176 ABM_MASK_SH_LIST_DCE110(__SHIFT) 177 }; 178 179 static const struct dce_abm_mask abm_mask = { 180 ABM_MASK_SH_LIST_DCE110(_MASK) 181 }; 182 183 #define ipp_regs(id)\ 184 [id] = {\ 185 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 186 } 187 188 static const struct dce_ipp_registers ipp_regs[] = { 189 ipp_regs(0), 190 ipp_regs(1), 191 ipp_regs(2), 192 ipp_regs(3), 193 ipp_regs(4), 194 ipp_regs(5) 195 }; 196 197 static const struct dce_ipp_shift ipp_shift = { 198 IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT) 199 }; 200 201 static const struct dce_ipp_mask ipp_mask = { 202 IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK) 203 }; 204 205 #define transform_regs(id)\ 206 [id] = {\ 207 XFM_COMMON_REG_LIST_DCE110(id)\ 208 } 209 210 static const struct dce_transform_registers xfm_regs[] = { 211 transform_regs(0), 212 transform_regs(1), 213 transform_regs(2), 214 transform_regs(3), 215 transform_regs(4), 216 transform_regs(5) 217 }; 218 219 static const struct dce_transform_shift xfm_shift = { 220 XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT) 221 }; 222 223 static const struct dce_transform_mask xfm_mask = { 224 XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK) 225 }; 226 227 #define aux_regs(id)\ 228 [id] = {\ 229 AUX_REG_LIST(id)\ 230 } 231 232 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 233 aux_regs(0), 234 aux_regs(1), 235 aux_regs(2), 236 aux_regs(3), 237 aux_regs(4), 238 aux_regs(5) 239 }; 240 241 #define hpd_regs(id)\ 242 [id] = {\ 243 HPD_REG_LIST(id)\ 244 } 245 246 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 247 hpd_regs(0), 248 hpd_regs(1), 249 hpd_regs(2), 250 hpd_regs(3), 251 hpd_regs(4), 252 hpd_regs(5) 253 }; 254 255 #define link_regs(id)\ 256 [id] = {\ 257 LE_DCE120_REG_LIST(id), \ 258 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 259 } 260 261 static const struct dce110_link_enc_registers link_enc_regs[] = { 262 link_regs(0), 263 link_regs(1), 264 link_regs(2), 265 link_regs(3), 266 link_regs(4), 267 link_regs(5), 268 link_regs(6), 269 }; 270 271 272 #define stream_enc_regs(id)\ 273 [id] = {\ 274 SE_COMMON_REG_LIST(id),\ 275 .TMDS_CNTL = 0,\ 276 } 277 278 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 279 stream_enc_regs(0), 280 stream_enc_regs(1), 281 stream_enc_regs(2), 282 stream_enc_regs(3), 283 stream_enc_regs(4), 284 stream_enc_regs(5) 285 }; 286 287 static const struct dce_stream_encoder_shift se_shift = { 288 SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT) 289 }; 290 291 static const struct dce_stream_encoder_mask se_mask = { 292 SE_COMMON_MASK_SH_LIST_DCE120(_MASK) 293 }; 294 295 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 296 { DCE_PANEL_CNTL_REG_LIST() } 297 }; 298 299 static const struct dce_panel_cntl_shift panel_cntl_shift = { 300 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 301 }; 302 303 static const struct dce_panel_cntl_mask panel_cntl_mask = { 304 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 305 }; 306 307 static const struct dce110_aux_registers_shift aux_shift = { 308 DCE12_AUX_MASK_SH_LIST(__SHIFT) 309 }; 310 311 static const struct dce110_aux_registers_mask aux_mask = { 312 DCE12_AUX_MASK_SH_LIST(_MASK) 313 }; 314 315 #define opp_regs(id)\ 316 [id] = {\ 317 OPP_DCE_120_REG_LIST(id),\ 318 } 319 320 static const struct dce_opp_registers opp_regs[] = { 321 opp_regs(0), 322 opp_regs(1), 323 opp_regs(2), 324 opp_regs(3), 325 opp_regs(4), 326 opp_regs(5) 327 }; 328 329 static const struct dce_opp_shift opp_shift = { 330 OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT) 331 }; 332 333 static const struct dce_opp_mask opp_mask = { 334 OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK) 335 }; 336 #define aux_engine_regs(id)\ 337 [id] = {\ 338 AUX_COMMON_REG_LIST(id), \ 339 .AUX_RESET_MASK = 0 \ 340 } 341 342 static const struct dce110_aux_registers aux_engine_regs[] = { 343 aux_engine_regs(0), 344 aux_engine_regs(1), 345 aux_engine_regs(2), 346 aux_engine_regs(3), 347 aux_engine_regs(4), 348 aux_engine_regs(5) 349 }; 350 351 #define audio_regs(id)\ 352 [id] = {\ 353 AUD_COMMON_REG_LIST(id)\ 354 } 355 356 static const struct dce_audio_registers audio_regs[] = { 357 audio_regs(0), 358 audio_regs(1), 359 audio_regs(2), 360 audio_regs(3), 361 audio_regs(4), 362 audio_regs(5), 363 audio_regs(6), 364 }; 365 366 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 367 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 368 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 369 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 370 371 static const struct dce_audio_shift audio_shift = { 372 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 373 }; 374 375 static const struct dce_audio_mask audio_mask = { 376 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 377 }; 378 379 static int map_transmitter_id_to_phy_instance( 380 enum transmitter transmitter) 381 { 382 switch (transmitter) { 383 case TRANSMITTER_UNIPHY_A: 384 return 0; 385 case TRANSMITTER_UNIPHY_B: 386 return 1; 387 case TRANSMITTER_UNIPHY_C: 388 return 2; 389 case TRANSMITTER_UNIPHY_D: 390 return 3; 391 case TRANSMITTER_UNIPHY_E: 392 return 4; 393 case TRANSMITTER_UNIPHY_F: 394 return 5; 395 case TRANSMITTER_UNIPHY_G: 396 return 6; 397 default: 398 ASSERT(0); 399 return 0; 400 } 401 } 402 403 #define clk_src_regs(index, id)\ 404 [index] = {\ 405 CS_COMMON_REG_LIST_DCE_112(id),\ 406 } 407 408 static const struct dce110_clk_src_regs clk_src_regs[] = { 409 clk_src_regs(0, A), 410 clk_src_regs(1, B), 411 clk_src_regs(2, C), 412 clk_src_regs(3, D), 413 clk_src_regs(4, E), 414 clk_src_regs(5, F) 415 }; 416 417 static const struct dce110_clk_src_shift cs_shift = { 418 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 419 }; 420 421 static const struct dce110_clk_src_mask cs_mask = { 422 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) 423 }; 424 425 static struct output_pixel_processor *dce120_opp_create( 426 struct dc_context *ctx, 427 uint32_t inst) 428 { 429 struct dce110_opp *opp = 430 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 431 432 if (!opp) 433 return NULL; 434 435 dce110_opp_construct(opp, 436 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 437 return &opp->base; 438 } 439 static struct dce_aux *dce120_aux_engine_create( 440 struct dc_context *ctx, 441 uint32_t inst) 442 { 443 struct aux_engine_dce110 *aux_engine = 444 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 445 446 if (!aux_engine) 447 return NULL; 448 449 dce110_aux_engine_construct(aux_engine, ctx, inst, 450 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 451 &aux_engine_regs[inst], 452 &aux_mask, 453 &aux_shift, 454 ctx->dc->caps.extended_aux_timeout_support); 455 456 return &aux_engine->base; 457 } 458 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 459 460 static const struct dce_i2c_registers i2c_hw_regs[] = { 461 i2c_inst_regs(1), 462 i2c_inst_regs(2), 463 i2c_inst_regs(3), 464 i2c_inst_regs(4), 465 i2c_inst_regs(5), 466 i2c_inst_regs(6), 467 }; 468 469 static const struct dce_i2c_shift i2c_shifts = { 470 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 471 }; 472 473 static const struct dce_i2c_mask i2c_masks = { 474 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 475 }; 476 477 static struct dce_i2c_hw *dce120_i2c_hw_create( 478 struct dc_context *ctx, 479 uint32_t inst) 480 { 481 struct dce_i2c_hw *dce_i2c_hw = 482 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 483 484 if (!dce_i2c_hw) 485 return NULL; 486 487 dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst, 488 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 489 490 return dce_i2c_hw; 491 } 492 static const struct bios_registers bios_regs = { 493 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + NBIO_BASE(mmBIOS_SCRATCH_3_BASE_IDX), 494 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX) 495 }; 496 497 static const struct resource_caps res_cap = { 498 .num_timing_generator = 6, 499 .num_audio = 7, 500 .num_stream_encoder = 6, 501 .num_pll = 6, 502 .num_ddc = 6, 503 }; 504 505 static const struct dc_plane_cap plane_cap = { 506 .type = DC_PLANE_TYPE_DCE_RGB, 507 508 .pixel_format_support = { 509 .argb8888 = true, 510 .nv12 = false, 511 .fp16 = true 512 }, 513 514 .max_upscale_factor = { 515 .argb8888 = 16000, 516 .nv12 = 1, 517 .fp16 = 1 518 }, 519 520 .max_downscale_factor = { 521 .argb8888 = 250, 522 .nv12 = 1, 523 .fp16 = 1 524 } 525 }; 526 527 static const struct dc_debug_options debug_defaults = { 528 .disable_clock_gate = true, 529 }; 530 531 static struct clock_source *dce120_clock_source_create( 532 struct dc_context *ctx, 533 struct dc_bios *bios, 534 enum clock_source_id id, 535 const struct dce110_clk_src_regs *regs, 536 bool dp_clk_src) 537 { 538 struct dce110_clk_src *clk_src = 539 kzalloc(sizeof(*clk_src), GFP_KERNEL); 540 541 if (!clk_src) 542 return NULL; 543 544 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 545 regs, &cs_shift, &cs_mask)) { 546 clk_src->base.dp_clk_src = dp_clk_src; 547 return &clk_src->base; 548 } 549 550 kfree(clk_src); 551 BREAK_TO_DEBUGGER(); 552 return NULL; 553 } 554 555 static void dce120_clock_source_destroy(struct clock_source **clk_src) 556 { 557 kfree(TO_DCE110_CLK_SRC(*clk_src)); 558 *clk_src = NULL; 559 } 560 561 562 static bool dce120_hw_sequencer_create(struct dc *dc) 563 { 564 /* All registers used by dce11.2 match those in dce11 in offset and 565 * structure 566 */ 567 dce120_hw_sequencer_construct(dc); 568 569 /*TODO Move to separate file and Override what is needed */ 570 571 return true; 572 } 573 574 static struct timing_generator *dce120_timing_generator_create( 575 struct dc_context *ctx, 576 uint32_t instance, 577 const struct dce110_timing_generator_offsets *offsets) 578 { 579 struct dce110_timing_generator *tg110 = 580 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 581 582 if (!tg110) 583 return NULL; 584 585 dce120_timing_generator_construct(tg110, ctx, instance, offsets); 586 return &tg110->base; 587 } 588 589 static void dce120_transform_destroy(struct transform **xfm) 590 { 591 kfree(TO_DCE_TRANSFORM(*xfm)); 592 *xfm = NULL; 593 } 594 595 static void dce120_resource_destruct(struct dce110_resource_pool *pool) 596 { 597 unsigned int i; 598 599 for (i = 0; i < pool->base.pipe_count; i++) { 600 if (pool->base.opps[i] != NULL) 601 dce110_opp_destroy(&pool->base.opps[i]); 602 603 if (pool->base.transforms[i] != NULL) 604 dce120_transform_destroy(&pool->base.transforms[i]); 605 606 if (pool->base.ipps[i] != NULL) 607 dce_ipp_destroy(&pool->base.ipps[i]); 608 609 if (pool->base.mis[i] != NULL) { 610 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 611 pool->base.mis[i] = NULL; 612 } 613 614 if (pool->base.irqs != NULL) { 615 dal_irq_service_destroy(&pool->base.irqs); 616 } 617 618 if (pool->base.timing_generators[i] != NULL) { 619 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 620 pool->base.timing_generators[i] = NULL; 621 } 622 } 623 624 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 625 if (pool->base.engines[i] != NULL) 626 dce110_engine_destroy(&pool->base.engines[i]); 627 if (pool->base.hw_i2cs[i] != NULL) { 628 kfree(pool->base.hw_i2cs[i]); 629 pool->base.hw_i2cs[i] = NULL; 630 } 631 if (pool->base.sw_i2cs[i] != NULL) { 632 kfree(pool->base.sw_i2cs[i]); 633 pool->base.sw_i2cs[i] = NULL; 634 } 635 } 636 637 for (i = 0; i < pool->base.audio_count; i++) { 638 if (pool->base.audios[i]) 639 dce_aud_destroy(&pool->base.audios[i]); 640 } 641 642 for (i = 0; i < pool->base.stream_enc_count; i++) { 643 if (pool->base.stream_enc[i] != NULL) 644 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 645 } 646 647 for (i = 0; i < pool->base.clk_src_count; i++) { 648 if (pool->base.clock_sources[i] != NULL) 649 dce120_clock_source_destroy( 650 &pool->base.clock_sources[i]); 651 } 652 653 if (pool->base.dp_clock_source != NULL) 654 dce120_clock_source_destroy(&pool->base.dp_clock_source); 655 656 if (pool->base.abm != NULL) 657 dce_abm_destroy(&pool->base.abm); 658 659 if (pool->base.dmcu != NULL) 660 dce_dmcu_destroy(&pool->base.dmcu); 661 } 662 663 static void read_dce_straps( 664 struct dc_context *ctx, 665 struct resource_straps *straps) 666 { 667 uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0); 668 669 straps->audio_stream_number = get_reg_field_value(reg_val, 670 CC_DC_MISC_STRAPS, 671 AUDIO_STREAM_NUMBER); 672 straps->hdmi_disable = get_reg_field_value(reg_val, 673 CC_DC_MISC_STRAPS, 674 HDMI_DISABLE); 675 676 reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0); 677 straps->dc_pinstraps_audio = get_reg_field_value(reg_val, 678 DC_PINSTRAPS, 679 DC_PINSTRAPS_AUDIO); 680 } 681 682 static struct audio *create_audio( 683 struct dc_context *ctx, unsigned int inst) 684 { 685 return dce_audio_create(ctx, inst, 686 &audio_regs[inst], &audio_shift, &audio_mask); 687 } 688 689 static const struct encoder_feature_support link_enc_feature = { 690 .max_hdmi_deep_color = COLOR_DEPTH_121212, 691 .max_hdmi_pixel_clock = 600000, 692 .hdmi_ycbcr420_supported = true, 693 .dp_ycbcr420_supported = false, 694 .flags.bits.IS_HBR2_CAPABLE = true, 695 .flags.bits.IS_HBR3_CAPABLE = true, 696 .flags.bits.IS_TPS3_CAPABLE = true, 697 .flags.bits.IS_TPS4_CAPABLE = true, 698 }; 699 700 static struct link_encoder *dce120_link_encoder_create( 701 struct dc_context *ctx, 702 const struct encoder_init_data *enc_init_data) 703 { 704 struct dce110_link_encoder *enc110 = 705 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 706 int link_regs_id; 707 708 if (!enc110) 709 return NULL; 710 711 link_regs_id = 712 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 713 714 dce110_link_encoder_construct(enc110, 715 enc_init_data, 716 &link_enc_feature, 717 &link_enc_regs[link_regs_id], 718 &link_enc_aux_regs[enc_init_data->channel - 1], 719 &link_enc_hpd_regs[enc_init_data->hpd_source]); 720 721 return &enc110->base; 722 } 723 724 static struct panel_cntl *dce120_panel_cntl_create(const struct panel_cntl_init_data *init_data) 725 { 726 struct dce_panel_cntl *panel_cntl = 727 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 728 729 if (!panel_cntl) 730 return NULL; 731 732 dce_panel_cntl_construct(panel_cntl, 733 init_data, 734 &panel_cntl_regs[init_data->inst], 735 &panel_cntl_shift, 736 &panel_cntl_mask); 737 738 return &panel_cntl->base; 739 } 740 741 static struct input_pixel_processor *dce120_ipp_create( 742 struct dc_context *ctx, uint32_t inst) 743 { 744 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 745 746 if (!ipp) { 747 BREAK_TO_DEBUGGER(); 748 return NULL; 749 } 750 751 dce_ipp_construct(ipp, ctx, inst, 752 &ipp_regs[inst], &ipp_shift, &ipp_mask); 753 return &ipp->base; 754 } 755 756 static struct stream_encoder *dce120_stream_encoder_create( 757 enum engine_id eng_id, 758 struct dc_context *ctx) 759 { 760 struct dce110_stream_encoder *enc110 = 761 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 762 763 if (!enc110) 764 return NULL; 765 766 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 767 &stream_enc_regs[eng_id], 768 &se_shift, &se_mask); 769 return &enc110->base; 770 } 771 772 #define SRII(reg_name, block, id)\ 773 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 774 mm ## block ## id ## _ ## reg_name 775 776 static const struct dce_hwseq_registers hwseq_reg = { 777 HWSEQ_DCE120_REG_LIST() 778 }; 779 780 static const struct dce_hwseq_shift hwseq_shift = { 781 HWSEQ_DCE12_MASK_SH_LIST(__SHIFT) 782 }; 783 784 static const struct dce_hwseq_mask hwseq_mask = { 785 HWSEQ_DCE12_MASK_SH_LIST(_MASK) 786 }; 787 788 /* HWSEQ regs for VG20 */ 789 static const struct dce_hwseq_registers dce121_hwseq_reg = { 790 HWSEQ_VG20_REG_LIST() 791 }; 792 793 static const struct dce_hwseq_shift dce121_hwseq_shift = { 794 HWSEQ_VG20_MASK_SH_LIST(__SHIFT) 795 }; 796 797 static const struct dce_hwseq_mask dce121_hwseq_mask = { 798 HWSEQ_VG20_MASK_SH_LIST(_MASK) 799 }; 800 801 static struct dce_hwseq *dce120_hwseq_create( 802 struct dc_context *ctx) 803 { 804 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 805 806 if (hws) { 807 hws->ctx = ctx; 808 hws->regs = &hwseq_reg; 809 hws->shifts = &hwseq_shift; 810 hws->masks = &hwseq_mask; 811 } 812 return hws; 813 } 814 815 static struct dce_hwseq *dce121_hwseq_create( 816 struct dc_context *ctx) 817 { 818 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 819 820 if (hws) { 821 hws->ctx = ctx; 822 hws->regs = &dce121_hwseq_reg; 823 hws->shifts = &dce121_hwseq_shift; 824 hws->masks = &dce121_hwseq_mask; 825 } 826 return hws; 827 } 828 829 static const struct resource_create_funcs res_create_funcs = { 830 .read_dce_straps = read_dce_straps, 831 .create_audio = create_audio, 832 .create_stream_encoder = dce120_stream_encoder_create, 833 .create_hwseq = dce120_hwseq_create, 834 }; 835 836 static const struct resource_create_funcs dce121_res_create_funcs = { 837 .read_dce_straps = read_dce_straps, 838 .create_audio = create_audio, 839 .create_stream_encoder = dce120_stream_encoder_create, 840 .create_hwseq = dce121_hwseq_create, 841 }; 842 843 844 #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) } 845 static const struct dce_mem_input_registers mi_regs[] = { 846 mi_inst_regs(0), 847 mi_inst_regs(1), 848 mi_inst_regs(2), 849 mi_inst_regs(3), 850 mi_inst_regs(4), 851 mi_inst_regs(5), 852 }; 853 854 static const struct dce_mem_input_shift mi_shifts = { 855 MI_DCE12_MASK_SH_LIST(__SHIFT) 856 }; 857 858 static const struct dce_mem_input_mask mi_masks = { 859 MI_DCE12_MASK_SH_LIST(_MASK) 860 }; 861 862 static struct mem_input *dce120_mem_input_create( 863 struct dc_context *ctx, 864 uint32_t inst) 865 { 866 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 867 GFP_KERNEL); 868 869 if (!dce_mi) { 870 BREAK_TO_DEBUGGER(); 871 return NULL; 872 } 873 874 dce120_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 875 return &dce_mi->base; 876 } 877 878 static struct transform *dce120_transform_create( 879 struct dc_context *ctx, 880 uint32_t inst) 881 { 882 struct dce_transform *transform = 883 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 884 885 if (!transform) 886 return NULL; 887 888 dce_transform_construct(transform, ctx, inst, 889 &xfm_regs[inst], &xfm_shift, &xfm_mask); 890 transform->lb_memory_size = 0x1404; /*5124*/ 891 return &transform->base; 892 } 893 894 static void dce120_destroy_resource_pool(struct resource_pool **pool) 895 { 896 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 897 898 dce120_resource_destruct(dce110_pool); 899 kfree(dce110_pool); 900 *pool = NULL; 901 } 902 903 static const struct resource_funcs dce120_res_pool_funcs = { 904 .destroy = dce120_destroy_resource_pool, 905 .link_enc_create = dce120_link_encoder_create, 906 .panel_cntl_create = dce120_panel_cntl_create, 907 .validate_bandwidth = dce112_validate_bandwidth, 908 .validate_plane = dce100_validate_plane, 909 .add_stream_to_ctx = dce112_add_stream_to_ctx, 910 .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link 911 }; 912 913 static void bw_calcs_data_update_from_pplib(struct dc *dc) 914 { 915 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 916 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 917 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; 918 int i; 919 unsigned int clk; 920 unsigned int latency; 921 /*original logic in dal3*/ 922 int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ; 923 924 /*do system clock*/ 925 if (!dm_pp_get_clock_levels_by_type_with_latency( 926 dc->ctx, 927 DM_PP_CLOCK_TYPE_ENGINE_CLK, 928 &eng_clks) || eng_clks.num_levels == 0) { 929 930 eng_clks.num_levels = 8; 931 clk = 300000; 932 933 for (i = 0; i < eng_clks.num_levels; i++) { 934 eng_clks.data[i].clocks_in_khz = clk; 935 clk += 100000; 936 } 937 } 938 939 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ 940 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 941 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); 942 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 943 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); 944 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 945 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); 946 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 947 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); 948 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 949 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); 950 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 951 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); 952 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 953 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); 954 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 955 eng_clks.data[0].clocks_in_khz, 1000); 956 957 /*do memory clock*/ 958 if (!dm_pp_get_clock_levels_by_type_with_latency( 959 dc->ctx, 960 DM_PP_CLOCK_TYPE_MEMORY_CLK, 961 &mem_clks) || mem_clks.num_levels == 0) { 962 963 mem_clks.num_levels = 3; 964 clk = 250000; 965 latency = 45; 966 967 for (i = 0; i < eng_clks.num_levels; i++) { 968 mem_clks.data[i].clocks_in_khz = clk; 969 mem_clks.data[i].latency_in_us = latency; 970 clk += 500000; 971 latency -= 5; 972 } 973 974 } 975 976 /* we don't need to call PPLIB for validation clock since they 977 * also give us the highest sclk and highest mclk (UMA clock). 978 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): 979 * YCLK = UMACLK*m_memoryTypeMultiplier 980 */ 981 if (dc->bw_vbios->memory_type == bw_def_hbm) 982 memory_type_multiplier = MEMORY_TYPE_HBM; 983 984 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 985 mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000); 986 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 987 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier, 988 1000); 989 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 990 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier, 991 1000); 992 993 /* Now notify PPLib/SMU about which Watermarks sets they should select 994 * depending on DPM state they are in. And update BW MGR GFX Engine and 995 * Memory clock member variables for Watermarks calculations for each 996 * Watermark Set 997 */ 998 clk_ranges.num_wm_sets = 4; 999 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; 1000 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = 1001 eng_clks.data[0].clocks_in_khz; 1002 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = 1003 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 1004 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz = 1005 mem_clks.data[0].clocks_in_khz; 1006 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = 1007 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 1008 1009 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; 1010 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = 1011 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 1012 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 1013 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; 1014 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz = 1015 mem_clks.data[0].clocks_in_khz; 1016 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = 1017 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 1018 1019 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; 1020 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = 1021 eng_clks.data[0].clocks_in_khz; 1022 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = 1023 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 1024 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz = 1025 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 1026 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 1027 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; 1028 1029 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; 1030 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = 1031 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 1032 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 1033 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; 1034 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz = 1035 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 1036 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 1037 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; 1038 1039 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 1040 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); 1041 } 1042 1043 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1044 { 1045 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); 1046 /* VG20 support max 6 pipes */ 1047 value = value & 0x3f; 1048 return value; 1049 } 1050 1051 static bool dce120_resource_construct( 1052 uint8_t num_virtual_links, 1053 struct dc *dc, 1054 struct dce110_resource_pool *pool) 1055 { 1056 unsigned int i; 1057 int j; 1058 struct dc_context *ctx = dc->ctx; 1059 struct irq_service_init_data irq_init_data; 1060 static const struct resource_create_funcs *res_funcs; 1061 bool is_vg20 = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev); 1062 uint32_t pipe_fuses; 1063 1064 ctx->dc_bios->regs = &bios_regs; 1065 1066 pool->base.res_cap = &res_cap; 1067 pool->base.funcs = &dce120_res_pool_funcs; 1068 1069 /* TODO: Fill more data from GreenlandAsicCapability.cpp */ 1070 pool->base.pipe_count = res_cap.num_timing_generator; 1071 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1072 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1073 1074 dc->caps.max_downscale_ratio = 200; 1075 dc->caps.i2c_speed_in_khz = 100; 1076 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/ 1077 dc->caps.max_cursor_size = 128; 1078 dc->caps.min_horizontal_blanking_period = 80; 1079 dc->caps.dual_link_dvi = true; 1080 dc->caps.psp_setup_panel_mode = true; 1081 dc->caps.extended_aux_timeout_support = false; 1082 dc->debug = debug_defaults; 1083 1084 /************************************************* 1085 * Create resources * 1086 *************************************************/ 1087 1088 pool->base.clock_sources[DCE120_CLK_SRC_PLL0] = 1089 dce120_clock_source_create(ctx, ctx->dc_bios, 1090 CLOCK_SOURCE_COMBO_PHY_PLL0, 1091 &clk_src_regs[0], false); 1092 pool->base.clock_sources[DCE120_CLK_SRC_PLL1] = 1093 dce120_clock_source_create(ctx, ctx->dc_bios, 1094 CLOCK_SOURCE_COMBO_PHY_PLL1, 1095 &clk_src_regs[1], false); 1096 pool->base.clock_sources[DCE120_CLK_SRC_PLL2] = 1097 dce120_clock_source_create(ctx, ctx->dc_bios, 1098 CLOCK_SOURCE_COMBO_PHY_PLL2, 1099 &clk_src_regs[2], false); 1100 pool->base.clock_sources[DCE120_CLK_SRC_PLL3] = 1101 dce120_clock_source_create(ctx, ctx->dc_bios, 1102 CLOCK_SOURCE_COMBO_PHY_PLL3, 1103 &clk_src_regs[3], false); 1104 pool->base.clock_sources[DCE120_CLK_SRC_PLL4] = 1105 dce120_clock_source_create(ctx, ctx->dc_bios, 1106 CLOCK_SOURCE_COMBO_PHY_PLL4, 1107 &clk_src_regs[4], false); 1108 pool->base.clock_sources[DCE120_CLK_SRC_PLL5] = 1109 dce120_clock_source_create(ctx, ctx->dc_bios, 1110 CLOCK_SOURCE_COMBO_PHY_PLL5, 1111 &clk_src_regs[5], false); 1112 pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL; 1113 1114 pool->base.dp_clock_source = 1115 dce120_clock_source_create(ctx, ctx->dc_bios, 1116 CLOCK_SOURCE_ID_DP_DTO, 1117 &clk_src_regs[0], true); 1118 1119 for (i = 0; i < pool->base.clk_src_count; i++) { 1120 if (pool->base.clock_sources[i] == NULL) { 1121 dm_error("DC: failed to create clock sources!\n"); 1122 BREAK_TO_DEBUGGER(); 1123 goto clk_src_create_fail; 1124 } 1125 } 1126 1127 pool->base.dmcu = dce_dmcu_create(ctx, 1128 &dmcu_regs, 1129 &dmcu_shift, 1130 &dmcu_mask); 1131 if (pool->base.dmcu == NULL) { 1132 dm_error("DC: failed to create dmcu!\n"); 1133 BREAK_TO_DEBUGGER(); 1134 goto res_create_fail; 1135 } 1136 1137 pool->base.abm = dce_abm_create(ctx, 1138 &abm_regs, 1139 &abm_shift, 1140 &abm_mask); 1141 if (pool->base.abm == NULL) { 1142 dm_error("DC: failed to create abm!\n"); 1143 BREAK_TO_DEBUGGER(); 1144 goto res_create_fail; 1145 } 1146 1147 1148 irq_init_data.ctx = dc->ctx; 1149 pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data); 1150 if (!pool->base.irqs) 1151 goto irqs_create_fail; 1152 1153 /* VG20: Pipe harvesting enabled, retrieve valid pipe fuses */ 1154 if (is_vg20) 1155 pipe_fuses = read_pipe_fuses(ctx); 1156 1157 /* index to valid pipe resource */ 1158 j = 0; 1159 for (i = 0; i < pool->base.pipe_count; i++) { 1160 if (is_vg20) { 1161 if ((pipe_fuses & (1 << i)) != 0) { 1162 dm_error("DC: skip invalid pipe %d!\n", i); 1163 continue; 1164 } 1165 } 1166 1167 pool->base.timing_generators[j] = 1168 dce120_timing_generator_create( 1169 ctx, 1170 i, 1171 &dce120_tg_offsets[i]); 1172 if (pool->base.timing_generators[j] == NULL) { 1173 BREAK_TO_DEBUGGER(); 1174 dm_error("DC: failed to create tg!\n"); 1175 goto controller_create_fail; 1176 } 1177 1178 pool->base.mis[j] = dce120_mem_input_create(ctx, i); 1179 1180 if (pool->base.mis[j] == NULL) { 1181 BREAK_TO_DEBUGGER(); 1182 dm_error( 1183 "DC: failed to create memory input!\n"); 1184 goto controller_create_fail; 1185 } 1186 1187 pool->base.ipps[j] = dce120_ipp_create(ctx, i); 1188 if (pool->base.ipps[i] == NULL) { 1189 BREAK_TO_DEBUGGER(); 1190 dm_error( 1191 "DC: failed to create input pixel processor!\n"); 1192 goto controller_create_fail; 1193 } 1194 1195 pool->base.transforms[j] = dce120_transform_create(ctx, i); 1196 if (pool->base.transforms[i] == NULL) { 1197 BREAK_TO_DEBUGGER(); 1198 dm_error( 1199 "DC: failed to create transform!\n"); 1200 goto res_create_fail; 1201 } 1202 1203 pool->base.opps[j] = dce120_opp_create( 1204 ctx, 1205 i); 1206 if (pool->base.opps[j] == NULL) { 1207 BREAK_TO_DEBUGGER(); 1208 dm_error( 1209 "DC: failed to create output pixel processor!\n"); 1210 } 1211 1212 /* check next valid pipe */ 1213 j++; 1214 } 1215 1216 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1217 pool->base.engines[i] = dce120_aux_engine_create(ctx, i); 1218 if (pool->base.engines[i] == NULL) { 1219 BREAK_TO_DEBUGGER(); 1220 dm_error( 1221 "DC:failed to create aux engine!!\n"); 1222 goto res_create_fail; 1223 } 1224 pool->base.hw_i2cs[i] = dce120_i2c_hw_create(ctx, i); 1225 if (pool->base.hw_i2cs[i] == NULL) { 1226 BREAK_TO_DEBUGGER(); 1227 dm_error( 1228 "DC:failed to create i2c engine!!\n"); 1229 goto res_create_fail; 1230 } 1231 pool->base.sw_i2cs[i] = NULL; 1232 } 1233 1234 /* valid pipe num */ 1235 pool->base.pipe_count = j; 1236 pool->base.timing_generator_count = j; 1237 1238 if (is_vg20) 1239 res_funcs = &dce121_res_create_funcs; 1240 else 1241 res_funcs = &res_create_funcs; 1242 1243 if (!resource_construct(num_virtual_links, dc, &pool->base, res_funcs)) 1244 goto res_create_fail; 1245 1246 /* Create hardware sequencer */ 1247 if (!dce120_hw_sequencer_create(dc)) 1248 goto controller_create_fail; 1249 1250 dc->caps.max_planes = pool->base.pipe_count; 1251 1252 for (i = 0; i < dc->caps.max_planes; ++i) 1253 dc->caps.planes[i] = plane_cap; 1254 1255 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1256 1257 bw_calcs_data_update_from_pplib(dc); 1258 1259 return true; 1260 1261 irqs_create_fail: 1262 controller_create_fail: 1263 clk_src_create_fail: 1264 res_create_fail: 1265 1266 dce120_resource_destruct(pool); 1267 1268 return false; 1269 } 1270 1271 struct resource_pool *dce120_create_resource_pool( 1272 uint8_t num_virtual_links, 1273 struct dc *dc) 1274 { 1275 struct dce110_resource_pool *pool = 1276 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1277 1278 if (!pool) 1279 return NULL; 1280 1281 if (dce120_resource_construct(num_virtual_links, dc, pool)) 1282 return &pool->base; 1283 1284 kfree(pool); 1285 BREAK_TO_DEBUGGER(); 1286 return NULL; 1287 } 1288