1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc.cls 3 * 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include <linux/slab.h> 28 29 #include "dm_services.h" 30 31 32 #include "stream_encoder.h" 33 #include "resource.h" 34 #include "include/irq_service_interface.h" 35 #include "dce120_resource.h" 36 37 #include "dce112/dce112_resource.h" 38 39 #include "dce110/dce110_resource.h" 40 #include "../virtual/virtual_stream_encoder.h" 41 #include "dce120_timing_generator.h" 42 #include "irq/dce120/irq_service_dce120.h" 43 #include "dce/dce_opp.h" 44 #include "dce/dce_clock_source.h" 45 #include "dce/dce_ipp.h" 46 #include "dce/dce_mem_input.h" 47 48 #include "dce110/dce110_hw_sequencer.h" 49 #include "dce120/dce120_hw_sequencer.h" 50 #include "dce/dce_transform.h" 51 #include "clk_mgr.h" 52 #include "dce/dce_audio.h" 53 #include "dce/dce_link_encoder.h" 54 #include "dce/dce_stream_encoder.h" 55 #include "dce/dce_hwseq.h" 56 #include "dce/dce_abm.h" 57 #include "dce/dce_dmcu.h" 58 #include "dce/dce_aux.h" 59 #include "dce/dce_i2c.h" 60 61 #include "dce/dce_12_0_offset.h" 62 #include "dce/dce_12_0_sh_mask.h" 63 #include "soc15_hw_ip.h" 64 #include "vega10_ip_offset.h" 65 #include "nbio/nbio_6_1_offset.h" 66 #include "mmhub/mmhub_9_4_0_offset.h" 67 #include "mmhub/mmhub_9_4_0_sh_mask.h" 68 #include "reg_helper.h" 69 70 #include "dce100/dce100_resource.h" 71 72 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 73 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 74 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 75 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 76 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 77 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 78 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 79 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 80 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 81 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 82 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 83 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 84 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 85 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 86 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 87 #endif 88 89 enum dce120_clk_src_array_id { 90 DCE120_CLK_SRC_PLL0, 91 DCE120_CLK_SRC_PLL1, 92 DCE120_CLK_SRC_PLL2, 93 DCE120_CLK_SRC_PLL3, 94 DCE120_CLK_SRC_PLL4, 95 DCE120_CLK_SRC_PLL5, 96 97 DCE120_CLK_SRC_TOTAL 98 }; 99 100 static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = { 101 { 102 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 103 }, 104 { 105 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 106 }, 107 { 108 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 109 }, 110 { 111 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 112 }, 113 { 114 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 115 }, 116 { 117 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 118 } 119 }; 120 121 /* begin ********************* 122 * macros to expend register list macro defined in HW object header file */ 123 124 #define BASE_INNER(seg) \ 125 DCE_BASE__INST0_SEG ## seg 126 127 #define NBIO_BASE_INNER(seg) \ 128 NBIF_BASE__INST0_SEG ## seg 129 130 #define NBIO_BASE(seg) \ 131 NBIO_BASE_INNER(seg) 132 133 /* compile time expand base address. */ 134 #define BASE(seg) \ 135 BASE_INNER(seg) 136 137 #define SR(reg_name)\ 138 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 139 mm ## reg_name 140 141 #define SRI(reg_name, block, id)\ 142 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 143 mm ## block ## id ## _ ## reg_name 144 145 /* MMHUB */ 146 #define MMHUB_BASE_INNER(seg) \ 147 MMHUB_BASE__INST0_SEG ## seg 148 149 #define MMHUB_BASE(seg) \ 150 MMHUB_BASE_INNER(seg) 151 152 #define MMHUB_SR(reg_name)\ 153 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 154 mm ## reg_name 155 156 /* macros to expend register list macro defined in HW object header file 157 * end *********************/ 158 159 160 static const struct dce_dmcu_registers dmcu_regs = { 161 DMCU_DCE110_COMMON_REG_LIST() 162 }; 163 164 static const struct dce_dmcu_shift dmcu_shift = { 165 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 166 }; 167 168 static const struct dce_dmcu_mask dmcu_mask = { 169 DMCU_MASK_SH_LIST_DCE110(_MASK) 170 }; 171 172 static const struct dce_abm_registers abm_regs = { 173 ABM_DCE110_COMMON_REG_LIST() 174 }; 175 176 static const struct dce_abm_shift abm_shift = { 177 ABM_MASK_SH_LIST_DCE110(__SHIFT) 178 }; 179 180 static const struct dce_abm_mask abm_mask = { 181 ABM_MASK_SH_LIST_DCE110(_MASK) 182 }; 183 184 #define ipp_regs(id)\ 185 [id] = {\ 186 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 187 } 188 189 static const struct dce_ipp_registers ipp_regs[] = { 190 ipp_regs(0), 191 ipp_regs(1), 192 ipp_regs(2), 193 ipp_regs(3), 194 ipp_regs(4), 195 ipp_regs(5) 196 }; 197 198 static const struct dce_ipp_shift ipp_shift = { 199 IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT) 200 }; 201 202 static const struct dce_ipp_mask ipp_mask = { 203 IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK) 204 }; 205 206 #define transform_regs(id)\ 207 [id] = {\ 208 XFM_COMMON_REG_LIST_DCE110(id)\ 209 } 210 211 static const struct dce_transform_registers xfm_regs[] = { 212 transform_regs(0), 213 transform_regs(1), 214 transform_regs(2), 215 transform_regs(3), 216 transform_regs(4), 217 transform_regs(5) 218 }; 219 220 static const struct dce_transform_shift xfm_shift = { 221 XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT) 222 }; 223 224 static const struct dce_transform_mask xfm_mask = { 225 XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK) 226 }; 227 228 #define aux_regs(id)\ 229 [id] = {\ 230 AUX_REG_LIST(id)\ 231 } 232 233 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 234 aux_regs(0), 235 aux_regs(1), 236 aux_regs(2), 237 aux_regs(3), 238 aux_regs(4), 239 aux_regs(5) 240 }; 241 242 #define hpd_regs(id)\ 243 [id] = {\ 244 HPD_REG_LIST(id)\ 245 } 246 247 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 248 hpd_regs(0), 249 hpd_regs(1), 250 hpd_regs(2), 251 hpd_regs(3), 252 hpd_regs(4), 253 hpd_regs(5) 254 }; 255 256 #define link_regs(id)\ 257 [id] = {\ 258 LE_DCE120_REG_LIST(id), \ 259 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 260 } 261 262 static const struct dce110_link_enc_registers link_enc_regs[] = { 263 link_regs(0), 264 link_regs(1), 265 link_regs(2), 266 link_regs(3), 267 link_regs(4), 268 link_regs(5), 269 link_regs(6), 270 }; 271 272 273 #define stream_enc_regs(id)\ 274 [id] = {\ 275 SE_COMMON_REG_LIST(id),\ 276 .TMDS_CNTL = 0,\ 277 } 278 279 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 280 stream_enc_regs(0), 281 stream_enc_regs(1), 282 stream_enc_regs(2), 283 stream_enc_regs(3), 284 stream_enc_regs(4), 285 stream_enc_regs(5) 286 }; 287 288 static const struct dce_stream_encoder_shift se_shift = { 289 SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT) 290 }; 291 292 static const struct dce_stream_encoder_mask se_mask = { 293 SE_COMMON_MASK_SH_LIST_DCE120(_MASK) 294 }; 295 296 #define opp_regs(id)\ 297 [id] = {\ 298 OPP_DCE_120_REG_LIST(id),\ 299 } 300 301 static const struct dce_opp_registers opp_regs[] = { 302 opp_regs(0), 303 opp_regs(1), 304 opp_regs(2), 305 opp_regs(3), 306 opp_regs(4), 307 opp_regs(5) 308 }; 309 310 static const struct dce_opp_shift opp_shift = { 311 OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT) 312 }; 313 314 static const struct dce_opp_mask opp_mask = { 315 OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK) 316 }; 317 #define aux_engine_regs(id)\ 318 [id] = {\ 319 AUX_COMMON_REG_LIST(id), \ 320 .AUX_RESET_MASK = 0 \ 321 } 322 323 static const struct dce110_aux_registers aux_engine_regs[] = { 324 aux_engine_regs(0), 325 aux_engine_regs(1), 326 aux_engine_regs(2), 327 aux_engine_regs(3), 328 aux_engine_regs(4), 329 aux_engine_regs(5) 330 }; 331 332 #define audio_regs(id)\ 333 [id] = {\ 334 AUD_COMMON_REG_LIST(id)\ 335 } 336 337 static const struct dce_audio_registers audio_regs[] = { 338 audio_regs(0), 339 audio_regs(1), 340 audio_regs(2), 341 audio_regs(3), 342 audio_regs(4), 343 audio_regs(5) 344 }; 345 346 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 347 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 348 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 349 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 350 351 static const struct dce_audio_shift audio_shift = { 352 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 353 }; 354 355 static const struct dce_audio_mask audio_mask = { 356 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 357 }; 358 359 #define clk_src_regs(index, id)\ 360 [index] = {\ 361 CS_COMMON_REG_LIST_DCE_112(id),\ 362 } 363 364 static const struct dce110_clk_src_regs clk_src_regs[] = { 365 clk_src_regs(0, A), 366 clk_src_regs(1, B), 367 clk_src_regs(2, C), 368 clk_src_regs(3, D), 369 clk_src_regs(4, E), 370 clk_src_regs(5, F) 371 }; 372 373 static const struct dce110_clk_src_shift cs_shift = { 374 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 375 }; 376 377 static const struct dce110_clk_src_mask cs_mask = { 378 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) 379 }; 380 381 struct output_pixel_processor *dce120_opp_create( 382 struct dc_context *ctx, 383 uint32_t inst) 384 { 385 struct dce110_opp *opp = 386 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 387 388 if (!opp) 389 return NULL; 390 391 dce110_opp_construct(opp, 392 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 393 return &opp->base; 394 } 395 struct dce_aux *dce120_aux_engine_create( 396 struct dc_context *ctx, 397 uint32_t inst) 398 { 399 struct aux_engine_dce110 *aux_engine = 400 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 401 402 if (!aux_engine) 403 return NULL; 404 405 dce110_aux_engine_construct(aux_engine, ctx, inst, 406 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 407 &aux_engine_regs[inst]); 408 409 return &aux_engine->base; 410 } 411 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 412 413 static const struct dce_i2c_registers i2c_hw_regs[] = { 414 i2c_inst_regs(1), 415 i2c_inst_regs(2), 416 i2c_inst_regs(3), 417 i2c_inst_regs(4), 418 i2c_inst_regs(5), 419 i2c_inst_regs(6), 420 }; 421 422 static const struct dce_i2c_shift i2c_shifts = { 423 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 424 }; 425 426 static const struct dce_i2c_mask i2c_masks = { 427 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 428 }; 429 430 struct dce_i2c_hw *dce120_i2c_hw_create( 431 struct dc_context *ctx, 432 uint32_t inst) 433 { 434 struct dce_i2c_hw *dce_i2c_hw = 435 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 436 437 if (!dce_i2c_hw) 438 return NULL; 439 440 dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst, 441 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 442 443 return dce_i2c_hw; 444 } 445 static const struct bios_registers bios_regs = { 446 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + NBIO_BASE(mmBIOS_SCRATCH_3_BASE_IDX), 447 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX) 448 }; 449 450 static const struct resource_caps res_cap = { 451 .num_timing_generator = 6, 452 .num_audio = 7, 453 .num_stream_encoder = 6, 454 .num_pll = 6, 455 .num_ddc = 6, 456 }; 457 458 static const struct dc_plane_cap plane_cap = { 459 .type = DC_PLANE_TYPE_DCE_RGB, 460 461 .pixel_format_support = { 462 .argb8888 = true, 463 .nv12 = false, 464 .fp16 = false 465 }, 466 467 .max_upscale_factor = { 468 .argb8888 = 16000, 469 .nv12 = 1, 470 .fp16 = 1 471 }, 472 473 .max_downscale_factor = { 474 .argb8888 = 250, 475 .nv12 = 1, 476 .fp16 = 1 477 } 478 }; 479 480 static const struct dc_debug_options debug_defaults = { 481 .disable_clock_gate = true, 482 }; 483 484 static struct clock_source *dce120_clock_source_create( 485 struct dc_context *ctx, 486 struct dc_bios *bios, 487 enum clock_source_id id, 488 const struct dce110_clk_src_regs *regs, 489 bool dp_clk_src) 490 { 491 struct dce110_clk_src *clk_src = 492 kzalloc(sizeof(*clk_src), GFP_KERNEL); 493 494 if (!clk_src) 495 return NULL; 496 497 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 498 regs, &cs_shift, &cs_mask)) { 499 clk_src->base.dp_clk_src = dp_clk_src; 500 return &clk_src->base; 501 } 502 503 kfree(clk_src); 504 BREAK_TO_DEBUGGER(); 505 return NULL; 506 } 507 508 static void dce120_clock_source_destroy(struct clock_source **clk_src) 509 { 510 kfree(TO_DCE110_CLK_SRC(*clk_src)); 511 *clk_src = NULL; 512 } 513 514 515 static bool dce120_hw_sequencer_create(struct dc *dc) 516 { 517 /* All registers used by dce11.2 match those in dce11 in offset and 518 * structure 519 */ 520 dce120_hw_sequencer_construct(dc); 521 522 /*TODO Move to separate file and Override what is needed */ 523 524 return true; 525 } 526 527 static struct timing_generator *dce120_timing_generator_create( 528 struct dc_context *ctx, 529 uint32_t instance, 530 const struct dce110_timing_generator_offsets *offsets) 531 { 532 struct dce110_timing_generator *tg110 = 533 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 534 535 if (!tg110) 536 return NULL; 537 538 dce120_timing_generator_construct(tg110, ctx, instance, offsets); 539 return &tg110->base; 540 } 541 542 static void dce120_transform_destroy(struct transform **xfm) 543 { 544 kfree(TO_DCE_TRANSFORM(*xfm)); 545 *xfm = NULL; 546 } 547 548 static void destruct(struct dce110_resource_pool *pool) 549 { 550 unsigned int i; 551 552 for (i = 0; i < pool->base.pipe_count; i++) { 553 if (pool->base.opps[i] != NULL) 554 dce110_opp_destroy(&pool->base.opps[i]); 555 556 if (pool->base.transforms[i] != NULL) 557 dce120_transform_destroy(&pool->base.transforms[i]); 558 559 if (pool->base.ipps[i] != NULL) 560 dce_ipp_destroy(&pool->base.ipps[i]); 561 562 if (pool->base.mis[i] != NULL) { 563 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 564 pool->base.mis[i] = NULL; 565 } 566 567 if (pool->base.irqs != NULL) { 568 dal_irq_service_destroy(&pool->base.irqs); 569 } 570 571 if (pool->base.timing_generators[i] != NULL) { 572 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 573 pool->base.timing_generators[i] = NULL; 574 } 575 } 576 577 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 578 if (pool->base.engines[i] != NULL) 579 dce110_engine_destroy(&pool->base.engines[i]); 580 if (pool->base.hw_i2cs[i] != NULL) { 581 kfree(pool->base.hw_i2cs[i]); 582 pool->base.hw_i2cs[i] = NULL; 583 } 584 if (pool->base.sw_i2cs[i] != NULL) { 585 kfree(pool->base.sw_i2cs[i]); 586 pool->base.sw_i2cs[i] = NULL; 587 } 588 } 589 590 for (i = 0; i < pool->base.audio_count; i++) { 591 if (pool->base.audios[i]) 592 dce_aud_destroy(&pool->base.audios[i]); 593 } 594 595 for (i = 0; i < pool->base.stream_enc_count; i++) { 596 if (pool->base.stream_enc[i] != NULL) 597 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 598 } 599 600 for (i = 0; i < pool->base.clk_src_count; i++) { 601 if (pool->base.clock_sources[i] != NULL) 602 dce120_clock_source_destroy( 603 &pool->base.clock_sources[i]); 604 } 605 606 if (pool->base.dp_clock_source != NULL) 607 dce120_clock_source_destroy(&pool->base.dp_clock_source); 608 609 if (pool->base.abm != NULL) 610 dce_abm_destroy(&pool->base.abm); 611 612 if (pool->base.dmcu != NULL) 613 dce_dmcu_destroy(&pool->base.dmcu); 614 } 615 616 static void read_dce_straps( 617 struct dc_context *ctx, 618 struct resource_straps *straps) 619 { 620 uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0); 621 622 straps->audio_stream_number = get_reg_field_value(reg_val, 623 CC_DC_MISC_STRAPS, 624 AUDIO_STREAM_NUMBER); 625 straps->hdmi_disable = get_reg_field_value(reg_val, 626 CC_DC_MISC_STRAPS, 627 HDMI_DISABLE); 628 629 reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0); 630 straps->dc_pinstraps_audio = get_reg_field_value(reg_val, 631 DC_PINSTRAPS, 632 DC_PINSTRAPS_AUDIO); 633 } 634 635 static struct audio *create_audio( 636 struct dc_context *ctx, unsigned int inst) 637 { 638 return dce_audio_create(ctx, inst, 639 &audio_regs[inst], &audio_shift, &audio_mask); 640 } 641 642 static const struct encoder_feature_support link_enc_feature = { 643 .max_hdmi_deep_color = COLOR_DEPTH_121212, 644 .max_hdmi_pixel_clock = 600000, 645 .hdmi_ycbcr420_supported = true, 646 .dp_ycbcr420_supported = false, 647 .flags.bits.IS_HBR2_CAPABLE = true, 648 .flags.bits.IS_HBR3_CAPABLE = true, 649 .flags.bits.IS_TPS3_CAPABLE = true, 650 .flags.bits.IS_TPS4_CAPABLE = true, 651 }; 652 653 static struct link_encoder *dce120_link_encoder_create( 654 const struct encoder_init_data *enc_init_data) 655 { 656 struct dce110_link_encoder *enc110 = 657 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 658 659 if (!enc110) 660 return NULL; 661 662 dce110_link_encoder_construct(enc110, 663 enc_init_data, 664 &link_enc_feature, 665 &link_enc_regs[enc_init_data->transmitter], 666 &link_enc_aux_regs[enc_init_data->channel - 1], 667 &link_enc_hpd_regs[enc_init_data->hpd_source]); 668 669 return &enc110->base; 670 } 671 672 static struct input_pixel_processor *dce120_ipp_create( 673 struct dc_context *ctx, uint32_t inst) 674 { 675 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 676 677 if (!ipp) { 678 BREAK_TO_DEBUGGER(); 679 return NULL; 680 } 681 682 dce_ipp_construct(ipp, ctx, inst, 683 &ipp_regs[inst], &ipp_shift, &ipp_mask); 684 return &ipp->base; 685 } 686 687 static struct stream_encoder *dce120_stream_encoder_create( 688 enum engine_id eng_id, 689 struct dc_context *ctx) 690 { 691 struct dce110_stream_encoder *enc110 = 692 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 693 694 if (!enc110) 695 return NULL; 696 697 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 698 &stream_enc_regs[eng_id], 699 &se_shift, &se_mask); 700 return &enc110->base; 701 } 702 703 #define SRII(reg_name, block, id)\ 704 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 705 mm ## block ## id ## _ ## reg_name 706 707 static const struct dce_hwseq_registers hwseq_reg = { 708 HWSEQ_DCE120_REG_LIST() 709 }; 710 711 static const struct dce_hwseq_shift hwseq_shift = { 712 HWSEQ_DCE12_MASK_SH_LIST(__SHIFT) 713 }; 714 715 static const struct dce_hwseq_mask hwseq_mask = { 716 HWSEQ_DCE12_MASK_SH_LIST(_MASK) 717 }; 718 719 /* HWSEQ regs for VG20 */ 720 static const struct dce_hwseq_registers dce121_hwseq_reg = { 721 HWSEQ_VG20_REG_LIST() 722 }; 723 724 static const struct dce_hwseq_shift dce121_hwseq_shift = { 725 HWSEQ_VG20_MASK_SH_LIST(__SHIFT) 726 }; 727 728 static const struct dce_hwseq_mask dce121_hwseq_mask = { 729 HWSEQ_VG20_MASK_SH_LIST(_MASK) 730 }; 731 732 static struct dce_hwseq *dce120_hwseq_create( 733 struct dc_context *ctx) 734 { 735 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 736 737 if (hws) { 738 hws->ctx = ctx; 739 hws->regs = &hwseq_reg; 740 hws->shifts = &hwseq_shift; 741 hws->masks = &hwseq_mask; 742 } 743 return hws; 744 } 745 746 static struct dce_hwseq *dce121_hwseq_create( 747 struct dc_context *ctx) 748 { 749 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 750 751 if (hws) { 752 hws->ctx = ctx; 753 hws->regs = &dce121_hwseq_reg; 754 hws->shifts = &dce121_hwseq_shift; 755 hws->masks = &dce121_hwseq_mask; 756 } 757 return hws; 758 } 759 760 static const struct resource_create_funcs res_create_funcs = { 761 .read_dce_straps = read_dce_straps, 762 .create_audio = create_audio, 763 .create_stream_encoder = dce120_stream_encoder_create, 764 .create_hwseq = dce120_hwseq_create, 765 }; 766 767 static const struct resource_create_funcs dce121_res_create_funcs = { 768 .read_dce_straps = read_dce_straps, 769 .create_audio = create_audio, 770 .create_stream_encoder = dce120_stream_encoder_create, 771 .create_hwseq = dce121_hwseq_create, 772 }; 773 774 775 #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) } 776 static const struct dce_mem_input_registers mi_regs[] = { 777 mi_inst_regs(0), 778 mi_inst_regs(1), 779 mi_inst_regs(2), 780 mi_inst_regs(3), 781 mi_inst_regs(4), 782 mi_inst_regs(5), 783 }; 784 785 static const struct dce_mem_input_shift mi_shifts = { 786 MI_DCE12_MASK_SH_LIST(__SHIFT) 787 }; 788 789 static const struct dce_mem_input_mask mi_masks = { 790 MI_DCE12_MASK_SH_LIST(_MASK) 791 }; 792 793 static struct mem_input *dce120_mem_input_create( 794 struct dc_context *ctx, 795 uint32_t inst) 796 { 797 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 798 GFP_KERNEL); 799 800 if (!dce_mi) { 801 BREAK_TO_DEBUGGER(); 802 return NULL; 803 } 804 805 dce120_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 806 return &dce_mi->base; 807 } 808 809 static struct transform *dce120_transform_create( 810 struct dc_context *ctx, 811 uint32_t inst) 812 { 813 struct dce_transform *transform = 814 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 815 816 if (!transform) 817 return NULL; 818 819 dce_transform_construct(transform, ctx, inst, 820 &xfm_regs[inst], &xfm_shift, &xfm_mask); 821 transform->lb_memory_size = 0x1404; /*5124*/ 822 return &transform->base; 823 } 824 825 static void dce120_destroy_resource_pool(struct resource_pool **pool) 826 { 827 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 828 829 destruct(dce110_pool); 830 kfree(dce110_pool); 831 *pool = NULL; 832 } 833 834 static const struct resource_funcs dce120_res_pool_funcs = { 835 .destroy = dce120_destroy_resource_pool, 836 .link_enc_create = dce120_link_encoder_create, 837 .validate_bandwidth = dce112_validate_bandwidth, 838 .validate_plane = dce100_validate_plane, 839 .add_stream_to_ctx = dce112_add_stream_to_ctx, 840 .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link 841 }; 842 843 static void bw_calcs_data_update_from_pplib(struct dc *dc) 844 { 845 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 846 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 847 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; 848 int i; 849 unsigned int clk; 850 unsigned int latency; 851 /*original logic in dal3*/ 852 int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ; 853 854 /*do system clock*/ 855 if (!dm_pp_get_clock_levels_by_type_with_latency( 856 dc->ctx, 857 DM_PP_CLOCK_TYPE_ENGINE_CLK, 858 &eng_clks) || eng_clks.num_levels == 0) { 859 860 eng_clks.num_levels = 8; 861 clk = 300000; 862 863 for (i = 0; i < eng_clks.num_levels; i++) { 864 eng_clks.data[i].clocks_in_khz = clk; 865 clk += 100000; 866 } 867 } 868 869 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ 870 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 871 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); 872 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 873 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); 874 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 875 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); 876 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 877 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); 878 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 879 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); 880 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 881 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); 882 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 883 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); 884 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 885 eng_clks.data[0].clocks_in_khz, 1000); 886 887 /*do memory clock*/ 888 if (!dm_pp_get_clock_levels_by_type_with_latency( 889 dc->ctx, 890 DM_PP_CLOCK_TYPE_MEMORY_CLK, 891 &mem_clks) || mem_clks.num_levels == 0) { 892 893 mem_clks.num_levels = 3; 894 clk = 250000; 895 latency = 45; 896 897 for (i = 0; i < eng_clks.num_levels; i++) { 898 mem_clks.data[i].clocks_in_khz = clk; 899 mem_clks.data[i].latency_in_us = latency; 900 clk += 500000; 901 latency -= 5; 902 } 903 904 } 905 906 /* we don't need to call PPLIB for validation clock since they 907 * also give us the highest sclk and highest mclk (UMA clock). 908 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): 909 * YCLK = UMACLK*m_memoryTypeMultiplier 910 */ 911 if (dc->bw_vbios->memory_type == bw_def_hbm) 912 memory_type_multiplier = MEMORY_TYPE_HBM; 913 914 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 915 mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000); 916 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 917 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier, 918 1000); 919 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 920 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier, 921 1000); 922 923 /* Now notify PPLib/SMU about which Watermarks sets they should select 924 * depending on DPM state they are in. And update BW MGR GFX Engine and 925 * Memory clock member variables for Watermarks calculations for each 926 * Watermark Set 927 */ 928 clk_ranges.num_wm_sets = 4; 929 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; 930 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = 931 eng_clks.data[0].clocks_in_khz; 932 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = 933 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 934 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz = 935 mem_clks.data[0].clocks_in_khz; 936 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = 937 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 938 939 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; 940 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = 941 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 942 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 943 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; 944 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz = 945 mem_clks.data[0].clocks_in_khz; 946 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = 947 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 948 949 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; 950 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = 951 eng_clks.data[0].clocks_in_khz; 952 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = 953 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 954 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz = 955 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 956 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 957 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; 958 959 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; 960 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = 961 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 962 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 963 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; 964 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz = 965 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 966 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 967 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; 968 969 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 970 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); 971 } 972 973 static uint32_t read_pipe_fuses(struct dc_context *ctx) 974 { 975 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); 976 /* VG20 support max 6 pipes */ 977 value = value & 0x3f; 978 return value; 979 } 980 981 static bool construct( 982 uint8_t num_virtual_links, 983 struct dc *dc, 984 struct dce110_resource_pool *pool) 985 { 986 unsigned int i; 987 int j; 988 struct dc_context *ctx = dc->ctx; 989 struct irq_service_init_data irq_init_data; 990 static const struct resource_create_funcs *res_funcs; 991 bool is_vg20 = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev); 992 uint32_t pipe_fuses; 993 994 ctx->dc_bios->regs = &bios_regs; 995 996 pool->base.res_cap = &res_cap; 997 pool->base.funcs = &dce120_res_pool_funcs; 998 999 /* TODO: Fill more data from GreenlandAsicCapability.cpp */ 1000 pool->base.pipe_count = res_cap.num_timing_generator; 1001 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1002 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1003 1004 dc->caps.max_downscale_ratio = 200; 1005 dc->caps.i2c_speed_in_khz = 100; 1006 dc->caps.max_cursor_size = 128; 1007 dc->caps.dual_link_dvi = true; 1008 dc->caps.psp_setup_panel_mode = true; 1009 1010 dc->debug = debug_defaults; 1011 1012 /************************************************* 1013 * Create resources * 1014 *************************************************/ 1015 1016 pool->base.clock_sources[DCE120_CLK_SRC_PLL0] = 1017 dce120_clock_source_create(ctx, ctx->dc_bios, 1018 CLOCK_SOURCE_COMBO_PHY_PLL0, 1019 &clk_src_regs[0], false); 1020 pool->base.clock_sources[DCE120_CLK_SRC_PLL1] = 1021 dce120_clock_source_create(ctx, ctx->dc_bios, 1022 CLOCK_SOURCE_COMBO_PHY_PLL1, 1023 &clk_src_regs[1], false); 1024 pool->base.clock_sources[DCE120_CLK_SRC_PLL2] = 1025 dce120_clock_source_create(ctx, ctx->dc_bios, 1026 CLOCK_SOURCE_COMBO_PHY_PLL2, 1027 &clk_src_regs[2], false); 1028 pool->base.clock_sources[DCE120_CLK_SRC_PLL3] = 1029 dce120_clock_source_create(ctx, ctx->dc_bios, 1030 CLOCK_SOURCE_COMBO_PHY_PLL3, 1031 &clk_src_regs[3], false); 1032 pool->base.clock_sources[DCE120_CLK_SRC_PLL4] = 1033 dce120_clock_source_create(ctx, ctx->dc_bios, 1034 CLOCK_SOURCE_COMBO_PHY_PLL4, 1035 &clk_src_regs[4], false); 1036 pool->base.clock_sources[DCE120_CLK_SRC_PLL5] = 1037 dce120_clock_source_create(ctx, ctx->dc_bios, 1038 CLOCK_SOURCE_COMBO_PHY_PLL5, 1039 &clk_src_regs[5], false); 1040 pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL; 1041 1042 pool->base.dp_clock_source = 1043 dce120_clock_source_create(ctx, ctx->dc_bios, 1044 CLOCK_SOURCE_ID_DP_DTO, 1045 &clk_src_regs[0], true); 1046 1047 for (i = 0; i < pool->base.clk_src_count; i++) { 1048 if (pool->base.clock_sources[i] == NULL) { 1049 dm_error("DC: failed to create clock sources!\n"); 1050 BREAK_TO_DEBUGGER(); 1051 goto clk_src_create_fail; 1052 } 1053 } 1054 1055 pool->base.dmcu = dce_dmcu_create(ctx, 1056 &dmcu_regs, 1057 &dmcu_shift, 1058 &dmcu_mask); 1059 if (pool->base.dmcu == NULL) { 1060 dm_error("DC: failed to create dmcu!\n"); 1061 BREAK_TO_DEBUGGER(); 1062 goto res_create_fail; 1063 } 1064 1065 pool->base.abm = dce_abm_create(ctx, 1066 &abm_regs, 1067 &abm_shift, 1068 &abm_mask); 1069 if (pool->base.abm == NULL) { 1070 dm_error("DC: failed to create abm!\n"); 1071 BREAK_TO_DEBUGGER(); 1072 goto res_create_fail; 1073 } 1074 1075 1076 irq_init_data.ctx = dc->ctx; 1077 pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data); 1078 if (!pool->base.irqs) 1079 goto irqs_create_fail; 1080 1081 /* VG20: Pipe harvesting enabled, retrieve valid pipe fuses */ 1082 if (is_vg20) 1083 pipe_fuses = read_pipe_fuses(ctx); 1084 1085 /* index to valid pipe resource */ 1086 j = 0; 1087 for (i = 0; i < pool->base.pipe_count; i++) { 1088 if (is_vg20) { 1089 if ((pipe_fuses & (1 << i)) != 0) { 1090 dm_error("DC: skip invalid pipe %d!\n", i); 1091 continue; 1092 } 1093 } 1094 1095 pool->base.timing_generators[j] = 1096 dce120_timing_generator_create( 1097 ctx, 1098 i, 1099 &dce120_tg_offsets[i]); 1100 if (pool->base.timing_generators[j] == NULL) { 1101 BREAK_TO_DEBUGGER(); 1102 dm_error("DC: failed to create tg!\n"); 1103 goto controller_create_fail; 1104 } 1105 1106 pool->base.mis[j] = dce120_mem_input_create(ctx, i); 1107 1108 if (pool->base.mis[j] == NULL) { 1109 BREAK_TO_DEBUGGER(); 1110 dm_error( 1111 "DC: failed to create memory input!\n"); 1112 goto controller_create_fail; 1113 } 1114 1115 pool->base.ipps[j] = dce120_ipp_create(ctx, i); 1116 if (pool->base.ipps[i] == NULL) { 1117 BREAK_TO_DEBUGGER(); 1118 dm_error( 1119 "DC: failed to create input pixel processor!\n"); 1120 goto controller_create_fail; 1121 } 1122 1123 pool->base.transforms[j] = dce120_transform_create(ctx, i); 1124 if (pool->base.transforms[i] == NULL) { 1125 BREAK_TO_DEBUGGER(); 1126 dm_error( 1127 "DC: failed to create transform!\n"); 1128 goto res_create_fail; 1129 } 1130 1131 pool->base.opps[j] = dce120_opp_create( 1132 ctx, 1133 i); 1134 if (pool->base.opps[j] == NULL) { 1135 BREAK_TO_DEBUGGER(); 1136 dm_error( 1137 "DC: failed to create output pixel processor!\n"); 1138 } 1139 1140 /* check next valid pipe */ 1141 j++; 1142 } 1143 1144 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1145 pool->base.engines[i] = dce120_aux_engine_create(ctx, i); 1146 if (pool->base.engines[i] == NULL) { 1147 BREAK_TO_DEBUGGER(); 1148 dm_error( 1149 "DC:failed to create aux engine!!\n"); 1150 goto res_create_fail; 1151 } 1152 pool->base.hw_i2cs[i] = dce120_i2c_hw_create(ctx, i); 1153 if (pool->base.hw_i2cs[i] == NULL) { 1154 BREAK_TO_DEBUGGER(); 1155 dm_error( 1156 "DC:failed to create i2c engine!!\n"); 1157 goto res_create_fail; 1158 } 1159 pool->base.sw_i2cs[i] = NULL; 1160 } 1161 1162 /* valid pipe num */ 1163 pool->base.pipe_count = j; 1164 pool->base.timing_generator_count = j; 1165 1166 if (is_vg20) 1167 res_funcs = &dce121_res_create_funcs; 1168 else 1169 res_funcs = &res_create_funcs; 1170 1171 if (!resource_construct(num_virtual_links, dc, &pool->base, res_funcs)) 1172 goto res_create_fail; 1173 1174 /* Create hardware sequencer */ 1175 if (!dce120_hw_sequencer_create(dc)) 1176 goto controller_create_fail; 1177 1178 dc->caps.max_planes = pool->base.pipe_count; 1179 1180 for (i = 0; i < dc->caps.max_planes; ++i) 1181 dc->caps.planes[i] = plane_cap; 1182 1183 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1184 1185 bw_calcs_data_update_from_pplib(dc); 1186 1187 return true; 1188 1189 irqs_create_fail: 1190 controller_create_fail: 1191 clk_src_create_fail: 1192 res_create_fail: 1193 1194 destruct(pool); 1195 1196 return false; 1197 } 1198 1199 struct resource_pool *dce120_create_resource_pool( 1200 uint8_t num_virtual_links, 1201 struct dc *dc) 1202 { 1203 struct dce110_resource_pool *pool = 1204 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1205 1206 if (!pool) 1207 return NULL; 1208 1209 if (construct(num_virtual_links, dc, pool)) 1210 return &pool->base; 1211 1212 kfree(pool); 1213 BREAK_TO_DEBUGGER(); 1214 return NULL; 1215 } 1216