1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc.cls 3 * 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 29 30 #include "stream_encoder.h" 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dce120_resource.h" 34 #include "dce112/dce112_resource.h" 35 36 #include "dce110/dce110_resource.h" 37 #include "../virtual/virtual_stream_encoder.h" 38 #include "dce120_timing_generator.h" 39 #include "irq/dce120/irq_service_dce120.h" 40 #include "dce/dce_opp.h" 41 #include "dce/dce_clock_source.h" 42 #include "dce/dce_clocks.h" 43 #include "dce/dce_ipp.h" 44 #include "dce/dce_mem_input.h" 45 46 #include "dce110/dce110_hw_sequencer.h" 47 #include "dce120/dce120_hw_sequencer.h" 48 #include "dce/dce_transform.h" 49 50 #include "dce/dce_audio.h" 51 #include "dce/dce_link_encoder.h" 52 #include "dce/dce_stream_encoder.h" 53 #include "dce/dce_hwseq.h" 54 #include "dce/dce_abm.h" 55 #include "dce/dce_dmcu.h" 56 57 #include "dce/dce_12_0_offset.h" 58 #include "dce/dce_12_0_sh_mask.h" 59 #include "soc15_hw_ip.h" 60 #include "vega10_ip_offset.h" 61 #include "nbio/nbio_6_1_offset.h" 62 #include "reg_helper.h" 63 64 #include "dce100/dce100_resource.h" 65 66 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 67 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 68 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 69 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 70 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 71 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 72 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 73 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 74 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 75 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 76 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 77 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 78 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 79 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 80 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 81 #endif 82 83 enum dce120_clk_src_array_id { 84 DCE120_CLK_SRC_PLL0, 85 DCE120_CLK_SRC_PLL1, 86 DCE120_CLK_SRC_PLL2, 87 DCE120_CLK_SRC_PLL3, 88 DCE120_CLK_SRC_PLL4, 89 DCE120_CLK_SRC_PLL5, 90 91 DCE120_CLK_SRC_TOTAL 92 }; 93 94 static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = { 95 { 96 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 97 }, 98 { 99 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 100 }, 101 { 102 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 103 }, 104 { 105 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 106 }, 107 { 108 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 109 }, 110 { 111 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 112 } 113 }; 114 115 /* begin ********************* 116 * macros to expend register list macro defined in HW object header file */ 117 118 #define BASE_INNER(seg) \ 119 DCE_BASE__INST0_SEG ## seg 120 121 #define NBIO_BASE_INNER(seg) \ 122 NBIF_BASE__INST0_SEG ## seg 123 124 #define NBIO_BASE(seg) \ 125 NBIO_BASE_INNER(seg) 126 127 /* compile time expand base address. */ 128 #define BASE(seg) \ 129 BASE_INNER(seg) 130 131 #define SR(reg_name)\ 132 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 133 mm ## reg_name 134 135 #define SRI(reg_name, block, id)\ 136 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 137 mm ## block ## id ## _ ## reg_name 138 139 /* macros to expend register list macro defined in HW object header file 140 * end *********************/ 141 142 143 static const struct dce_dmcu_registers dmcu_regs = { 144 DMCU_DCE110_COMMON_REG_LIST() 145 }; 146 147 static const struct dce_dmcu_shift dmcu_shift = { 148 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 149 }; 150 151 static const struct dce_dmcu_mask dmcu_mask = { 152 DMCU_MASK_SH_LIST_DCE110(_MASK) 153 }; 154 155 static const struct dce_abm_registers abm_regs = { 156 ABM_DCE110_COMMON_REG_LIST() 157 }; 158 159 static const struct dce_abm_shift abm_shift = { 160 ABM_MASK_SH_LIST_DCE110(__SHIFT) 161 }; 162 163 static const struct dce_abm_mask abm_mask = { 164 ABM_MASK_SH_LIST_DCE110(_MASK) 165 }; 166 167 #define ipp_regs(id)\ 168 [id] = {\ 169 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 170 } 171 172 static const struct dce_ipp_registers ipp_regs[] = { 173 ipp_regs(0), 174 ipp_regs(1), 175 ipp_regs(2), 176 ipp_regs(3), 177 ipp_regs(4), 178 ipp_regs(5) 179 }; 180 181 static const struct dce_ipp_shift ipp_shift = { 182 IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT) 183 }; 184 185 static const struct dce_ipp_mask ipp_mask = { 186 IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK) 187 }; 188 189 #define transform_regs(id)\ 190 [id] = {\ 191 XFM_COMMON_REG_LIST_DCE110(id)\ 192 } 193 194 static const struct dce_transform_registers xfm_regs[] = { 195 transform_regs(0), 196 transform_regs(1), 197 transform_regs(2), 198 transform_regs(3), 199 transform_regs(4), 200 transform_regs(5) 201 }; 202 203 static const struct dce_transform_shift xfm_shift = { 204 XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT) 205 }; 206 207 static const struct dce_transform_mask xfm_mask = { 208 XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK) 209 }; 210 211 #define aux_regs(id)\ 212 [id] = {\ 213 AUX_REG_LIST(id)\ 214 } 215 216 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 217 aux_regs(0), 218 aux_regs(1), 219 aux_regs(2), 220 aux_regs(3), 221 aux_regs(4), 222 aux_regs(5) 223 }; 224 225 #define hpd_regs(id)\ 226 [id] = {\ 227 HPD_REG_LIST(id)\ 228 } 229 230 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 231 hpd_regs(0), 232 hpd_regs(1), 233 hpd_regs(2), 234 hpd_regs(3), 235 hpd_regs(4), 236 hpd_regs(5) 237 }; 238 239 #define link_regs(id)\ 240 [id] = {\ 241 LE_DCE120_REG_LIST(id), \ 242 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 243 } 244 245 static const struct dce110_link_enc_registers link_enc_regs[] = { 246 link_regs(0), 247 link_regs(1), 248 link_regs(2), 249 link_regs(3), 250 link_regs(4), 251 link_regs(5), 252 link_regs(6), 253 }; 254 255 256 #define stream_enc_regs(id)\ 257 [id] = {\ 258 SE_COMMON_REG_LIST(id),\ 259 .TMDS_CNTL = 0,\ 260 } 261 262 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 263 stream_enc_regs(0), 264 stream_enc_regs(1), 265 stream_enc_regs(2), 266 stream_enc_regs(3), 267 stream_enc_regs(4), 268 stream_enc_regs(5) 269 }; 270 271 static const struct dce_stream_encoder_shift se_shift = { 272 SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT) 273 }; 274 275 static const struct dce_stream_encoder_mask se_mask = { 276 SE_COMMON_MASK_SH_LIST_DCE120(_MASK) 277 }; 278 279 #define opp_regs(id)\ 280 [id] = {\ 281 OPP_DCE_120_REG_LIST(id),\ 282 } 283 284 static const struct dce_opp_registers opp_regs[] = { 285 opp_regs(0), 286 opp_regs(1), 287 opp_regs(2), 288 opp_regs(3), 289 opp_regs(4), 290 opp_regs(5) 291 }; 292 293 static const struct dce_opp_shift opp_shift = { 294 OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT) 295 }; 296 297 static const struct dce_opp_mask opp_mask = { 298 OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK) 299 }; 300 301 #define audio_regs(id)\ 302 [id] = {\ 303 AUD_COMMON_REG_LIST(id)\ 304 } 305 306 static const struct dce_audio_registers audio_regs[] = { 307 audio_regs(0), 308 audio_regs(1), 309 audio_regs(2), 310 audio_regs(3), 311 audio_regs(4), 312 audio_regs(5) 313 }; 314 315 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 316 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 317 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 318 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 319 320 static const struct dce_audio_shift audio_shift = { 321 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 322 }; 323 324 static const struct dce_aduio_mask audio_mask = { 325 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 326 }; 327 328 #define clk_src_regs(index, id)\ 329 [index] = {\ 330 CS_COMMON_REG_LIST_DCE_112(id),\ 331 } 332 333 static const struct dce110_clk_src_regs clk_src_regs[] = { 334 clk_src_regs(0, A), 335 clk_src_regs(1, B), 336 clk_src_regs(2, C), 337 clk_src_regs(3, D), 338 clk_src_regs(4, E), 339 clk_src_regs(5, F) 340 }; 341 342 static const struct dce110_clk_src_shift cs_shift = { 343 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 344 }; 345 346 static const struct dce110_clk_src_mask cs_mask = { 347 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) 348 }; 349 350 struct output_pixel_processor *dce120_opp_create( 351 struct dc_context *ctx, 352 uint32_t inst) 353 { 354 struct dce110_opp *opp = 355 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 356 357 if (!opp) 358 return NULL; 359 360 dce110_opp_construct(opp, 361 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 362 return &opp->base; 363 } 364 365 static const struct bios_registers bios_regs = { 366 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX) 367 }; 368 369 static const struct resource_caps res_cap = { 370 .num_timing_generator = 6, 371 .num_audio = 7, 372 .num_stream_encoder = 6, 373 .num_pll = 6, 374 }; 375 376 static const struct dc_debug debug_defaults = { 377 .disable_clock_gate = true, 378 }; 379 380 struct clock_source *dce120_clock_source_create( 381 struct dc_context *ctx, 382 struct dc_bios *bios, 383 enum clock_source_id id, 384 const struct dce110_clk_src_regs *regs, 385 bool dp_clk_src) 386 { 387 struct dce110_clk_src *clk_src = 388 kzalloc(sizeof(*clk_src), GFP_KERNEL); 389 390 if (!clk_src) 391 return NULL; 392 393 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 394 regs, &cs_shift, &cs_mask)) { 395 clk_src->base.dp_clk_src = dp_clk_src; 396 return &clk_src->base; 397 } 398 399 BREAK_TO_DEBUGGER(); 400 return NULL; 401 } 402 403 void dce120_clock_source_destroy(struct clock_source **clk_src) 404 { 405 kfree(TO_DCE110_CLK_SRC(*clk_src)); 406 *clk_src = NULL; 407 } 408 409 410 bool dce120_hw_sequencer_create(struct dc *dc) 411 { 412 /* All registers used by dce11.2 match those in dce11 in offset and 413 * structure 414 */ 415 dce120_hw_sequencer_construct(dc); 416 417 /*TODO Move to separate file and Override what is needed */ 418 419 return true; 420 } 421 422 static struct timing_generator *dce120_timing_generator_create( 423 struct dc_context *ctx, 424 uint32_t instance, 425 const struct dce110_timing_generator_offsets *offsets) 426 { 427 struct dce110_timing_generator *tg110 = 428 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 429 430 if (!tg110) 431 return NULL; 432 433 dce120_timing_generator_construct(tg110, ctx, instance, offsets); 434 return &tg110->base; 435 } 436 437 static void dce120_transform_destroy(struct transform **xfm) 438 { 439 kfree(TO_DCE_TRANSFORM(*xfm)); 440 *xfm = NULL; 441 } 442 443 static void destruct(struct dce110_resource_pool *pool) 444 { 445 unsigned int i; 446 447 for (i = 0; i < pool->base.pipe_count; i++) { 448 if (pool->base.opps[i] != NULL) 449 dce110_opp_destroy(&pool->base.opps[i]); 450 451 if (pool->base.transforms[i] != NULL) 452 dce120_transform_destroy(&pool->base.transforms[i]); 453 454 if (pool->base.ipps[i] != NULL) 455 dce_ipp_destroy(&pool->base.ipps[i]); 456 457 if (pool->base.mis[i] != NULL) { 458 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 459 pool->base.mis[i] = NULL; 460 } 461 462 if (pool->base.irqs != NULL) { 463 dal_irq_service_destroy(&pool->base.irqs); 464 } 465 466 if (pool->base.timing_generators[i] != NULL) { 467 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 468 pool->base.timing_generators[i] = NULL; 469 } 470 } 471 472 for (i = 0; i < pool->base.audio_count; i++) { 473 if (pool->base.audios[i]) 474 dce_aud_destroy(&pool->base.audios[i]); 475 } 476 477 for (i = 0; i < pool->base.stream_enc_count; i++) { 478 if (pool->base.stream_enc[i] != NULL) 479 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 480 } 481 482 for (i = 0; i < pool->base.clk_src_count; i++) { 483 if (pool->base.clock_sources[i] != NULL) 484 dce120_clock_source_destroy( 485 &pool->base.clock_sources[i]); 486 } 487 488 if (pool->base.dp_clock_source != NULL) 489 dce120_clock_source_destroy(&pool->base.dp_clock_source); 490 491 if (pool->base.abm != NULL) 492 dce_abm_destroy(&pool->base.abm); 493 494 if (pool->base.dmcu != NULL) 495 dce_dmcu_destroy(&pool->base.dmcu); 496 497 if (pool->base.dccg != NULL) 498 dce_dccg_destroy(&pool->base.dccg); 499 } 500 501 static void read_dce_straps( 502 struct dc_context *ctx, 503 struct resource_straps *straps) 504 { 505 uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0); 506 507 straps->audio_stream_number = get_reg_field_value(reg_val, 508 CC_DC_MISC_STRAPS, 509 AUDIO_STREAM_NUMBER); 510 straps->hdmi_disable = get_reg_field_value(reg_val, 511 CC_DC_MISC_STRAPS, 512 HDMI_DISABLE); 513 514 reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0); 515 straps->dc_pinstraps_audio = get_reg_field_value(reg_val, 516 DC_PINSTRAPS, 517 DC_PINSTRAPS_AUDIO); 518 } 519 520 static struct audio *create_audio( 521 struct dc_context *ctx, unsigned int inst) 522 { 523 return dce_audio_create(ctx, inst, 524 &audio_regs[inst], &audio_shift, &audio_mask); 525 } 526 527 static const struct encoder_feature_support link_enc_feature = { 528 .max_hdmi_deep_color = COLOR_DEPTH_121212, 529 .max_hdmi_pixel_clock = 600000, 530 .ycbcr420_supported = true, 531 .flags.bits.IS_HBR2_CAPABLE = true, 532 .flags.bits.IS_HBR3_CAPABLE = true, 533 .flags.bits.IS_TPS3_CAPABLE = true, 534 .flags.bits.IS_TPS4_CAPABLE = true, 535 .flags.bits.IS_YCBCR_CAPABLE = true 536 }; 537 538 static struct link_encoder *dce120_link_encoder_create( 539 const struct encoder_init_data *enc_init_data) 540 { 541 struct dce110_link_encoder *enc110 = 542 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 543 544 if (!enc110) 545 return NULL; 546 547 dce110_link_encoder_construct(enc110, 548 enc_init_data, 549 &link_enc_feature, 550 &link_enc_regs[enc_init_data->transmitter], 551 &link_enc_aux_regs[enc_init_data->channel - 1], 552 &link_enc_hpd_regs[enc_init_data->hpd_source]); 553 554 return &enc110->base; 555 } 556 557 static struct input_pixel_processor *dce120_ipp_create( 558 struct dc_context *ctx, uint32_t inst) 559 { 560 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 561 562 if (!ipp) { 563 BREAK_TO_DEBUGGER(); 564 return NULL; 565 } 566 567 dce_ipp_construct(ipp, ctx, inst, 568 &ipp_regs[inst], &ipp_shift, &ipp_mask); 569 return &ipp->base; 570 } 571 572 static struct stream_encoder *dce120_stream_encoder_create( 573 enum engine_id eng_id, 574 struct dc_context *ctx) 575 { 576 struct dce110_stream_encoder *enc110 = 577 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 578 579 if (!enc110) 580 return NULL; 581 582 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 583 &stream_enc_regs[eng_id], 584 &se_shift, &se_mask); 585 return &enc110->base; 586 } 587 588 #define SRII(reg_name, block, id)\ 589 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 590 mm ## block ## id ## _ ## reg_name 591 592 static const struct dce_hwseq_registers hwseq_reg = { 593 HWSEQ_DCE120_REG_LIST() 594 }; 595 596 static const struct dce_hwseq_shift hwseq_shift = { 597 HWSEQ_DCE12_MASK_SH_LIST(__SHIFT) 598 }; 599 600 static const struct dce_hwseq_mask hwseq_mask = { 601 HWSEQ_DCE12_MASK_SH_LIST(_MASK) 602 }; 603 604 static struct dce_hwseq *dce120_hwseq_create( 605 struct dc_context *ctx) 606 { 607 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 608 609 if (hws) { 610 hws->ctx = ctx; 611 hws->regs = &hwseq_reg; 612 hws->shifts = &hwseq_shift; 613 hws->masks = &hwseq_mask; 614 } 615 return hws; 616 } 617 618 static const struct resource_create_funcs res_create_funcs = { 619 .read_dce_straps = read_dce_straps, 620 .create_audio = create_audio, 621 .create_stream_encoder = dce120_stream_encoder_create, 622 .create_hwseq = dce120_hwseq_create, 623 }; 624 625 #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) } 626 static const struct dce_mem_input_registers mi_regs[] = { 627 mi_inst_regs(0), 628 mi_inst_regs(1), 629 mi_inst_regs(2), 630 mi_inst_regs(3), 631 mi_inst_regs(4), 632 mi_inst_regs(5), 633 }; 634 635 static const struct dce_mem_input_shift mi_shifts = { 636 MI_DCE12_MASK_SH_LIST(__SHIFT) 637 }; 638 639 static const struct dce_mem_input_mask mi_masks = { 640 MI_DCE12_MASK_SH_LIST(_MASK) 641 }; 642 643 static struct mem_input *dce120_mem_input_create( 644 struct dc_context *ctx, 645 uint32_t inst) 646 { 647 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 648 GFP_KERNEL); 649 650 if (!dce_mi) { 651 BREAK_TO_DEBUGGER(); 652 return NULL; 653 } 654 655 dce120_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 656 return &dce_mi->base; 657 } 658 659 static struct transform *dce120_transform_create( 660 struct dc_context *ctx, 661 uint32_t inst) 662 { 663 struct dce_transform *transform = 664 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 665 666 if (!transform) 667 return NULL; 668 669 dce_transform_construct(transform, ctx, inst, 670 &xfm_regs[inst], &xfm_shift, &xfm_mask); 671 transform->lb_memory_size = 0x1404; /*5124*/ 672 return &transform->base; 673 } 674 675 static void dce120_destroy_resource_pool(struct resource_pool **pool) 676 { 677 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 678 679 destruct(dce110_pool); 680 kfree(dce110_pool); 681 *pool = NULL; 682 } 683 684 static const struct resource_funcs dce120_res_pool_funcs = { 685 .destroy = dce120_destroy_resource_pool, 686 .link_enc_create = dce120_link_encoder_create, 687 .validate_bandwidth = dce112_validate_bandwidth, 688 .validate_plane = dce100_validate_plane, 689 .add_stream_to_ctx = dce112_add_stream_to_ctx 690 }; 691 692 static void bw_calcs_data_update_from_pplib(struct dc *dc) 693 { 694 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 695 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 696 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; 697 int i; 698 unsigned int clk; 699 unsigned int latency; 700 701 /*do system clock*/ 702 if (!dm_pp_get_clock_levels_by_type_with_latency( 703 dc->ctx, 704 DM_PP_CLOCK_TYPE_ENGINE_CLK, 705 &eng_clks) || eng_clks.num_levels == 0) { 706 707 eng_clks.num_levels = 8; 708 clk = 300000; 709 710 for (i = 0; i < eng_clks.num_levels; i++) { 711 eng_clks.data[i].clocks_in_khz = clk; 712 clk += 100000; 713 } 714 } 715 716 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ 717 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 718 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); 719 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 720 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); 721 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 722 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); 723 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 724 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); 725 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 726 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); 727 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 728 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); 729 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 730 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); 731 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 732 eng_clks.data[0].clocks_in_khz, 1000); 733 734 /*do memory clock*/ 735 if (!dm_pp_get_clock_levels_by_type_with_latency( 736 dc->ctx, 737 DM_PP_CLOCK_TYPE_MEMORY_CLK, 738 &mem_clks) || mem_clks.num_levels == 0) { 739 740 mem_clks.num_levels = 3; 741 clk = 250000; 742 latency = 45; 743 744 for (i = 0; i < eng_clks.num_levels; i++) { 745 mem_clks.data[i].clocks_in_khz = clk; 746 mem_clks.data[i].latency_in_us = latency; 747 clk += 500000; 748 latency -= 5; 749 } 750 751 } 752 753 /* we don't need to call PPLIB for validation clock since they 754 * also give us the highest sclk and highest mclk (UMA clock). 755 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): 756 * YCLK = UMACLK*m_memoryTypeMultiplier 757 */ 758 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 759 mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000); 760 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 761 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 762 1000); 763 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 764 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 765 1000); 766 767 /* Now notify PPLib/SMU about which Watermarks sets they should select 768 * depending on DPM state they are in. And update BW MGR GFX Engine and 769 * Memory clock member variables for Watermarks calculations for each 770 * Watermark Set 771 */ 772 clk_ranges.num_wm_sets = 4; 773 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; 774 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = 775 eng_clks.data[0].clocks_in_khz; 776 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = 777 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 778 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz = 779 mem_clks.data[0].clocks_in_khz; 780 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = 781 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 782 783 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; 784 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = 785 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 786 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 787 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; 788 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz = 789 mem_clks.data[0].clocks_in_khz; 790 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = 791 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 792 793 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; 794 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = 795 eng_clks.data[0].clocks_in_khz; 796 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = 797 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 798 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz = 799 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 800 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 801 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; 802 803 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; 804 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = 805 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 806 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 807 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; 808 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz = 809 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 810 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 811 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; 812 813 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 814 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); 815 } 816 817 static uint32_t read_pipe_fuses(struct dc_context *ctx) 818 { 819 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); 820 /* VG20 support max 6 pipes */ 821 value = value & 0x3f; 822 return value; 823 } 824 825 static bool construct( 826 uint8_t num_virtual_links, 827 struct dc *dc, 828 struct dce110_resource_pool *pool) 829 { 830 unsigned int i; 831 int j; 832 struct dc_context *ctx = dc->ctx; 833 struct irq_service_init_data irq_init_data; 834 bool harvest_enabled = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev); 835 uint32_t pipe_fuses; 836 837 ctx->dc_bios->regs = &bios_regs; 838 839 pool->base.res_cap = &res_cap; 840 pool->base.funcs = &dce120_res_pool_funcs; 841 842 /* TODO: Fill more data from GreenlandAsicCapability.cpp */ 843 pool->base.pipe_count = res_cap.num_timing_generator; 844 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 845 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 846 847 dc->caps.max_downscale_ratio = 200; 848 dc->caps.i2c_speed_in_khz = 100; 849 dc->caps.max_cursor_size = 128; 850 dc->caps.dual_link_dvi = true; 851 852 dc->debug = debug_defaults; 853 854 /************************************************* 855 * Create resources * 856 *************************************************/ 857 858 pool->base.clock_sources[DCE120_CLK_SRC_PLL0] = 859 dce120_clock_source_create(ctx, ctx->dc_bios, 860 CLOCK_SOURCE_COMBO_PHY_PLL0, 861 &clk_src_regs[0], false); 862 pool->base.clock_sources[DCE120_CLK_SRC_PLL1] = 863 dce120_clock_source_create(ctx, ctx->dc_bios, 864 CLOCK_SOURCE_COMBO_PHY_PLL1, 865 &clk_src_regs[1], false); 866 pool->base.clock_sources[DCE120_CLK_SRC_PLL2] = 867 dce120_clock_source_create(ctx, ctx->dc_bios, 868 CLOCK_SOURCE_COMBO_PHY_PLL2, 869 &clk_src_regs[2], false); 870 pool->base.clock_sources[DCE120_CLK_SRC_PLL3] = 871 dce120_clock_source_create(ctx, ctx->dc_bios, 872 CLOCK_SOURCE_COMBO_PHY_PLL3, 873 &clk_src_regs[3], false); 874 pool->base.clock_sources[DCE120_CLK_SRC_PLL4] = 875 dce120_clock_source_create(ctx, ctx->dc_bios, 876 CLOCK_SOURCE_COMBO_PHY_PLL4, 877 &clk_src_regs[4], false); 878 pool->base.clock_sources[DCE120_CLK_SRC_PLL5] = 879 dce120_clock_source_create(ctx, ctx->dc_bios, 880 CLOCK_SOURCE_COMBO_PHY_PLL5, 881 &clk_src_regs[5], false); 882 pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL; 883 884 pool->base.dp_clock_source = 885 dce120_clock_source_create(ctx, ctx->dc_bios, 886 CLOCK_SOURCE_ID_DP_DTO, 887 &clk_src_regs[0], true); 888 889 for (i = 0; i < pool->base.clk_src_count; i++) { 890 if (pool->base.clock_sources[i] == NULL) { 891 dm_error("DC: failed to create clock sources!\n"); 892 BREAK_TO_DEBUGGER(); 893 goto clk_src_create_fail; 894 } 895 } 896 897 pool->base.dccg = dce120_dccg_create(ctx); 898 if (pool->base.dccg == NULL) { 899 dm_error("DC: failed to create display clock!\n"); 900 BREAK_TO_DEBUGGER(); 901 goto dccg_create_fail; 902 } 903 904 pool->base.dmcu = dce_dmcu_create(ctx, 905 &dmcu_regs, 906 &dmcu_shift, 907 &dmcu_mask); 908 if (pool->base.dmcu == NULL) { 909 dm_error("DC: failed to create dmcu!\n"); 910 BREAK_TO_DEBUGGER(); 911 goto res_create_fail; 912 } 913 914 pool->base.abm = dce_abm_create(ctx, 915 &abm_regs, 916 &abm_shift, 917 &abm_mask); 918 if (pool->base.abm == NULL) { 919 dm_error("DC: failed to create abm!\n"); 920 BREAK_TO_DEBUGGER(); 921 goto res_create_fail; 922 } 923 924 irq_init_data.ctx = dc->ctx; 925 pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data); 926 if (!pool->base.irqs) 927 goto irqs_create_fail; 928 929 /* retrieve valid pipe fuses */ 930 if (harvest_enabled) 931 pipe_fuses = read_pipe_fuses(ctx); 932 933 /* index to valid pipe resource */ 934 j = 0; 935 for (i = 0; i < pool->base.pipe_count; i++) { 936 if (harvest_enabled) { 937 if ((pipe_fuses & (1 << i)) != 0) { 938 dm_error("DC: skip invalid pipe %d!\n", i); 939 continue; 940 } 941 } 942 943 pool->base.timing_generators[j] = 944 dce120_timing_generator_create( 945 ctx, 946 i, 947 &dce120_tg_offsets[i]); 948 if (pool->base.timing_generators[j] == NULL) { 949 BREAK_TO_DEBUGGER(); 950 dm_error("DC: failed to create tg!\n"); 951 goto controller_create_fail; 952 } 953 954 pool->base.mis[j] = dce120_mem_input_create(ctx, i); 955 956 if (pool->base.mis[j] == NULL) { 957 BREAK_TO_DEBUGGER(); 958 dm_error( 959 "DC: failed to create memory input!\n"); 960 goto controller_create_fail; 961 } 962 963 pool->base.ipps[j] = dce120_ipp_create(ctx, i); 964 if (pool->base.ipps[i] == NULL) { 965 BREAK_TO_DEBUGGER(); 966 dm_error( 967 "DC: failed to create input pixel processor!\n"); 968 goto controller_create_fail; 969 } 970 971 pool->base.transforms[j] = dce120_transform_create(ctx, i); 972 if (pool->base.transforms[i] == NULL) { 973 BREAK_TO_DEBUGGER(); 974 dm_error( 975 "DC: failed to create transform!\n"); 976 goto res_create_fail; 977 } 978 979 pool->base.opps[j] = dce120_opp_create( 980 ctx, 981 i); 982 if (pool->base.opps[j] == NULL) { 983 BREAK_TO_DEBUGGER(); 984 dm_error( 985 "DC: failed to create output pixel processor!\n"); 986 } 987 988 /* check next valid pipe */ 989 j++; 990 } 991 992 /* valid pipe num */ 993 pool->base.pipe_count = j; 994 pool->base.timing_generator_count = j; 995 996 if (!resource_construct(num_virtual_links, dc, &pool->base, 997 &res_create_funcs)) 998 goto res_create_fail; 999 1000 /* Create hardware sequencer */ 1001 if (!dce120_hw_sequencer_create(dc)) 1002 goto controller_create_fail; 1003 1004 dc->caps.max_planes = pool->base.pipe_count; 1005 1006 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1007 1008 bw_calcs_data_update_from_pplib(dc); 1009 1010 return true; 1011 1012 irqs_create_fail: 1013 controller_create_fail: 1014 dccg_create_fail: 1015 clk_src_create_fail: 1016 res_create_fail: 1017 1018 destruct(pool); 1019 1020 return false; 1021 } 1022 1023 struct resource_pool *dce120_create_resource_pool( 1024 uint8_t num_virtual_links, 1025 struct dc *dc) 1026 { 1027 struct dce110_resource_pool *pool = 1028 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1029 1030 if (!pool) 1031 return NULL; 1032 1033 if (construct(num_virtual_links, dc, pool)) 1034 return &pool->base; 1035 1036 BREAK_TO_DEBUGGER(); 1037 return NULL; 1038 } 1039