1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc.cls 3 * 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 29 30 #include "stream_encoder.h" 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dce120_resource.h" 34 #include "dce112/dce112_resource.h" 35 36 #include "dce110/dce110_resource.h" 37 #include "../virtual/virtual_stream_encoder.h" 38 #include "dce120_timing_generator.h" 39 #include "irq/dce120/irq_service_dce120.h" 40 #include "dce/dce_opp.h" 41 #include "dce/dce_clock_source.h" 42 #include "dce/dce_clocks.h" 43 #include "dce/dce_ipp.h" 44 #include "dce110/dce110_mem_input.h" 45 #include "dce120/dce120_mem_input.h" 46 47 #include "dce110/dce110_hw_sequencer.h" 48 #include "dce120/dce120_hw_sequencer.h" 49 #include "dce/dce_transform.h" 50 51 #include "dce/dce_audio.h" 52 #include "dce/dce_link_encoder.h" 53 #include "dce/dce_stream_encoder.h" 54 #include "dce/dce_hwseq.h" 55 #include "dce/dce_abm.h" 56 #include "dce/dce_dmcu.h" 57 58 #include "vega10/DC/dce_12_0_offset.h" 59 #include "vega10/DC/dce_12_0_sh_mask.h" 60 #include "vega10/soc15ip.h" 61 #include "vega10/NBIO/nbio_6_1_offset.h" 62 #include "reg_helper.h" 63 64 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 65 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 66 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 67 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 68 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 69 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 70 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 71 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 72 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 73 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 74 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 75 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 76 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 77 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 78 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 79 #endif 80 81 enum dce120_clk_src_array_id { 82 DCE120_CLK_SRC_PLL0, 83 DCE120_CLK_SRC_PLL1, 84 DCE120_CLK_SRC_PLL2, 85 DCE120_CLK_SRC_PLL3, 86 DCE120_CLK_SRC_PLL4, 87 DCE120_CLK_SRC_PLL5, 88 89 DCE120_CLK_SRC_TOTAL 90 }; 91 92 static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = { 93 { 94 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 95 }, 96 { 97 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 98 }, 99 { 100 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 101 }, 102 { 103 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 104 }, 105 { 106 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 107 }, 108 { 109 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 110 } 111 }; 112 113 /* begin ********************* 114 * macros to expend register list macro defined in HW object header file */ 115 116 #define BASE_INNER(seg) \ 117 DCE_BASE__INST0_SEG ## seg 118 119 #define NBIO_BASE_INNER(seg) \ 120 NBIF_BASE__INST0_SEG ## seg 121 122 #define NBIO_BASE(seg) \ 123 NBIO_BASE_INNER(seg) 124 125 /* compile time expand base address. */ 126 #define BASE(seg) \ 127 BASE_INNER(seg) 128 129 #define SR(reg_name)\ 130 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 131 mm ## reg_name 132 133 #define SRI(reg_name, block, id)\ 134 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 135 mm ## block ## id ## _ ## reg_name 136 137 /* macros to expend register list macro defined in HW object header file 138 * end *********************/ 139 140 141 static const struct dce_disp_clk_registers disp_clk_regs = { 142 CLK_COMMON_REG_LIST_DCE_BASE() 143 }; 144 145 static const struct dce_disp_clk_shift disp_clk_shift = { 146 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 147 }; 148 149 static const struct dce_disp_clk_mask disp_clk_mask = { 150 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 151 }; 152 153 static const struct dce_dmcu_registers dmcu_regs = { 154 DMCU_DCE110_COMMON_REG_LIST() 155 }; 156 157 static const struct dce_dmcu_shift dmcu_shift = { 158 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 159 }; 160 161 static const struct dce_dmcu_mask dmcu_mask = { 162 DMCU_MASK_SH_LIST_DCE110(_MASK) 163 }; 164 165 static const struct dce_abm_registers abm_regs = { 166 ABM_DCE110_COMMON_REG_LIST() 167 }; 168 169 static const struct dce_abm_shift abm_shift = { 170 ABM_MASK_SH_LIST_DCE110(__SHIFT) 171 }; 172 173 static const struct dce_abm_mask abm_mask = { 174 ABM_MASK_SH_LIST_DCE110(_MASK) 175 }; 176 177 #define ipp_regs(id)\ 178 [id] = {\ 179 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 180 } 181 182 static const struct dce_ipp_registers ipp_regs[] = { 183 ipp_regs(0), 184 ipp_regs(1), 185 ipp_regs(2), 186 ipp_regs(3), 187 ipp_regs(4), 188 ipp_regs(5) 189 }; 190 191 static const struct dce_ipp_shift ipp_shift = { 192 IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT) 193 }; 194 195 static const struct dce_ipp_mask ipp_mask = { 196 IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK) 197 }; 198 199 #define transform_regs(id)\ 200 [id] = {\ 201 XFM_COMMON_REG_LIST_DCE110(id)\ 202 } 203 204 static const struct dce_transform_registers xfm_regs[] = { 205 transform_regs(0), 206 transform_regs(1), 207 transform_regs(2), 208 transform_regs(3), 209 transform_regs(4), 210 transform_regs(5) 211 }; 212 213 static const struct dce_transform_shift xfm_shift = { 214 XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT) 215 }; 216 217 static const struct dce_transform_mask xfm_mask = { 218 XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK) 219 }; 220 221 #define aux_regs(id)\ 222 [id] = {\ 223 AUX_REG_LIST(id)\ 224 } 225 226 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 227 aux_regs(0), 228 aux_regs(1), 229 aux_regs(2), 230 aux_regs(3), 231 aux_regs(4), 232 aux_regs(5) 233 }; 234 235 #define hpd_regs(id)\ 236 [id] = {\ 237 HPD_REG_LIST(id)\ 238 } 239 240 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 241 hpd_regs(0), 242 hpd_regs(1), 243 hpd_regs(2), 244 hpd_regs(3), 245 hpd_regs(4), 246 hpd_regs(5) 247 }; 248 249 #define link_regs(id)\ 250 [id] = {\ 251 LE_DCE120_REG_LIST(id), \ 252 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 253 } 254 255 static const struct dce110_link_enc_registers link_enc_regs[] = { 256 link_regs(0), 257 link_regs(1), 258 link_regs(2), 259 link_regs(3), 260 link_regs(4), 261 link_regs(5), 262 link_regs(6), 263 }; 264 265 266 #define stream_enc_regs(id)\ 267 [id] = {\ 268 SE_COMMON_REG_LIST(id),\ 269 .TMDS_CNTL = 0,\ 270 } 271 272 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 273 stream_enc_regs(0), 274 stream_enc_regs(1), 275 stream_enc_regs(2), 276 stream_enc_regs(3), 277 stream_enc_regs(4), 278 stream_enc_regs(5) 279 }; 280 281 static const struct dce_stream_encoder_shift se_shift = { 282 SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT) 283 }; 284 285 static const struct dce_stream_encoder_mask se_mask = { 286 SE_COMMON_MASK_SH_LIST_DCE120(_MASK) 287 }; 288 289 #define opp_regs(id)\ 290 [id] = {\ 291 OPP_DCE_120_REG_LIST(id),\ 292 } 293 294 static const struct dce_opp_registers opp_regs[] = { 295 opp_regs(0), 296 opp_regs(1), 297 opp_regs(2), 298 opp_regs(3), 299 opp_regs(4), 300 opp_regs(5) 301 }; 302 303 static const struct dce_opp_shift opp_shift = { 304 OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT) 305 }; 306 307 static const struct dce_opp_mask opp_mask = { 308 OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK) 309 }; 310 311 #define audio_regs(id)\ 312 [id] = {\ 313 AUD_COMMON_REG_LIST(id)\ 314 } 315 316 static struct dce_audio_registers audio_regs[] = { 317 audio_regs(0), 318 audio_regs(1), 319 audio_regs(2), 320 audio_regs(3), 321 audio_regs(4), 322 audio_regs(5) 323 }; 324 325 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 326 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 327 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 328 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 329 330 static const struct dce_audio_shift audio_shift = { 331 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 332 }; 333 334 static const struct dce_aduio_mask audio_mask = { 335 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 336 }; 337 338 #define clk_src_regs(index, id)\ 339 [index] = {\ 340 CS_COMMON_REG_LIST_DCE_112(id),\ 341 } 342 343 static const struct dce110_clk_src_regs clk_src_regs[] = { 344 clk_src_regs(0, A), 345 clk_src_regs(1, B), 346 clk_src_regs(2, C), 347 clk_src_regs(3, D), 348 clk_src_regs(4, E), 349 clk_src_regs(5, F) 350 }; 351 352 static const struct dce110_clk_src_shift cs_shift = { 353 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 354 }; 355 356 static const struct dce110_clk_src_mask cs_mask = { 357 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) 358 }; 359 360 struct output_pixel_processor *dce120_opp_create( 361 struct dc_context *ctx, 362 uint32_t inst) 363 { 364 struct dce110_opp *opp = 365 dm_alloc(sizeof(struct dce110_opp)); 366 367 if (!opp) 368 return NULL; 369 370 if (dce110_opp_construct(opp, 371 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask)) 372 return &opp->base; 373 374 BREAK_TO_DEBUGGER(); 375 dm_free(opp); 376 return NULL; 377 } 378 379 static const struct dce110_mem_input_reg_offsets dce120_mi_reg_offsets[] = { 380 { 381 .dcp = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 382 .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 383 - mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL), 384 .pipe = (mmPIPE0_DMIF_BUFFER_CONTROL 385 - mmPIPE0_DMIF_BUFFER_CONTROL), 386 }, 387 { 388 .dcp = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 389 .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 390 - mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL), 391 .pipe = (mmPIPE1_DMIF_BUFFER_CONTROL 392 - mmPIPE0_DMIF_BUFFER_CONTROL), 393 }, 394 { 395 .dcp = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 396 .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 397 - mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL), 398 .pipe = (mmPIPE2_DMIF_BUFFER_CONTROL 399 - mmPIPE0_DMIF_BUFFER_CONTROL), 400 }, 401 { 402 .dcp = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 403 .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 404 - mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL), 405 .pipe = (mmPIPE3_DMIF_BUFFER_CONTROL 406 - mmPIPE0_DMIF_BUFFER_CONTROL), 407 }, 408 { 409 .dcp = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 410 .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 411 - mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL), 412 .pipe = (mmPIPE4_DMIF_BUFFER_CONTROL 413 - mmPIPE0_DMIF_BUFFER_CONTROL), 414 }, 415 { 416 .dcp = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 417 .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 418 - mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL), 419 .pipe = (mmPIPE5_DMIF_BUFFER_CONTROL 420 - mmPIPE0_DMIF_BUFFER_CONTROL), 421 } 422 }; 423 424 static const struct bios_registers bios_regs = { 425 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX) 426 }; 427 428 static const struct resource_caps res_cap = { 429 .num_timing_generator = 3, 430 .num_audio = 7, 431 .num_stream_encoder = 6, 432 .num_pll = 6, 433 }; 434 435 static const struct dc_debug debug_defaults = { 436 .disable_clock_gate = true, 437 }; 438 439 struct clock_source *dce120_clock_source_create( 440 struct dc_context *ctx, 441 struct dc_bios *bios, 442 enum clock_source_id id, 443 const struct dce110_clk_src_regs *regs, 444 bool dp_clk_src) 445 { 446 struct dce110_clk_src *clk_src = 447 dm_alloc(sizeof(struct dce110_clk_src)); 448 449 if (!clk_src) 450 return NULL; 451 452 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 453 regs, &cs_shift, &cs_mask)) { 454 clk_src->base.dp_clk_src = dp_clk_src; 455 return &clk_src->base; 456 } 457 458 BREAK_TO_DEBUGGER(); 459 return NULL; 460 } 461 462 void dce120_clock_source_destroy(struct clock_source **clk_src) 463 { 464 dm_free(TO_DCE110_CLK_SRC(*clk_src)); 465 *clk_src = NULL; 466 } 467 468 469 bool dce120_hw_sequencer_create(struct core_dc *dc) 470 { 471 /* All registers used by dce11.2 match those in dce11 in offset and 472 * structure 473 */ 474 dce120_hw_sequencer_construct(dc); 475 476 /*TODO Move to separate file and Override what is needed */ 477 478 return true; 479 } 480 481 static struct timing_generator *dce120_timing_generator_create( 482 struct dc_context *ctx, 483 uint32_t instance, 484 const struct dce110_timing_generator_offsets *offsets) 485 { 486 struct dce110_timing_generator *tg110 = 487 dm_alloc(sizeof(struct dce110_timing_generator)); 488 489 if (!tg110) 490 return NULL; 491 492 if (dce120_timing_generator_construct(tg110, ctx, instance, offsets)) 493 return &tg110->base; 494 495 BREAK_TO_DEBUGGER(); 496 dm_free(tg110); 497 return NULL; 498 } 499 500 static void dce120_transform_destroy(struct transform **xfm) 501 { 502 dm_free(TO_DCE_TRANSFORM(*xfm)); 503 *xfm = NULL; 504 } 505 506 static void destruct(struct dce110_resource_pool *pool) 507 { 508 unsigned int i; 509 510 for (i = 0; i < pool->base.pipe_count; i++) { 511 if (pool->base.opps[i] != NULL) 512 dce110_opp_destroy(&pool->base.opps[i]); 513 514 if (pool->base.transforms[i] != NULL) 515 dce120_transform_destroy(&pool->base.transforms[i]); 516 517 if (pool->base.ipps[i] != NULL) 518 dce_ipp_destroy(&pool->base.ipps[i]); 519 520 if (pool->base.mis[i] != NULL) { 521 dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i])); 522 pool->base.mis[i] = NULL; 523 } 524 525 if (pool->base.irqs != NULL) { 526 dal_irq_service_destroy(&pool->base.irqs); 527 } 528 529 if (pool->base.timing_generators[i] != NULL) { 530 dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 531 pool->base.timing_generators[i] = NULL; 532 } 533 } 534 535 for (i = 0; i < pool->base.audio_count; i++) { 536 if (pool->base.audios[i]) 537 dce_aud_destroy(&pool->base.audios[i]); 538 } 539 540 for (i = 0; i < pool->base.stream_enc_count; i++) { 541 if (pool->base.stream_enc[i] != NULL) 542 dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 543 } 544 545 for (i = 0; i < pool->base.clk_src_count; i++) { 546 if (pool->base.clock_sources[i] != NULL) 547 dce120_clock_source_destroy( 548 &pool->base.clock_sources[i]); 549 } 550 551 if (pool->base.dp_clock_source != NULL) 552 dce120_clock_source_destroy(&pool->base.dp_clock_source); 553 554 if (pool->base.abm != NULL) 555 dce_abm_destroy(&pool->base.abm); 556 557 if (pool->base.dmcu != NULL) 558 dce_dmcu_destroy(&pool->base.dmcu); 559 560 if (pool->base.display_clock != NULL) 561 dce_disp_clk_destroy(&pool->base.display_clock); 562 } 563 564 static void read_dce_straps( 565 struct dc_context *ctx, 566 struct resource_straps *straps) 567 { 568 /* TODO: Registers are missing */ 569 /*REG_GET_2(CC_DC_HDMI_STRAPS, 570 HDMI_DISABLE, &straps->hdmi_disable, 571 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 572 573 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);*/ 574 } 575 576 static struct audio *create_audio( 577 struct dc_context *ctx, unsigned int inst) 578 { 579 return dce_audio_create(ctx, inst, 580 &audio_regs[inst], &audio_shift, &audio_mask); 581 } 582 583 static const struct encoder_feature_support link_enc_feature = { 584 .max_hdmi_deep_color = COLOR_DEPTH_121212, 585 .max_hdmi_pixel_clock = 600000, 586 .ycbcr420_supported = true, 587 .flags.bits.IS_HBR2_CAPABLE = true, 588 .flags.bits.IS_HBR3_CAPABLE = true, 589 .flags.bits.IS_TPS3_CAPABLE = true, 590 .flags.bits.IS_TPS4_CAPABLE = true, 591 .flags.bits.IS_YCBCR_CAPABLE = true 592 }; 593 594 struct link_encoder *dce120_link_encoder_create( 595 const struct encoder_init_data *enc_init_data) 596 { 597 struct dce110_link_encoder *enc110 = 598 dm_alloc(sizeof(struct dce110_link_encoder)); 599 600 if (!enc110) 601 return NULL; 602 603 if (dce110_link_encoder_construct( 604 enc110, 605 enc_init_data, 606 &link_enc_feature, 607 &link_enc_regs[enc_init_data->transmitter], 608 &link_enc_aux_regs[enc_init_data->channel - 1], 609 &link_enc_hpd_regs[enc_init_data->hpd_source])) { 610 611 return &enc110->base; 612 } 613 614 BREAK_TO_DEBUGGER(); 615 dm_free(enc110); 616 return NULL; 617 } 618 619 static struct input_pixel_processor *dce120_ipp_create( 620 struct dc_context *ctx, uint32_t inst) 621 { 622 struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); 623 624 if (!ipp) { 625 BREAK_TO_DEBUGGER(); 626 return NULL; 627 } 628 629 dce_ipp_construct(ipp, ctx, inst, 630 &ipp_regs[inst], &ipp_shift, &ipp_mask); 631 return &ipp->base; 632 } 633 634 static struct stream_encoder *dce120_stream_encoder_create( 635 enum engine_id eng_id, 636 struct dc_context *ctx) 637 { 638 struct dce110_stream_encoder *enc110 = 639 dm_alloc(sizeof(struct dce110_stream_encoder)); 640 641 if (!enc110) 642 return NULL; 643 644 if (dce110_stream_encoder_construct( 645 enc110, ctx, ctx->dc_bios, eng_id, 646 &stream_enc_regs[eng_id], &se_shift, &se_mask)) 647 return &enc110->base; 648 649 BREAK_TO_DEBUGGER(); 650 dm_free(enc110); 651 return NULL; 652 } 653 654 #define SRII(reg_name, block, id)\ 655 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 656 mm ## block ## id ## _ ## reg_name 657 658 static const struct dce_hwseq_registers hwseq_reg = { 659 HWSEQ_DCE112_REG_LIST() 660 }; 661 662 static const struct dce_hwseq_shift hwseq_shift = { 663 HWSEQ_DCE12_MASK_SH_LIST(__SHIFT) 664 }; 665 666 static const struct dce_hwseq_mask hwseq_mask = { 667 HWSEQ_DCE12_MASK_SH_LIST(_MASK) 668 }; 669 670 static struct dce_hwseq *dce120_hwseq_create( 671 struct dc_context *ctx) 672 { 673 struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq)); 674 675 if (hws) { 676 hws->ctx = ctx; 677 hws->regs = &hwseq_reg; 678 hws->shifts = &hwseq_shift; 679 hws->masks = &hwseq_mask; 680 } 681 return hws; 682 } 683 684 static const struct resource_create_funcs res_create_funcs = { 685 .read_dce_straps = read_dce_straps, 686 .create_audio = create_audio, 687 .create_stream_encoder = dce120_stream_encoder_create, 688 .create_hwseq = dce120_hwseq_create, 689 }; 690 691 #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) } 692 static const struct dce_mem_input_registers mi_regs[] = { 693 mi_inst_regs(0), 694 mi_inst_regs(1), 695 mi_inst_regs(2), 696 mi_inst_regs(3), 697 mi_inst_regs(4), 698 mi_inst_regs(5), 699 }; 700 701 static const struct dce_mem_input_shift mi_shifts = { 702 MI_DCE12_MASK_SH_LIST(__SHIFT) 703 }; 704 705 static const struct dce_mem_input_mask mi_masks = { 706 MI_DCE12_MASK_SH_LIST(_MASK) 707 }; 708 709 static struct mem_input *dce120_mem_input_create( 710 struct dc_context *ctx, 711 uint32_t inst, 712 const struct dce110_mem_input_reg_offsets *offset) 713 { 714 struct dce110_mem_input *mem_input110 = 715 dm_alloc(sizeof(struct dce110_mem_input)); 716 717 if (!mem_input110) 718 return NULL; 719 720 if (dce120_mem_input_construct(mem_input110, ctx, inst, offset)) { 721 struct mem_input *mi = &mem_input110->base; 722 723 mi->regs = &mi_regs[inst]; 724 mi->shifts = &mi_shifts; 725 mi->masks = &mi_masks; 726 return mi; 727 } 728 729 BREAK_TO_DEBUGGER(); 730 dm_free(mem_input110); 731 return NULL; 732 } 733 734 static struct transform *dce120_transform_create( 735 struct dc_context *ctx, 736 uint32_t inst) 737 { 738 struct dce_transform *transform = 739 dm_alloc(sizeof(struct dce_transform)); 740 741 if (!transform) 742 return NULL; 743 744 if (dce_transform_construct(transform, ctx, inst, 745 &xfm_regs[inst], &xfm_shift, &xfm_mask)) { 746 transform->lb_memory_size = 0x1404; /*5124*/ 747 return &transform->base; 748 } 749 750 BREAK_TO_DEBUGGER(); 751 dm_free(transform); 752 return NULL; 753 } 754 755 static void dce120_destroy_resource_pool(struct resource_pool **pool) 756 { 757 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 758 759 destruct(dce110_pool); 760 dm_free(dce110_pool); 761 *pool = NULL; 762 } 763 764 static const struct resource_funcs dce120_res_pool_funcs = { 765 .destroy = dce120_destroy_resource_pool, 766 .link_enc_create = dce120_link_encoder_create, 767 .validate_with_context = dce112_validate_with_context, 768 .validate_guaranteed = dce112_validate_guaranteed, 769 .validate_bandwidth = dce112_validate_bandwidth 770 }; 771 772 static void bw_calcs_data_update_from_pplib(struct core_dc *dc) 773 { 774 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 775 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 776 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; 777 int i; 778 unsigned int clk; 779 unsigned int latency; 780 781 /*do system clock*/ 782 if (!dm_pp_get_clock_levels_by_type_with_latency( 783 dc->ctx, 784 DM_PP_CLOCK_TYPE_ENGINE_CLK, 785 &eng_clks) || eng_clks.num_levels == 0) { 786 787 eng_clks.num_levels = 8; 788 clk = 300000; 789 790 for (i = 0; i < eng_clks.num_levels; i++) { 791 eng_clks.data[i].clocks_in_khz = clk; 792 clk += 100000; 793 } 794 } 795 796 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ 797 dc->bw_vbios.high_sclk = bw_frc_to_fixed( 798 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); 799 dc->bw_vbios.mid1_sclk = bw_frc_to_fixed( 800 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); 801 dc->bw_vbios.mid2_sclk = bw_frc_to_fixed( 802 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); 803 dc->bw_vbios.mid3_sclk = bw_frc_to_fixed( 804 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); 805 dc->bw_vbios.mid4_sclk = bw_frc_to_fixed( 806 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); 807 dc->bw_vbios.mid5_sclk = bw_frc_to_fixed( 808 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); 809 dc->bw_vbios.mid6_sclk = bw_frc_to_fixed( 810 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); 811 dc->bw_vbios.low_sclk = bw_frc_to_fixed( 812 eng_clks.data[0].clocks_in_khz, 1000); 813 814 /*do memory clock*/ 815 if (!dm_pp_get_clock_levels_by_type_with_latency( 816 dc->ctx, 817 DM_PP_CLOCK_TYPE_MEMORY_CLK, 818 &mem_clks) || mem_clks.num_levels == 0) { 819 820 mem_clks.num_levels = 3; 821 clk = 250000; 822 latency = 45; 823 824 for (i = 0; i < eng_clks.num_levels; i++) { 825 mem_clks.data[i].clocks_in_khz = clk; 826 mem_clks.data[i].latency_in_us = latency; 827 clk += 500000; 828 latency -= 5; 829 } 830 831 } 832 833 /* we don't need to call PPLIB for validation clock since they 834 * also give us the highest sclk and highest mclk (UMA clock). 835 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): 836 * YCLK = UMACLK*m_memoryTypeMultiplier 837 */ 838 dc->bw_vbios.low_yclk = bw_frc_to_fixed( 839 mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000); 840 dc->bw_vbios.mid_yclk = bw_frc_to_fixed( 841 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 842 1000); 843 dc->bw_vbios.high_yclk = bw_frc_to_fixed( 844 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 845 1000); 846 847 /* Now notify PPLib/SMU about which Watermarks sets they should select 848 * depending on DPM state they are in. And update BW MGR GFX Engine and 849 * Memory clock member variables for Watermarks calculations for each 850 * Watermark Set 851 */ 852 clk_ranges.num_wm_sets = 4; 853 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; 854 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = 855 eng_clks.data[0].clocks_in_khz; 856 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = 857 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 858 clk_ranges.wm_clk_ranges[0].wm_min_memg_clk_in_khz = 859 mem_clks.data[0].clocks_in_khz; 860 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = 861 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 862 863 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; 864 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = 865 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 866 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 867 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; 868 clk_ranges.wm_clk_ranges[1].wm_min_memg_clk_in_khz = 869 mem_clks.data[0].clocks_in_khz; 870 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = 871 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 872 873 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; 874 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = 875 eng_clks.data[0].clocks_in_khz; 876 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = 877 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 878 clk_ranges.wm_clk_ranges[2].wm_min_memg_clk_in_khz = 879 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 880 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 881 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; 882 883 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; 884 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = 885 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 886 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 887 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; 888 clk_ranges.wm_clk_ranges[3].wm_min_memg_clk_in_khz = 889 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 890 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 891 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; 892 893 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 894 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); 895 } 896 897 static bool construct( 898 uint8_t num_virtual_links, 899 struct core_dc *dc, 900 struct dce110_resource_pool *pool) 901 { 902 unsigned int i; 903 struct dc_context *ctx = dc->ctx; 904 struct irq_service_init_data irq_init_data; 905 906 ctx->dc_bios->regs = &bios_regs; 907 908 pool->base.res_cap = &res_cap; 909 pool->base.funcs = &dce120_res_pool_funcs; 910 911 /* TODO: Fill more data from GreenlandAsicCapability.cpp */ 912 pool->base.pipe_count = 6; 913 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 914 915 dc->public.caps.max_downscale_ratio = 200; 916 dc->public.caps.i2c_speed_in_khz = 100; 917 dc->public.caps.max_cursor_size = 128; 918 dc->public.debug = debug_defaults; 919 920 /************************************************* 921 * Create resources * 922 *************************************************/ 923 924 pool->base.clock_sources[DCE120_CLK_SRC_PLL0] = 925 dce120_clock_source_create(ctx, ctx->dc_bios, 926 CLOCK_SOURCE_COMBO_PHY_PLL0, 927 &clk_src_regs[0], false); 928 pool->base.clock_sources[DCE120_CLK_SRC_PLL1] = 929 dce120_clock_source_create(ctx, ctx->dc_bios, 930 CLOCK_SOURCE_COMBO_PHY_PLL1, 931 &clk_src_regs[1], false); 932 pool->base.clock_sources[DCE120_CLK_SRC_PLL2] = 933 dce120_clock_source_create(ctx, ctx->dc_bios, 934 CLOCK_SOURCE_COMBO_PHY_PLL2, 935 &clk_src_regs[2], false); 936 pool->base.clock_sources[DCE120_CLK_SRC_PLL3] = 937 dce120_clock_source_create(ctx, ctx->dc_bios, 938 CLOCK_SOURCE_COMBO_PHY_PLL3, 939 &clk_src_regs[3], false); 940 pool->base.clock_sources[DCE120_CLK_SRC_PLL4] = 941 dce120_clock_source_create(ctx, ctx->dc_bios, 942 CLOCK_SOURCE_COMBO_PHY_PLL4, 943 &clk_src_regs[4], false); 944 pool->base.clock_sources[DCE120_CLK_SRC_PLL5] = 945 dce120_clock_source_create(ctx, ctx->dc_bios, 946 CLOCK_SOURCE_COMBO_PHY_PLL5, 947 &clk_src_regs[5], false); 948 pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL; 949 950 pool->base.dp_clock_source = 951 dce120_clock_source_create(ctx, ctx->dc_bios, 952 CLOCK_SOURCE_ID_DP_DTO, 953 &clk_src_regs[0], true); 954 955 for (i = 0; i < pool->base.clk_src_count; i++) { 956 if (pool->base.clock_sources[i] == NULL) { 957 dm_error("DC: failed to create clock sources!\n"); 958 BREAK_TO_DEBUGGER(); 959 goto clk_src_create_fail; 960 } 961 } 962 963 pool->base.display_clock = dce120_disp_clk_create(ctx, 964 &disp_clk_regs, 965 &disp_clk_shift, 966 &disp_clk_mask); 967 if (pool->base.display_clock == NULL) { 968 dm_error("DC: failed to create display clock!\n"); 969 BREAK_TO_DEBUGGER(); 970 goto disp_clk_create_fail; 971 } 972 973 pool->base.dmcu = dce_dmcu_create(ctx, 974 &dmcu_regs, 975 &dmcu_shift, 976 &dmcu_mask); 977 if (pool->base.dmcu == NULL) { 978 dm_error("DC: failed to create dmcu!\n"); 979 BREAK_TO_DEBUGGER(); 980 goto res_create_fail; 981 } 982 983 pool->base.abm = dce_abm_create(ctx, 984 &abm_regs, 985 &abm_shift, 986 &abm_mask); 987 if (pool->base.abm == NULL) { 988 dm_error("DC: failed to create abm!\n"); 989 BREAK_TO_DEBUGGER(); 990 goto res_create_fail; 991 } 992 993 irq_init_data.ctx = dc->ctx; 994 pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data); 995 if (!pool->base.irqs) 996 goto irqs_create_fail; 997 998 for (i = 0; i < pool->base.pipe_count; i++) { 999 pool->base.timing_generators[i] = 1000 dce120_timing_generator_create( 1001 ctx, 1002 i, 1003 &dce120_tg_offsets[i]); 1004 if (pool->base.timing_generators[i] == NULL) { 1005 BREAK_TO_DEBUGGER(); 1006 dm_error("DC: failed to create tg!\n"); 1007 goto controller_create_fail; 1008 } 1009 1010 pool->base.mis[i] = dce120_mem_input_create(ctx, 1011 i, &dce120_mi_reg_offsets[i]); 1012 1013 if (pool->base.mis[i] == NULL) { 1014 BREAK_TO_DEBUGGER(); 1015 dm_error( 1016 "DC: failed to create memory input!\n"); 1017 goto controller_create_fail; 1018 } 1019 1020 pool->base.ipps[i] = dce120_ipp_create(ctx, i); 1021 if (pool->base.ipps[i] == NULL) { 1022 BREAK_TO_DEBUGGER(); 1023 dm_error( 1024 "DC: failed to create input pixel processor!\n"); 1025 goto controller_create_fail; 1026 } 1027 1028 pool->base.transforms[i] = dce120_transform_create(ctx, i); 1029 if (pool->base.transforms[i] == NULL) { 1030 BREAK_TO_DEBUGGER(); 1031 dm_error( 1032 "DC: failed to create transform!\n"); 1033 goto res_create_fail; 1034 } 1035 1036 pool->base.opps[i] = dce120_opp_create( 1037 ctx, 1038 i); 1039 if (pool->base.opps[i] == NULL) { 1040 BREAK_TO_DEBUGGER(); 1041 dm_error( 1042 "DC: failed to create output pixel processor!\n"); 1043 } 1044 } 1045 1046 if (!resource_construct(num_virtual_links, dc, &pool->base, 1047 &res_create_funcs)) 1048 goto res_create_fail; 1049 1050 /* Create hardware sequencer */ 1051 if (!dce120_hw_sequencer_create(dc)) 1052 goto controller_create_fail; 1053 1054 dc->public.caps.max_surfaces = pool->base.pipe_count; 1055 1056 bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id); 1057 1058 bw_calcs_data_update_from_pplib(dc); 1059 1060 return true; 1061 1062 irqs_create_fail: 1063 controller_create_fail: 1064 disp_clk_create_fail: 1065 clk_src_create_fail: 1066 res_create_fail: 1067 1068 destruct(pool); 1069 1070 return false; 1071 } 1072 1073 struct resource_pool *dce120_create_resource_pool( 1074 uint8_t num_virtual_links, 1075 struct core_dc *dc) 1076 { 1077 struct dce110_resource_pool *pool = 1078 dm_alloc(sizeof(struct dce110_resource_pool)); 1079 1080 if (!pool) 1081 return NULL; 1082 1083 if (construct(num_virtual_links, dc, pool)) 1084 return &pool->base; 1085 1086 BREAK_TO_DEBUGGER(); 1087 return NULL; 1088 } 1089