1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc.cls 3 * 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include <linux/slab.h> 28 29 #include "dm_services.h" 30 31 32 #include "stream_encoder.h" 33 #include "resource.h" 34 #include "include/irq_service_interface.h" 35 #include "dce120_resource.h" 36 37 #include "dce112/dce112_resource.h" 38 39 #include "dce110/dce110_resource.h" 40 #include "../virtual/virtual_stream_encoder.h" 41 #include "dce120_timing_generator.h" 42 #include "irq/dce120/irq_service_dce120.h" 43 #include "dce/dce_opp.h" 44 #include "dce/dce_clock_source.h" 45 #include "dce/dce_ipp.h" 46 #include "dce/dce_mem_input.h" 47 #include "dce/dce_panel_cntl.h" 48 49 #include "dce110/dce110_hw_sequencer.h" 50 #include "dce120/dce120_hw_sequencer.h" 51 #include "dce/dce_transform.h" 52 #include "clk_mgr.h" 53 #include "dce/dce_audio.h" 54 #include "dce/dce_link_encoder.h" 55 #include "dce/dce_stream_encoder.h" 56 #include "dce/dce_hwseq.h" 57 #include "dce/dce_abm.h" 58 #include "dce/dce_dmcu.h" 59 #include "dce/dce_aux.h" 60 #include "dce/dce_i2c.h" 61 62 #include "dce/dce_12_0_offset.h" 63 #include "dce/dce_12_0_sh_mask.h" 64 #include "soc15_hw_ip.h" 65 #include "vega10_ip_offset.h" 66 #include "nbio/nbio_6_1_offset.h" 67 #include "mmhub/mmhub_1_0_offset.h" 68 #include "mmhub/mmhub_1_0_sh_mask.h" 69 #include "reg_helper.h" 70 71 #include "dce100/dce100_resource.h" 72 73 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 74 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 75 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 76 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 77 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 78 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 79 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 80 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 81 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 82 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 83 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 84 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 85 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 86 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 87 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 88 #endif 89 90 enum dce120_clk_src_array_id { 91 DCE120_CLK_SRC_PLL0, 92 DCE120_CLK_SRC_PLL1, 93 DCE120_CLK_SRC_PLL2, 94 DCE120_CLK_SRC_PLL3, 95 DCE120_CLK_SRC_PLL4, 96 DCE120_CLK_SRC_PLL5, 97 98 DCE120_CLK_SRC_TOTAL 99 }; 100 101 static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = { 102 { 103 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 104 }, 105 { 106 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 107 }, 108 { 109 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 110 }, 111 { 112 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 113 }, 114 { 115 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 116 }, 117 { 118 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 119 } 120 }; 121 122 /* begin ********************* 123 * macros to expend register list macro defined in HW object header file */ 124 125 #define BASE_INNER(seg) \ 126 DCE_BASE__INST0_SEG ## seg 127 128 #define NBIO_BASE_INNER(seg) \ 129 NBIF_BASE__INST0_SEG ## seg 130 131 #define NBIO_BASE(seg) \ 132 NBIO_BASE_INNER(seg) 133 134 /* compile time expand base address. */ 135 #define BASE(seg) \ 136 BASE_INNER(seg) 137 138 #define SR(reg_name)\ 139 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 140 mm ## reg_name 141 142 #define SRI(reg_name, block, id)\ 143 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 144 mm ## block ## id ## _ ## reg_name 145 146 /* MMHUB */ 147 #define MMHUB_BASE_INNER(seg) \ 148 MMHUB_BASE__INST0_SEG ## seg 149 150 #define MMHUB_BASE(seg) \ 151 MMHUB_BASE_INNER(seg) 152 153 #define MMHUB_SR(reg_name)\ 154 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 155 mm ## reg_name 156 157 /* macros to expend register list macro defined in HW object header file 158 * end *********************/ 159 160 161 static const struct dce_dmcu_registers dmcu_regs = { 162 DMCU_DCE110_COMMON_REG_LIST() 163 }; 164 165 static const struct dce_dmcu_shift dmcu_shift = { 166 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 167 }; 168 169 static const struct dce_dmcu_mask dmcu_mask = { 170 DMCU_MASK_SH_LIST_DCE110(_MASK) 171 }; 172 173 static const struct dce_abm_registers abm_regs = { 174 ABM_DCE110_COMMON_REG_LIST() 175 }; 176 177 static const struct dce_abm_shift abm_shift = { 178 ABM_MASK_SH_LIST_DCE110(__SHIFT) 179 }; 180 181 static const struct dce_abm_mask abm_mask = { 182 ABM_MASK_SH_LIST_DCE110(_MASK) 183 }; 184 185 #define ipp_regs(id)\ 186 [id] = {\ 187 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 188 } 189 190 static const struct dce_ipp_registers ipp_regs[] = { 191 ipp_regs(0), 192 ipp_regs(1), 193 ipp_regs(2), 194 ipp_regs(3), 195 ipp_regs(4), 196 ipp_regs(5) 197 }; 198 199 static const struct dce_ipp_shift ipp_shift = { 200 IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT) 201 }; 202 203 static const struct dce_ipp_mask ipp_mask = { 204 IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK) 205 }; 206 207 #define transform_regs(id)\ 208 [id] = {\ 209 XFM_COMMON_REG_LIST_DCE110(id)\ 210 } 211 212 static const struct dce_transform_registers xfm_regs[] = { 213 transform_regs(0), 214 transform_regs(1), 215 transform_regs(2), 216 transform_regs(3), 217 transform_regs(4), 218 transform_regs(5) 219 }; 220 221 static const struct dce_transform_shift xfm_shift = { 222 XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT) 223 }; 224 225 static const struct dce_transform_mask xfm_mask = { 226 XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK) 227 }; 228 229 #define aux_regs(id)\ 230 [id] = {\ 231 AUX_REG_LIST(id)\ 232 } 233 234 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 235 aux_regs(0), 236 aux_regs(1), 237 aux_regs(2), 238 aux_regs(3), 239 aux_regs(4), 240 aux_regs(5) 241 }; 242 243 #define hpd_regs(id)\ 244 [id] = {\ 245 HPD_REG_LIST(id)\ 246 } 247 248 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 249 hpd_regs(0), 250 hpd_regs(1), 251 hpd_regs(2), 252 hpd_regs(3), 253 hpd_regs(4), 254 hpd_regs(5) 255 }; 256 257 #define link_regs(id)\ 258 [id] = {\ 259 LE_DCE120_REG_LIST(id), \ 260 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 261 } 262 263 static const struct dce110_link_enc_registers link_enc_regs[] = { 264 link_regs(0), 265 link_regs(1), 266 link_regs(2), 267 link_regs(3), 268 link_regs(4), 269 link_regs(5), 270 link_regs(6), 271 }; 272 273 274 #define stream_enc_regs(id)\ 275 [id] = {\ 276 SE_COMMON_REG_LIST(id),\ 277 .TMDS_CNTL = 0,\ 278 } 279 280 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 281 stream_enc_regs(0), 282 stream_enc_regs(1), 283 stream_enc_regs(2), 284 stream_enc_regs(3), 285 stream_enc_regs(4), 286 stream_enc_regs(5) 287 }; 288 289 static const struct dce_stream_encoder_shift se_shift = { 290 SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT) 291 }; 292 293 static const struct dce_stream_encoder_mask se_mask = { 294 SE_COMMON_MASK_SH_LIST_DCE120(_MASK) 295 }; 296 297 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 298 { DCE_PANEL_CNTL_REG_LIST() } 299 }; 300 301 static const struct dce_panel_cntl_shift panel_cntl_shift = { 302 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 303 }; 304 305 static const struct dce_panel_cntl_mask panel_cntl_mask = { 306 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 307 }; 308 309 static const struct dce110_aux_registers_shift aux_shift = { 310 DCE12_AUX_MASK_SH_LIST(__SHIFT) 311 }; 312 313 static const struct dce110_aux_registers_mask aux_mask = { 314 DCE12_AUX_MASK_SH_LIST(_MASK) 315 }; 316 317 #define opp_regs(id)\ 318 [id] = {\ 319 OPP_DCE_120_REG_LIST(id),\ 320 } 321 322 static const struct dce_opp_registers opp_regs[] = { 323 opp_regs(0), 324 opp_regs(1), 325 opp_regs(2), 326 opp_regs(3), 327 opp_regs(4), 328 opp_regs(5) 329 }; 330 331 static const struct dce_opp_shift opp_shift = { 332 OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT) 333 }; 334 335 static const struct dce_opp_mask opp_mask = { 336 OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK) 337 }; 338 #define aux_engine_regs(id)\ 339 [id] = {\ 340 AUX_COMMON_REG_LIST(id), \ 341 .AUX_RESET_MASK = 0 \ 342 } 343 344 static const struct dce110_aux_registers aux_engine_regs[] = { 345 aux_engine_regs(0), 346 aux_engine_regs(1), 347 aux_engine_regs(2), 348 aux_engine_regs(3), 349 aux_engine_regs(4), 350 aux_engine_regs(5) 351 }; 352 353 #define audio_regs(id)\ 354 [id] = {\ 355 AUD_COMMON_REG_LIST(id)\ 356 } 357 358 static const struct dce_audio_registers audio_regs[] = { 359 audio_regs(0), 360 audio_regs(1), 361 audio_regs(2), 362 audio_regs(3), 363 audio_regs(4), 364 audio_regs(5) 365 }; 366 367 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 368 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 369 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 370 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 371 372 static const struct dce_audio_shift audio_shift = { 373 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 374 }; 375 376 static const struct dce_audio_mask audio_mask = { 377 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 378 }; 379 380 static int map_transmitter_id_to_phy_instance( 381 enum transmitter transmitter) 382 { 383 switch (transmitter) { 384 case TRANSMITTER_UNIPHY_A: 385 return 0; 386 break; 387 case TRANSMITTER_UNIPHY_B: 388 return 1; 389 break; 390 case TRANSMITTER_UNIPHY_C: 391 return 2; 392 break; 393 case TRANSMITTER_UNIPHY_D: 394 return 3; 395 break; 396 case TRANSMITTER_UNIPHY_E: 397 return 4; 398 break; 399 case TRANSMITTER_UNIPHY_F: 400 return 5; 401 break; 402 case TRANSMITTER_UNIPHY_G: 403 return 6; 404 break; 405 default: 406 ASSERT(0); 407 return 0; 408 } 409 } 410 411 #define clk_src_regs(index, id)\ 412 [index] = {\ 413 CS_COMMON_REG_LIST_DCE_112(id),\ 414 } 415 416 static const struct dce110_clk_src_regs clk_src_regs[] = { 417 clk_src_regs(0, A), 418 clk_src_regs(1, B), 419 clk_src_regs(2, C), 420 clk_src_regs(3, D), 421 clk_src_regs(4, E), 422 clk_src_regs(5, F) 423 }; 424 425 static const struct dce110_clk_src_shift cs_shift = { 426 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 427 }; 428 429 static const struct dce110_clk_src_mask cs_mask = { 430 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) 431 }; 432 433 struct output_pixel_processor *dce120_opp_create( 434 struct dc_context *ctx, 435 uint32_t inst) 436 { 437 struct dce110_opp *opp = 438 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 439 440 if (!opp) 441 return NULL; 442 443 dce110_opp_construct(opp, 444 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 445 return &opp->base; 446 } 447 struct dce_aux *dce120_aux_engine_create( 448 struct dc_context *ctx, 449 uint32_t inst) 450 { 451 struct aux_engine_dce110 *aux_engine = 452 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 453 454 if (!aux_engine) 455 return NULL; 456 457 dce110_aux_engine_construct(aux_engine, ctx, inst, 458 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 459 &aux_engine_regs[inst], 460 &aux_mask, 461 &aux_shift, 462 ctx->dc->caps.extended_aux_timeout_support); 463 464 return &aux_engine->base; 465 } 466 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 467 468 static const struct dce_i2c_registers i2c_hw_regs[] = { 469 i2c_inst_regs(1), 470 i2c_inst_regs(2), 471 i2c_inst_regs(3), 472 i2c_inst_regs(4), 473 i2c_inst_regs(5), 474 i2c_inst_regs(6), 475 }; 476 477 static const struct dce_i2c_shift i2c_shifts = { 478 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 479 }; 480 481 static const struct dce_i2c_mask i2c_masks = { 482 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 483 }; 484 485 struct dce_i2c_hw *dce120_i2c_hw_create( 486 struct dc_context *ctx, 487 uint32_t inst) 488 { 489 struct dce_i2c_hw *dce_i2c_hw = 490 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 491 492 if (!dce_i2c_hw) 493 return NULL; 494 495 dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst, 496 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 497 498 return dce_i2c_hw; 499 } 500 static const struct bios_registers bios_regs = { 501 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + NBIO_BASE(mmBIOS_SCRATCH_3_BASE_IDX), 502 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX) 503 }; 504 505 static const struct resource_caps res_cap = { 506 .num_timing_generator = 6, 507 .num_audio = 7, 508 .num_stream_encoder = 6, 509 .num_pll = 6, 510 .num_ddc = 6, 511 }; 512 513 static const struct dc_plane_cap plane_cap = { 514 .type = DC_PLANE_TYPE_DCE_RGB, 515 516 .pixel_format_support = { 517 .argb8888 = true, 518 .nv12 = false, 519 .fp16 = true 520 }, 521 522 .max_upscale_factor = { 523 .argb8888 = 16000, 524 .nv12 = 1, 525 .fp16 = 1 526 }, 527 528 .max_downscale_factor = { 529 .argb8888 = 250, 530 .nv12 = 1, 531 .fp16 = 1 532 } 533 }; 534 535 static const struct dc_debug_options debug_defaults = { 536 .disable_clock_gate = true, 537 }; 538 539 static struct clock_source *dce120_clock_source_create( 540 struct dc_context *ctx, 541 struct dc_bios *bios, 542 enum clock_source_id id, 543 const struct dce110_clk_src_regs *regs, 544 bool dp_clk_src) 545 { 546 struct dce110_clk_src *clk_src = 547 kzalloc(sizeof(*clk_src), GFP_KERNEL); 548 549 if (!clk_src) 550 return NULL; 551 552 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 553 regs, &cs_shift, &cs_mask)) { 554 clk_src->base.dp_clk_src = dp_clk_src; 555 return &clk_src->base; 556 } 557 558 kfree(clk_src); 559 BREAK_TO_DEBUGGER(); 560 return NULL; 561 } 562 563 static void dce120_clock_source_destroy(struct clock_source **clk_src) 564 { 565 kfree(TO_DCE110_CLK_SRC(*clk_src)); 566 *clk_src = NULL; 567 } 568 569 570 static bool dce120_hw_sequencer_create(struct dc *dc) 571 { 572 /* All registers used by dce11.2 match those in dce11 in offset and 573 * structure 574 */ 575 dce120_hw_sequencer_construct(dc); 576 577 /*TODO Move to separate file and Override what is needed */ 578 579 return true; 580 } 581 582 static struct timing_generator *dce120_timing_generator_create( 583 struct dc_context *ctx, 584 uint32_t instance, 585 const struct dce110_timing_generator_offsets *offsets) 586 { 587 struct dce110_timing_generator *tg110 = 588 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 589 590 if (!tg110) 591 return NULL; 592 593 dce120_timing_generator_construct(tg110, ctx, instance, offsets); 594 return &tg110->base; 595 } 596 597 static void dce120_transform_destroy(struct transform **xfm) 598 { 599 kfree(TO_DCE_TRANSFORM(*xfm)); 600 *xfm = NULL; 601 } 602 603 static void dce120_resource_destruct(struct dce110_resource_pool *pool) 604 { 605 unsigned int i; 606 607 for (i = 0; i < pool->base.pipe_count; i++) { 608 if (pool->base.opps[i] != NULL) 609 dce110_opp_destroy(&pool->base.opps[i]); 610 611 if (pool->base.transforms[i] != NULL) 612 dce120_transform_destroy(&pool->base.transforms[i]); 613 614 if (pool->base.ipps[i] != NULL) 615 dce_ipp_destroy(&pool->base.ipps[i]); 616 617 if (pool->base.mis[i] != NULL) { 618 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 619 pool->base.mis[i] = NULL; 620 } 621 622 if (pool->base.irqs != NULL) { 623 dal_irq_service_destroy(&pool->base.irqs); 624 } 625 626 if (pool->base.timing_generators[i] != NULL) { 627 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 628 pool->base.timing_generators[i] = NULL; 629 } 630 } 631 632 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 633 if (pool->base.engines[i] != NULL) 634 dce110_engine_destroy(&pool->base.engines[i]); 635 if (pool->base.hw_i2cs[i] != NULL) { 636 kfree(pool->base.hw_i2cs[i]); 637 pool->base.hw_i2cs[i] = NULL; 638 } 639 if (pool->base.sw_i2cs[i] != NULL) { 640 kfree(pool->base.sw_i2cs[i]); 641 pool->base.sw_i2cs[i] = NULL; 642 } 643 } 644 645 for (i = 0; i < pool->base.audio_count; i++) { 646 if (pool->base.audios[i]) 647 dce_aud_destroy(&pool->base.audios[i]); 648 } 649 650 for (i = 0; i < pool->base.stream_enc_count; i++) { 651 if (pool->base.stream_enc[i] != NULL) 652 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 653 } 654 655 for (i = 0; i < pool->base.clk_src_count; i++) { 656 if (pool->base.clock_sources[i] != NULL) 657 dce120_clock_source_destroy( 658 &pool->base.clock_sources[i]); 659 } 660 661 if (pool->base.dp_clock_source != NULL) 662 dce120_clock_source_destroy(&pool->base.dp_clock_source); 663 664 if (pool->base.abm != NULL) 665 dce_abm_destroy(&pool->base.abm); 666 667 if (pool->base.dmcu != NULL) 668 dce_dmcu_destroy(&pool->base.dmcu); 669 } 670 671 static void read_dce_straps( 672 struct dc_context *ctx, 673 struct resource_straps *straps) 674 { 675 uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0); 676 677 straps->audio_stream_number = get_reg_field_value(reg_val, 678 CC_DC_MISC_STRAPS, 679 AUDIO_STREAM_NUMBER); 680 straps->hdmi_disable = get_reg_field_value(reg_val, 681 CC_DC_MISC_STRAPS, 682 HDMI_DISABLE); 683 684 reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0); 685 straps->dc_pinstraps_audio = get_reg_field_value(reg_val, 686 DC_PINSTRAPS, 687 DC_PINSTRAPS_AUDIO); 688 } 689 690 static struct audio *create_audio( 691 struct dc_context *ctx, unsigned int inst) 692 { 693 return dce_audio_create(ctx, inst, 694 &audio_regs[inst], &audio_shift, &audio_mask); 695 } 696 697 static const struct encoder_feature_support link_enc_feature = { 698 .max_hdmi_deep_color = COLOR_DEPTH_121212, 699 .max_hdmi_pixel_clock = 600000, 700 .hdmi_ycbcr420_supported = true, 701 .dp_ycbcr420_supported = false, 702 .flags.bits.IS_HBR2_CAPABLE = true, 703 .flags.bits.IS_HBR3_CAPABLE = true, 704 .flags.bits.IS_TPS3_CAPABLE = true, 705 .flags.bits.IS_TPS4_CAPABLE = true, 706 }; 707 708 static struct link_encoder *dce120_link_encoder_create( 709 const struct encoder_init_data *enc_init_data) 710 { 711 struct dce110_link_encoder *enc110 = 712 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 713 int link_regs_id; 714 715 if (!enc110) 716 return NULL; 717 718 link_regs_id = 719 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 720 721 dce110_link_encoder_construct(enc110, 722 enc_init_data, 723 &link_enc_feature, 724 &link_enc_regs[link_regs_id], 725 &link_enc_aux_regs[enc_init_data->channel - 1], 726 &link_enc_hpd_regs[enc_init_data->hpd_source]); 727 728 return &enc110->base; 729 } 730 731 static struct panel_cntl *dce120_panel_cntl_create(const struct panel_cntl_init_data *init_data) 732 { 733 struct dce_panel_cntl *panel_cntl = 734 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 735 736 if (!panel_cntl) 737 return NULL; 738 739 dce_panel_cntl_construct(panel_cntl, 740 init_data, 741 &panel_cntl_regs[init_data->inst], 742 &panel_cntl_shift, 743 &panel_cntl_mask); 744 745 return &panel_cntl->base; 746 } 747 748 static struct input_pixel_processor *dce120_ipp_create( 749 struct dc_context *ctx, uint32_t inst) 750 { 751 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 752 753 if (!ipp) { 754 BREAK_TO_DEBUGGER(); 755 return NULL; 756 } 757 758 dce_ipp_construct(ipp, ctx, inst, 759 &ipp_regs[inst], &ipp_shift, &ipp_mask); 760 return &ipp->base; 761 } 762 763 static struct stream_encoder *dce120_stream_encoder_create( 764 enum engine_id eng_id, 765 struct dc_context *ctx) 766 { 767 struct dce110_stream_encoder *enc110 = 768 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 769 770 if (!enc110) 771 return NULL; 772 773 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 774 &stream_enc_regs[eng_id], 775 &se_shift, &se_mask); 776 return &enc110->base; 777 } 778 779 #define SRII(reg_name, block, id)\ 780 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 781 mm ## block ## id ## _ ## reg_name 782 783 static const struct dce_hwseq_registers hwseq_reg = { 784 HWSEQ_DCE120_REG_LIST() 785 }; 786 787 static const struct dce_hwseq_shift hwseq_shift = { 788 HWSEQ_DCE12_MASK_SH_LIST(__SHIFT) 789 }; 790 791 static const struct dce_hwseq_mask hwseq_mask = { 792 HWSEQ_DCE12_MASK_SH_LIST(_MASK) 793 }; 794 795 /* HWSEQ regs for VG20 */ 796 static const struct dce_hwseq_registers dce121_hwseq_reg = { 797 HWSEQ_VG20_REG_LIST() 798 }; 799 800 static const struct dce_hwseq_shift dce121_hwseq_shift = { 801 HWSEQ_VG20_MASK_SH_LIST(__SHIFT) 802 }; 803 804 static const struct dce_hwseq_mask dce121_hwseq_mask = { 805 HWSEQ_VG20_MASK_SH_LIST(_MASK) 806 }; 807 808 static struct dce_hwseq *dce120_hwseq_create( 809 struct dc_context *ctx) 810 { 811 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 812 813 if (hws) { 814 hws->ctx = ctx; 815 hws->regs = &hwseq_reg; 816 hws->shifts = &hwseq_shift; 817 hws->masks = &hwseq_mask; 818 } 819 return hws; 820 } 821 822 static struct dce_hwseq *dce121_hwseq_create( 823 struct dc_context *ctx) 824 { 825 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 826 827 if (hws) { 828 hws->ctx = ctx; 829 hws->regs = &dce121_hwseq_reg; 830 hws->shifts = &dce121_hwseq_shift; 831 hws->masks = &dce121_hwseq_mask; 832 } 833 return hws; 834 } 835 836 static const struct resource_create_funcs res_create_funcs = { 837 .read_dce_straps = read_dce_straps, 838 .create_audio = create_audio, 839 .create_stream_encoder = dce120_stream_encoder_create, 840 .create_hwseq = dce120_hwseq_create, 841 }; 842 843 static const struct resource_create_funcs dce121_res_create_funcs = { 844 .read_dce_straps = read_dce_straps, 845 .create_audio = create_audio, 846 .create_stream_encoder = dce120_stream_encoder_create, 847 .create_hwseq = dce121_hwseq_create, 848 }; 849 850 851 #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) } 852 static const struct dce_mem_input_registers mi_regs[] = { 853 mi_inst_regs(0), 854 mi_inst_regs(1), 855 mi_inst_regs(2), 856 mi_inst_regs(3), 857 mi_inst_regs(4), 858 mi_inst_regs(5), 859 }; 860 861 static const struct dce_mem_input_shift mi_shifts = { 862 MI_DCE12_MASK_SH_LIST(__SHIFT) 863 }; 864 865 static const struct dce_mem_input_mask mi_masks = { 866 MI_DCE12_MASK_SH_LIST(_MASK) 867 }; 868 869 static struct mem_input *dce120_mem_input_create( 870 struct dc_context *ctx, 871 uint32_t inst) 872 { 873 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 874 GFP_KERNEL); 875 876 if (!dce_mi) { 877 BREAK_TO_DEBUGGER(); 878 return NULL; 879 } 880 881 dce120_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 882 return &dce_mi->base; 883 } 884 885 static struct transform *dce120_transform_create( 886 struct dc_context *ctx, 887 uint32_t inst) 888 { 889 struct dce_transform *transform = 890 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 891 892 if (!transform) 893 return NULL; 894 895 dce_transform_construct(transform, ctx, inst, 896 &xfm_regs[inst], &xfm_shift, &xfm_mask); 897 transform->lb_memory_size = 0x1404; /*5124*/ 898 return &transform->base; 899 } 900 901 static void dce120_destroy_resource_pool(struct resource_pool **pool) 902 { 903 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 904 905 dce120_resource_destruct(dce110_pool); 906 kfree(dce110_pool); 907 *pool = NULL; 908 } 909 910 static const struct resource_funcs dce120_res_pool_funcs = { 911 .destroy = dce120_destroy_resource_pool, 912 .link_enc_create = dce120_link_encoder_create, 913 .panel_cntl_create = dce120_panel_cntl_create, 914 .validate_bandwidth = dce112_validate_bandwidth, 915 .validate_plane = dce100_validate_plane, 916 .add_stream_to_ctx = dce112_add_stream_to_ctx, 917 .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link 918 }; 919 920 static void bw_calcs_data_update_from_pplib(struct dc *dc) 921 { 922 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 923 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 924 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; 925 int i; 926 unsigned int clk; 927 unsigned int latency; 928 /*original logic in dal3*/ 929 int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ; 930 931 /*do system clock*/ 932 if (!dm_pp_get_clock_levels_by_type_with_latency( 933 dc->ctx, 934 DM_PP_CLOCK_TYPE_ENGINE_CLK, 935 &eng_clks) || eng_clks.num_levels == 0) { 936 937 eng_clks.num_levels = 8; 938 clk = 300000; 939 940 for (i = 0; i < eng_clks.num_levels; i++) { 941 eng_clks.data[i].clocks_in_khz = clk; 942 clk += 100000; 943 } 944 } 945 946 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ 947 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 948 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); 949 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 950 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); 951 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 952 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); 953 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 954 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); 955 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 956 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); 957 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 958 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); 959 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 960 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); 961 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 962 eng_clks.data[0].clocks_in_khz, 1000); 963 964 /*do memory clock*/ 965 if (!dm_pp_get_clock_levels_by_type_with_latency( 966 dc->ctx, 967 DM_PP_CLOCK_TYPE_MEMORY_CLK, 968 &mem_clks) || mem_clks.num_levels == 0) { 969 970 mem_clks.num_levels = 3; 971 clk = 250000; 972 latency = 45; 973 974 for (i = 0; i < eng_clks.num_levels; i++) { 975 mem_clks.data[i].clocks_in_khz = clk; 976 mem_clks.data[i].latency_in_us = latency; 977 clk += 500000; 978 latency -= 5; 979 } 980 981 } 982 983 /* we don't need to call PPLIB for validation clock since they 984 * also give us the highest sclk and highest mclk (UMA clock). 985 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): 986 * YCLK = UMACLK*m_memoryTypeMultiplier 987 */ 988 if (dc->bw_vbios->memory_type == bw_def_hbm) 989 memory_type_multiplier = MEMORY_TYPE_HBM; 990 991 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 992 mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000); 993 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 994 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier, 995 1000); 996 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 997 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier, 998 1000); 999 1000 /* Now notify PPLib/SMU about which Watermarks sets they should select 1001 * depending on DPM state they are in. And update BW MGR GFX Engine and 1002 * Memory clock member variables for Watermarks calculations for each 1003 * Watermark Set 1004 */ 1005 clk_ranges.num_wm_sets = 4; 1006 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; 1007 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = 1008 eng_clks.data[0].clocks_in_khz; 1009 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = 1010 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 1011 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz = 1012 mem_clks.data[0].clocks_in_khz; 1013 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = 1014 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 1015 1016 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; 1017 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = 1018 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 1019 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 1020 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; 1021 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz = 1022 mem_clks.data[0].clocks_in_khz; 1023 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = 1024 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 1025 1026 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; 1027 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = 1028 eng_clks.data[0].clocks_in_khz; 1029 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = 1030 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 1031 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz = 1032 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 1033 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 1034 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; 1035 1036 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; 1037 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = 1038 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 1039 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 1040 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; 1041 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz = 1042 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 1043 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 1044 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; 1045 1046 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 1047 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); 1048 } 1049 1050 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1051 { 1052 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); 1053 /* VG20 support max 6 pipes */ 1054 value = value & 0x3f; 1055 return value; 1056 } 1057 1058 static bool dce120_resource_construct( 1059 uint8_t num_virtual_links, 1060 struct dc *dc, 1061 struct dce110_resource_pool *pool) 1062 { 1063 unsigned int i; 1064 int j; 1065 struct dc_context *ctx = dc->ctx; 1066 struct irq_service_init_data irq_init_data; 1067 static const struct resource_create_funcs *res_funcs; 1068 bool is_vg20 = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev); 1069 uint32_t pipe_fuses; 1070 1071 ctx->dc_bios->regs = &bios_regs; 1072 1073 pool->base.res_cap = &res_cap; 1074 pool->base.funcs = &dce120_res_pool_funcs; 1075 1076 /* TODO: Fill more data from GreenlandAsicCapability.cpp */ 1077 pool->base.pipe_count = res_cap.num_timing_generator; 1078 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1079 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1080 1081 dc->caps.max_downscale_ratio = 200; 1082 dc->caps.i2c_speed_in_khz = 100; 1083 dc->caps.max_cursor_size = 128; 1084 dc->caps.dual_link_dvi = true; 1085 dc->caps.psp_setup_panel_mode = true; 1086 dc->caps.extended_aux_timeout_support = false; 1087 dc->debug = debug_defaults; 1088 1089 /************************************************* 1090 * Create resources * 1091 *************************************************/ 1092 1093 pool->base.clock_sources[DCE120_CLK_SRC_PLL0] = 1094 dce120_clock_source_create(ctx, ctx->dc_bios, 1095 CLOCK_SOURCE_COMBO_PHY_PLL0, 1096 &clk_src_regs[0], false); 1097 pool->base.clock_sources[DCE120_CLK_SRC_PLL1] = 1098 dce120_clock_source_create(ctx, ctx->dc_bios, 1099 CLOCK_SOURCE_COMBO_PHY_PLL1, 1100 &clk_src_regs[1], false); 1101 pool->base.clock_sources[DCE120_CLK_SRC_PLL2] = 1102 dce120_clock_source_create(ctx, ctx->dc_bios, 1103 CLOCK_SOURCE_COMBO_PHY_PLL2, 1104 &clk_src_regs[2], false); 1105 pool->base.clock_sources[DCE120_CLK_SRC_PLL3] = 1106 dce120_clock_source_create(ctx, ctx->dc_bios, 1107 CLOCK_SOURCE_COMBO_PHY_PLL3, 1108 &clk_src_regs[3], false); 1109 pool->base.clock_sources[DCE120_CLK_SRC_PLL4] = 1110 dce120_clock_source_create(ctx, ctx->dc_bios, 1111 CLOCK_SOURCE_COMBO_PHY_PLL4, 1112 &clk_src_regs[4], false); 1113 pool->base.clock_sources[DCE120_CLK_SRC_PLL5] = 1114 dce120_clock_source_create(ctx, ctx->dc_bios, 1115 CLOCK_SOURCE_COMBO_PHY_PLL5, 1116 &clk_src_regs[5], false); 1117 pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL; 1118 1119 pool->base.dp_clock_source = 1120 dce120_clock_source_create(ctx, ctx->dc_bios, 1121 CLOCK_SOURCE_ID_DP_DTO, 1122 &clk_src_regs[0], true); 1123 1124 for (i = 0; i < pool->base.clk_src_count; i++) { 1125 if (pool->base.clock_sources[i] == NULL) { 1126 dm_error("DC: failed to create clock sources!\n"); 1127 BREAK_TO_DEBUGGER(); 1128 goto clk_src_create_fail; 1129 } 1130 } 1131 1132 pool->base.dmcu = dce_dmcu_create(ctx, 1133 &dmcu_regs, 1134 &dmcu_shift, 1135 &dmcu_mask); 1136 if (pool->base.dmcu == NULL) { 1137 dm_error("DC: failed to create dmcu!\n"); 1138 BREAK_TO_DEBUGGER(); 1139 goto res_create_fail; 1140 } 1141 1142 pool->base.abm = dce_abm_create(ctx, 1143 &abm_regs, 1144 &abm_shift, 1145 &abm_mask); 1146 if (pool->base.abm == NULL) { 1147 dm_error("DC: failed to create abm!\n"); 1148 BREAK_TO_DEBUGGER(); 1149 goto res_create_fail; 1150 } 1151 1152 1153 irq_init_data.ctx = dc->ctx; 1154 pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data); 1155 if (!pool->base.irqs) 1156 goto irqs_create_fail; 1157 1158 /* VG20: Pipe harvesting enabled, retrieve valid pipe fuses */ 1159 if (is_vg20) 1160 pipe_fuses = read_pipe_fuses(ctx); 1161 1162 /* index to valid pipe resource */ 1163 j = 0; 1164 for (i = 0; i < pool->base.pipe_count; i++) { 1165 if (is_vg20) { 1166 if ((pipe_fuses & (1 << i)) != 0) { 1167 dm_error("DC: skip invalid pipe %d!\n", i); 1168 continue; 1169 } 1170 } 1171 1172 pool->base.timing_generators[j] = 1173 dce120_timing_generator_create( 1174 ctx, 1175 i, 1176 &dce120_tg_offsets[i]); 1177 if (pool->base.timing_generators[j] == NULL) { 1178 BREAK_TO_DEBUGGER(); 1179 dm_error("DC: failed to create tg!\n"); 1180 goto controller_create_fail; 1181 } 1182 1183 pool->base.mis[j] = dce120_mem_input_create(ctx, i); 1184 1185 if (pool->base.mis[j] == NULL) { 1186 BREAK_TO_DEBUGGER(); 1187 dm_error( 1188 "DC: failed to create memory input!\n"); 1189 goto controller_create_fail; 1190 } 1191 1192 pool->base.ipps[j] = dce120_ipp_create(ctx, i); 1193 if (pool->base.ipps[i] == NULL) { 1194 BREAK_TO_DEBUGGER(); 1195 dm_error( 1196 "DC: failed to create input pixel processor!\n"); 1197 goto controller_create_fail; 1198 } 1199 1200 pool->base.transforms[j] = dce120_transform_create(ctx, i); 1201 if (pool->base.transforms[i] == NULL) { 1202 BREAK_TO_DEBUGGER(); 1203 dm_error( 1204 "DC: failed to create transform!\n"); 1205 goto res_create_fail; 1206 } 1207 1208 pool->base.opps[j] = dce120_opp_create( 1209 ctx, 1210 i); 1211 if (pool->base.opps[j] == NULL) { 1212 BREAK_TO_DEBUGGER(); 1213 dm_error( 1214 "DC: failed to create output pixel processor!\n"); 1215 } 1216 1217 /* check next valid pipe */ 1218 j++; 1219 } 1220 1221 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1222 pool->base.engines[i] = dce120_aux_engine_create(ctx, i); 1223 if (pool->base.engines[i] == NULL) { 1224 BREAK_TO_DEBUGGER(); 1225 dm_error( 1226 "DC:failed to create aux engine!!\n"); 1227 goto res_create_fail; 1228 } 1229 pool->base.hw_i2cs[i] = dce120_i2c_hw_create(ctx, i); 1230 if (pool->base.hw_i2cs[i] == NULL) { 1231 BREAK_TO_DEBUGGER(); 1232 dm_error( 1233 "DC:failed to create i2c engine!!\n"); 1234 goto res_create_fail; 1235 } 1236 pool->base.sw_i2cs[i] = NULL; 1237 } 1238 1239 /* valid pipe num */ 1240 pool->base.pipe_count = j; 1241 pool->base.timing_generator_count = j; 1242 1243 if (is_vg20) 1244 res_funcs = &dce121_res_create_funcs; 1245 else 1246 res_funcs = &res_create_funcs; 1247 1248 if (!resource_construct(num_virtual_links, dc, &pool->base, res_funcs)) 1249 goto res_create_fail; 1250 1251 /* Create hardware sequencer */ 1252 if (!dce120_hw_sequencer_create(dc)) 1253 goto controller_create_fail; 1254 1255 dc->caps.max_planes = pool->base.pipe_count; 1256 1257 for (i = 0; i < dc->caps.max_planes; ++i) 1258 dc->caps.planes[i] = plane_cap; 1259 1260 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1261 1262 bw_calcs_data_update_from_pplib(dc); 1263 1264 return true; 1265 1266 irqs_create_fail: 1267 controller_create_fail: 1268 clk_src_create_fail: 1269 res_create_fail: 1270 1271 dce120_resource_destruct(pool); 1272 1273 return false; 1274 } 1275 1276 struct resource_pool *dce120_create_resource_pool( 1277 uint8_t num_virtual_links, 1278 struct dc *dc) 1279 { 1280 struct dce110_resource_pool *pool = 1281 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1282 1283 if (!pool) 1284 return NULL; 1285 1286 if (dce120_resource_construct(num_virtual_links, dc, pool)) 1287 return &pool->base; 1288 1289 kfree(pool); 1290 BREAK_TO_DEBUGGER(); 1291 return NULL; 1292 } 1293