1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc.cls 3 * 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 29 30 #include "stream_encoder.h" 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dce120_resource.h" 34 #include "dce112/dce112_resource.h" 35 36 #include "dce110/dce110_resource.h" 37 #include "../virtual/virtual_stream_encoder.h" 38 #include "dce120_timing_generator.h" 39 #include "irq/dce120/irq_service_dce120.h" 40 #include "dce/dce_opp.h" 41 #include "dce/dce_clock_source.h" 42 #include "dce/dce_clocks.h" 43 #include "dce/dce_ipp.h" 44 #include "dce/dce_mem_input.h" 45 46 #include "dce110/dce110_hw_sequencer.h" 47 #include "dce120/dce120_hw_sequencer.h" 48 #include "dce/dce_transform.h" 49 50 #include "dce/dce_audio.h" 51 #include "dce/dce_link_encoder.h" 52 #include "dce/dce_stream_encoder.h" 53 #include "dce/dce_hwseq.h" 54 #include "dce/dce_abm.h" 55 #include "dce/dce_dmcu.h" 56 57 #include "vega10/DC/dce_12_0_offset.h" 58 #include "vega10/DC/dce_12_0_sh_mask.h" 59 #include "vega10/soc15ip.h" 60 #include "vega10/NBIO/nbio_6_1_offset.h" 61 #include "reg_helper.h" 62 63 #include "dce100/dce100_resource.h" 64 65 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 66 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 67 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 68 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 69 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 70 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 71 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 72 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 73 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 74 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 75 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 76 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 77 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 78 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 79 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 80 #endif 81 82 enum dce120_clk_src_array_id { 83 DCE120_CLK_SRC_PLL0, 84 DCE120_CLK_SRC_PLL1, 85 DCE120_CLK_SRC_PLL2, 86 DCE120_CLK_SRC_PLL3, 87 DCE120_CLK_SRC_PLL4, 88 DCE120_CLK_SRC_PLL5, 89 90 DCE120_CLK_SRC_TOTAL 91 }; 92 93 static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = { 94 { 95 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 96 }, 97 { 98 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 99 }, 100 { 101 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 102 }, 103 { 104 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 105 }, 106 { 107 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 108 }, 109 { 110 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 111 } 112 }; 113 114 /* begin ********************* 115 * macros to expend register list macro defined in HW object header file */ 116 117 #define BASE_INNER(seg) \ 118 DCE_BASE__INST0_SEG ## seg 119 120 #define NBIO_BASE_INNER(seg) \ 121 NBIF_BASE__INST0_SEG ## seg 122 123 #define NBIO_BASE(seg) \ 124 NBIO_BASE_INNER(seg) 125 126 /* compile time expand base address. */ 127 #define BASE(seg) \ 128 BASE_INNER(seg) 129 130 #define SR(reg_name)\ 131 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 132 mm ## reg_name 133 134 #define SRI(reg_name, block, id)\ 135 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 136 mm ## block ## id ## _ ## reg_name 137 138 /* macros to expend register list macro defined in HW object header file 139 * end *********************/ 140 141 142 static const struct dce_dmcu_registers dmcu_regs = { 143 DMCU_DCE110_COMMON_REG_LIST() 144 }; 145 146 static const struct dce_dmcu_shift dmcu_shift = { 147 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 148 }; 149 150 static const struct dce_dmcu_mask dmcu_mask = { 151 DMCU_MASK_SH_LIST_DCE110(_MASK) 152 }; 153 154 static const struct dce_abm_registers abm_regs = { 155 ABM_DCE110_COMMON_REG_LIST() 156 }; 157 158 static const struct dce_abm_shift abm_shift = { 159 ABM_MASK_SH_LIST_DCE110(__SHIFT) 160 }; 161 162 static const struct dce_abm_mask abm_mask = { 163 ABM_MASK_SH_LIST_DCE110(_MASK) 164 }; 165 166 #define ipp_regs(id)\ 167 [id] = {\ 168 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 169 } 170 171 static const struct dce_ipp_registers ipp_regs[] = { 172 ipp_regs(0), 173 ipp_regs(1), 174 ipp_regs(2), 175 ipp_regs(3), 176 ipp_regs(4), 177 ipp_regs(5) 178 }; 179 180 static const struct dce_ipp_shift ipp_shift = { 181 IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT) 182 }; 183 184 static const struct dce_ipp_mask ipp_mask = { 185 IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK) 186 }; 187 188 #define transform_regs(id)\ 189 [id] = {\ 190 XFM_COMMON_REG_LIST_DCE110(id)\ 191 } 192 193 static const struct dce_transform_registers xfm_regs[] = { 194 transform_regs(0), 195 transform_regs(1), 196 transform_regs(2), 197 transform_regs(3), 198 transform_regs(4), 199 transform_regs(5) 200 }; 201 202 static const struct dce_transform_shift xfm_shift = { 203 XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT) 204 }; 205 206 static const struct dce_transform_mask xfm_mask = { 207 XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK) 208 }; 209 210 #define aux_regs(id)\ 211 [id] = {\ 212 AUX_REG_LIST(id)\ 213 } 214 215 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 216 aux_regs(0), 217 aux_regs(1), 218 aux_regs(2), 219 aux_regs(3), 220 aux_regs(4), 221 aux_regs(5) 222 }; 223 224 #define hpd_regs(id)\ 225 [id] = {\ 226 HPD_REG_LIST(id)\ 227 } 228 229 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 230 hpd_regs(0), 231 hpd_regs(1), 232 hpd_regs(2), 233 hpd_regs(3), 234 hpd_regs(4), 235 hpd_regs(5) 236 }; 237 238 #define link_regs(id)\ 239 [id] = {\ 240 LE_DCE120_REG_LIST(id), \ 241 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 242 } 243 244 static const struct dce110_link_enc_registers link_enc_regs[] = { 245 link_regs(0), 246 link_regs(1), 247 link_regs(2), 248 link_regs(3), 249 link_regs(4), 250 link_regs(5), 251 link_regs(6), 252 }; 253 254 255 #define stream_enc_regs(id)\ 256 [id] = {\ 257 SE_COMMON_REG_LIST(id),\ 258 .TMDS_CNTL = 0,\ 259 } 260 261 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 262 stream_enc_regs(0), 263 stream_enc_regs(1), 264 stream_enc_regs(2), 265 stream_enc_regs(3), 266 stream_enc_regs(4), 267 stream_enc_regs(5) 268 }; 269 270 static const struct dce_stream_encoder_shift se_shift = { 271 SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT) 272 }; 273 274 static const struct dce_stream_encoder_mask se_mask = { 275 SE_COMMON_MASK_SH_LIST_DCE120(_MASK) 276 }; 277 278 #define opp_regs(id)\ 279 [id] = {\ 280 OPP_DCE_120_REG_LIST(id),\ 281 } 282 283 static const struct dce_opp_registers opp_regs[] = { 284 opp_regs(0), 285 opp_regs(1), 286 opp_regs(2), 287 opp_regs(3), 288 opp_regs(4), 289 opp_regs(5) 290 }; 291 292 static const struct dce_opp_shift opp_shift = { 293 OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT) 294 }; 295 296 static const struct dce_opp_mask opp_mask = { 297 OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK) 298 }; 299 300 #define audio_regs(id)\ 301 [id] = {\ 302 AUD_COMMON_REG_LIST(id)\ 303 } 304 305 static const struct dce_audio_registers audio_regs[] = { 306 audio_regs(0), 307 audio_regs(1), 308 audio_regs(2), 309 audio_regs(3), 310 audio_regs(4), 311 audio_regs(5) 312 }; 313 314 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 315 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 316 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 317 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 318 319 static const struct dce_audio_shift audio_shift = { 320 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 321 }; 322 323 static const struct dce_aduio_mask audio_mask = { 324 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 325 }; 326 327 #define clk_src_regs(index, id)\ 328 [index] = {\ 329 CS_COMMON_REG_LIST_DCE_112(id),\ 330 } 331 332 static const struct dce110_clk_src_regs clk_src_regs[] = { 333 clk_src_regs(0, A), 334 clk_src_regs(1, B), 335 clk_src_regs(2, C), 336 clk_src_regs(3, D), 337 clk_src_regs(4, E), 338 clk_src_regs(5, F) 339 }; 340 341 static const struct dce110_clk_src_shift cs_shift = { 342 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 343 }; 344 345 static const struct dce110_clk_src_mask cs_mask = { 346 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) 347 }; 348 349 struct output_pixel_processor *dce120_opp_create( 350 struct dc_context *ctx, 351 uint32_t inst) 352 { 353 struct dce110_opp *opp = 354 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 355 356 if (!opp) 357 return NULL; 358 359 dce110_opp_construct(opp, 360 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 361 return &opp->base; 362 } 363 364 static const struct bios_registers bios_regs = { 365 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX) 366 }; 367 368 static const struct resource_caps res_cap = { 369 .num_timing_generator = 6, 370 .num_audio = 7, 371 .num_stream_encoder = 6, 372 .num_pll = 6, 373 }; 374 375 static const struct dc_debug debug_defaults = { 376 .disable_clock_gate = true, 377 }; 378 379 struct clock_source *dce120_clock_source_create( 380 struct dc_context *ctx, 381 struct dc_bios *bios, 382 enum clock_source_id id, 383 const struct dce110_clk_src_regs *regs, 384 bool dp_clk_src) 385 { 386 struct dce110_clk_src *clk_src = 387 kzalloc(sizeof(*clk_src), GFP_KERNEL); 388 389 if (!clk_src) 390 return NULL; 391 392 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 393 regs, &cs_shift, &cs_mask)) { 394 clk_src->base.dp_clk_src = dp_clk_src; 395 return &clk_src->base; 396 } 397 398 BREAK_TO_DEBUGGER(); 399 return NULL; 400 } 401 402 void dce120_clock_source_destroy(struct clock_source **clk_src) 403 { 404 kfree(TO_DCE110_CLK_SRC(*clk_src)); 405 *clk_src = NULL; 406 } 407 408 409 bool dce120_hw_sequencer_create(struct dc *dc) 410 { 411 /* All registers used by dce11.2 match those in dce11 in offset and 412 * structure 413 */ 414 dce120_hw_sequencer_construct(dc); 415 416 /*TODO Move to separate file and Override what is needed */ 417 418 return true; 419 } 420 421 static struct timing_generator *dce120_timing_generator_create( 422 struct dc_context *ctx, 423 uint32_t instance, 424 const struct dce110_timing_generator_offsets *offsets) 425 { 426 struct dce110_timing_generator *tg110 = 427 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 428 429 if (!tg110) 430 return NULL; 431 432 dce120_timing_generator_construct(tg110, ctx, instance, offsets); 433 return &tg110->base; 434 } 435 436 static void dce120_transform_destroy(struct transform **xfm) 437 { 438 kfree(TO_DCE_TRANSFORM(*xfm)); 439 *xfm = NULL; 440 } 441 442 static void destruct(struct dce110_resource_pool *pool) 443 { 444 unsigned int i; 445 446 for (i = 0; i < pool->base.pipe_count; i++) { 447 if (pool->base.opps[i] != NULL) 448 dce110_opp_destroy(&pool->base.opps[i]); 449 450 if (pool->base.transforms[i] != NULL) 451 dce120_transform_destroy(&pool->base.transforms[i]); 452 453 if (pool->base.ipps[i] != NULL) 454 dce_ipp_destroy(&pool->base.ipps[i]); 455 456 if (pool->base.mis[i] != NULL) { 457 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 458 pool->base.mis[i] = NULL; 459 } 460 461 if (pool->base.irqs != NULL) { 462 dal_irq_service_destroy(&pool->base.irqs); 463 } 464 465 if (pool->base.timing_generators[i] != NULL) { 466 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 467 pool->base.timing_generators[i] = NULL; 468 } 469 } 470 471 for (i = 0; i < pool->base.audio_count; i++) { 472 if (pool->base.audios[i]) 473 dce_aud_destroy(&pool->base.audios[i]); 474 } 475 476 for (i = 0; i < pool->base.stream_enc_count; i++) { 477 if (pool->base.stream_enc[i] != NULL) 478 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 479 } 480 481 for (i = 0; i < pool->base.clk_src_count; i++) { 482 if (pool->base.clock_sources[i] != NULL) 483 dce120_clock_source_destroy( 484 &pool->base.clock_sources[i]); 485 } 486 487 if (pool->base.dp_clock_source != NULL) 488 dce120_clock_source_destroy(&pool->base.dp_clock_source); 489 490 if (pool->base.abm != NULL) 491 dce_abm_destroy(&pool->base.abm); 492 493 if (pool->base.dmcu != NULL) 494 dce_dmcu_destroy(&pool->base.dmcu); 495 496 if (pool->base.display_clock != NULL) 497 dce_disp_clk_destroy(&pool->base.display_clock); 498 } 499 500 static void read_dce_straps( 501 struct dc_context *ctx, 502 struct resource_straps *straps) 503 { 504 uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0); 505 506 straps->audio_stream_number = get_reg_field_value(reg_val, 507 CC_DC_MISC_STRAPS, 508 AUDIO_STREAM_NUMBER); 509 straps->hdmi_disable = get_reg_field_value(reg_val, 510 CC_DC_MISC_STRAPS, 511 HDMI_DISABLE); 512 513 reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0); 514 straps->dc_pinstraps_audio = get_reg_field_value(reg_val, 515 DC_PINSTRAPS, 516 DC_PINSTRAPS_AUDIO); 517 } 518 519 static struct audio *create_audio( 520 struct dc_context *ctx, unsigned int inst) 521 { 522 return dce_audio_create(ctx, inst, 523 &audio_regs[inst], &audio_shift, &audio_mask); 524 } 525 526 static const struct encoder_feature_support link_enc_feature = { 527 .max_hdmi_deep_color = COLOR_DEPTH_121212, 528 .max_hdmi_pixel_clock = 600000, 529 .ycbcr420_supported = true, 530 .flags.bits.IS_HBR2_CAPABLE = true, 531 .flags.bits.IS_HBR3_CAPABLE = true, 532 .flags.bits.IS_TPS3_CAPABLE = true, 533 .flags.bits.IS_TPS4_CAPABLE = true, 534 .flags.bits.IS_YCBCR_CAPABLE = true 535 }; 536 537 static struct link_encoder *dce120_link_encoder_create( 538 const struct encoder_init_data *enc_init_data) 539 { 540 struct dce110_link_encoder *enc110 = 541 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 542 543 if (!enc110) 544 return NULL; 545 546 dce110_link_encoder_construct(enc110, 547 enc_init_data, 548 &link_enc_feature, 549 &link_enc_regs[enc_init_data->transmitter], 550 &link_enc_aux_regs[enc_init_data->channel - 1], 551 &link_enc_hpd_regs[enc_init_data->hpd_source]); 552 553 return &enc110->base; 554 } 555 556 static struct input_pixel_processor *dce120_ipp_create( 557 struct dc_context *ctx, uint32_t inst) 558 { 559 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 560 561 if (!ipp) { 562 BREAK_TO_DEBUGGER(); 563 return NULL; 564 } 565 566 dce_ipp_construct(ipp, ctx, inst, 567 &ipp_regs[inst], &ipp_shift, &ipp_mask); 568 return &ipp->base; 569 } 570 571 static struct stream_encoder *dce120_stream_encoder_create( 572 enum engine_id eng_id, 573 struct dc_context *ctx) 574 { 575 struct dce110_stream_encoder *enc110 = 576 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 577 578 if (!enc110) 579 return NULL; 580 581 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 582 &stream_enc_regs[eng_id], 583 &se_shift, &se_mask); 584 return &enc110->base; 585 } 586 587 #define SRII(reg_name, block, id)\ 588 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 589 mm ## block ## id ## _ ## reg_name 590 591 static const struct dce_hwseq_registers hwseq_reg = { 592 HWSEQ_DCE120_REG_LIST() 593 }; 594 595 static const struct dce_hwseq_shift hwseq_shift = { 596 HWSEQ_DCE12_MASK_SH_LIST(__SHIFT) 597 }; 598 599 static const struct dce_hwseq_mask hwseq_mask = { 600 HWSEQ_DCE12_MASK_SH_LIST(_MASK) 601 }; 602 603 static struct dce_hwseq *dce120_hwseq_create( 604 struct dc_context *ctx) 605 { 606 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 607 608 if (hws) { 609 hws->ctx = ctx; 610 hws->regs = &hwseq_reg; 611 hws->shifts = &hwseq_shift; 612 hws->masks = &hwseq_mask; 613 } 614 return hws; 615 } 616 617 static const struct resource_create_funcs res_create_funcs = { 618 .read_dce_straps = read_dce_straps, 619 .create_audio = create_audio, 620 .create_stream_encoder = dce120_stream_encoder_create, 621 .create_hwseq = dce120_hwseq_create, 622 }; 623 624 #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) } 625 static const struct dce_mem_input_registers mi_regs[] = { 626 mi_inst_regs(0), 627 mi_inst_regs(1), 628 mi_inst_regs(2), 629 mi_inst_regs(3), 630 mi_inst_regs(4), 631 mi_inst_regs(5), 632 }; 633 634 static const struct dce_mem_input_shift mi_shifts = { 635 MI_DCE12_MASK_SH_LIST(__SHIFT) 636 }; 637 638 static const struct dce_mem_input_mask mi_masks = { 639 MI_DCE12_MASK_SH_LIST(_MASK) 640 }; 641 642 static struct mem_input *dce120_mem_input_create( 643 struct dc_context *ctx, 644 uint32_t inst) 645 { 646 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 647 GFP_KERNEL); 648 649 if (!dce_mi) { 650 BREAK_TO_DEBUGGER(); 651 return NULL; 652 } 653 654 dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 655 return &dce_mi->base; 656 } 657 658 static struct transform *dce120_transform_create( 659 struct dc_context *ctx, 660 uint32_t inst) 661 { 662 struct dce_transform *transform = 663 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 664 665 if (!transform) 666 return NULL; 667 668 dce_transform_construct(transform, ctx, inst, 669 &xfm_regs[inst], &xfm_shift, &xfm_mask); 670 transform->lb_memory_size = 0x1404; /*5124*/ 671 return &transform->base; 672 } 673 674 static void dce120_destroy_resource_pool(struct resource_pool **pool) 675 { 676 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 677 678 destruct(dce110_pool); 679 kfree(dce110_pool); 680 *pool = NULL; 681 } 682 683 static const struct resource_funcs dce120_res_pool_funcs = { 684 .destroy = dce120_destroy_resource_pool, 685 .link_enc_create = dce120_link_encoder_create, 686 .validate_guaranteed = dce112_validate_guaranteed, 687 .validate_bandwidth = dce112_validate_bandwidth, 688 .validate_plane = dce100_validate_plane, 689 .add_stream_to_ctx = dce112_add_stream_to_ctx 690 }; 691 692 static void bw_calcs_data_update_from_pplib(struct dc *dc) 693 { 694 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 695 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 696 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; 697 int i; 698 unsigned int clk; 699 unsigned int latency; 700 701 /*do system clock*/ 702 if (!dm_pp_get_clock_levels_by_type_with_latency( 703 dc->ctx, 704 DM_PP_CLOCK_TYPE_ENGINE_CLK, 705 &eng_clks) || eng_clks.num_levels == 0) { 706 707 eng_clks.num_levels = 8; 708 clk = 300000; 709 710 for (i = 0; i < eng_clks.num_levels; i++) { 711 eng_clks.data[i].clocks_in_khz = clk; 712 clk += 100000; 713 } 714 } 715 716 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ 717 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 718 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); 719 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 720 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); 721 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 722 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); 723 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 724 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); 725 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 726 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); 727 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 728 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); 729 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 730 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); 731 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 732 eng_clks.data[0].clocks_in_khz, 1000); 733 734 /*do memory clock*/ 735 if (!dm_pp_get_clock_levels_by_type_with_latency( 736 dc->ctx, 737 DM_PP_CLOCK_TYPE_MEMORY_CLK, 738 &mem_clks) || mem_clks.num_levels == 0) { 739 740 mem_clks.num_levels = 3; 741 clk = 250000; 742 latency = 45; 743 744 for (i = 0; i < eng_clks.num_levels; i++) { 745 mem_clks.data[i].clocks_in_khz = clk; 746 mem_clks.data[i].latency_in_us = latency; 747 clk += 500000; 748 latency -= 5; 749 } 750 751 } 752 753 /* we don't need to call PPLIB for validation clock since they 754 * also give us the highest sclk and highest mclk (UMA clock). 755 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): 756 * YCLK = UMACLK*m_memoryTypeMultiplier 757 */ 758 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 759 mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000); 760 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 761 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 762 1000); 763 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 764 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 765 1000); 766 767 /* Now notify PPLib/SMU about which Watermarks sets they should select 768 * depending on DPM state they are in. And update BW MGR GFX Engine and 769 * Memory clock member variables for Watermarks calculations for each 770 * Watermark Set 771 */ 772 clk_ranges.num_wm_sets = 4; 773 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; 774 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = 775 eng_clks.data[0].clocks_in_khz; 776 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = 777 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 778 clk_ranges.wm_clk_ranges[0].wm_min_memg_clk_in_khz = 779 mem_clks.data[0].clocks_in_khz; 780 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = 781 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 782 783 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; 784 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = 785 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 786 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 787 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; 788 clk_ranges.wm_clk_ranges[1].wm_min_memg_clk_in_khz = 789 mem_clks.data[0].clocks_in_khz; 790 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = 791 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 792 793 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; 794 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = 795 eng_clks.data[0].clocks_in_khz; 796 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = 797 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 798 clk_ranges.wm_clk_ranges[2].wm_min_memg_clk_in_khz = 799 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 800 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 801 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; 802 803 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; 804 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = 805 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 806 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 807 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; 808 clk_ranges.wm_clk_ranges[3].wm_min_memg_clk_in_khz = 809 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 810 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 811 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; 812 813 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 814 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); 815 } 816 817 static bool construct( 818 uint8_t num_virtual_links, 819 struct dc *dc, 820 struct dce110_resource_pool *pool) 821 { 822 unsigned int i; 823 struct dc_context *ctx = dc->ctx; 824 struct irq_service_init_data irq_init_data; 825 826 ctx->dc_bios->regs = &bios_regs; 827 828 pool->base.res_cap = &res_cap; 829 pool->base.funcs = &dce120_res_pool_funcs; 830 831 /* TODO: Fill more data from GreenlandAsicCapability.cpp */ 832 pool->base.pipe_count = res_cap.num_timing_generator; 833 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 834 835 dc->caps.max_downscale_ratio = 200; 836 dc->caps.i2c_speed_in_khz = 100; 837 dc->caps.max_cursor_size = 128; 838 dc->debug = debug_defaults; 839 840 /************************************************* 841 * Create resources * 842 *************************************************/ 843 844 pool->base.clock_sources[DCE120_CLK_SRC_PLL0] = 845 dce120_clock_source_create(ctx, ctx->dc_bios, 846 CLOCK_SOURCE_COMBO_PHY_PLL0, 847 &clk_src_regs[0], false); 848 pool->base.clock_sources[DCE120_CLK_SRC_PLL1] = 849 dce120_clock_source_create(ctx, ctx->dc_bios, 850 CLOCK_SOURCE_COMBO_PHY_PLL1, 851 &clk_src_regs[1], false); 852 pool->base.clock_sources[DCE120_CLK_SRC_PLL2] = 853 dce120_clock_source_create(ctx, ctx->dc_bios, 854 CLOCK_SOURCE_COMBO_PHY_PLL2, 855 &clk_src_regs[2], false); 856 pool->base.clock_sources[DCE120_CLK_SRC_PLL3] = 857 dce120_clock_source_create(ctx, ctx->dc_bios, 858 CLOCK_SOURCE_COMBO_PHY_PLL3, 859 &clk_src_regs[3], false); 860 pool->base.clock_sources[DCE120_CLK_SRC_PLL4] = 861 dce120_clock_source_create(ctx, ctx->dc_bios, 862 CLOCK_SOURCE_COMBO_PHY_PLL4, 863 &clk_src_regs[4], false); 864 pool->base.clock_sources[DCE120_CLK_SRC_PLL5] = 865 dce120_clock_source_create(ctx, ctx->dc_bios, 866 CLOCK_SOURCE_COMBO_PHY_PLL5, 867 &clk_src_regs[5], false); 868 pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL; 869 870 pool->base.dp_clock_source = 871 dce120_clock_source_create(ctx, ctx->dc_bios, 872 CLOCK_SOURCE_ID_DP_DTO, 873 &clk_src_regs[0], true); 874 875 for (i = 0; i < pool->base.clk_src_count; i++) { 876 if (pool->base.clock_sources[i] == NULL) { 877 dm_error("DC: failed to create clock sources!\n"); 878 BREAK_TO_DEBUGGER(); 879 goto clk_src_create_fail; 880 } 881 } 882 883 pool->base.display_clock = dce120_disp_clk_create(ctx); 884 if (pool->base.display_clock == NULL) { 885 dm_error("DC: failed to create display clock!\n"); 886 BREAK_TO_DEBUGGER(); 887 goto disp_clk_create_fail; 888 } 889 890 pool->base.dmcu = dce_dmcu_create(ctx, 891 &dmcu_regs, 892 &dmcu_shift, 893 &dmcu_mask); 894 if (pool->base.dmcu == NULL) { 895 dm_error("DC: failed to create dmcu!\n"); 896 BREAK_TO_DEBUGGER(); 897 goto res_create_fail; 898 } 899 900 pool->base.abm = dce_abm_create(ctx, 901 &abm_regs, 902 &abm_shift, 903 &abm_mask); 904 if (pool->base.abm == NULL) { 905 dm_error("DC: failed to create abm!\n"); 906 BREAK_TO_DEBUGGER(); 907 goto res_create_fail; 908 } 909 910 irq_init_data.ctx = dc->ctx; 911 pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data); 912 if (!pool->base.irqs) 913 goto irqs_create_fail; 914 915 for (i = 0; i < pool->base.pipe_count; i++) { 916 pool->base.timing_generators[i] = 917 dce120_timing_generator_create( 918 ctx, 919 i, 920 &dce120_tg_offsets[i]); 921 if (pool->base.timing_generators[i] == NULL) { 922 BREAK_TO_DEBUGGER(); 923 dm_error("DC: failed to create tg!\n"); 924 goto controller_create_fail; 925 } 926 927 pool->base.mis[i] = dce120_mem_input_create(ctx, i); 928 929 if (pool->base.mis[i] == NULL) { 930 BREAK_TO_DEBUGGER(); 931 dm_error( 932 "DC: failed to create memory input!\n"); 933 goto controller_create_fail; 934 } 935 936 pool->base.ipps[i] = dce120_ipp_create(ctx, i); 937 if (pool->base.ipps[i] == NULL) { 938 BREAK_TO_DEBUGGER(); 939 dm_error( 940 "DC: failed to create input pixel processor!\n"); 941 goto controller_create_fail; 942 } 943 944 pool->base.transforms[i] = dce120_transform_create(ctx, i); 945 if (pool->base.transforms[i] == NULL) { 946 BREAK_TO_DEBUGGER(); 947 dm_error( 948 "DC: failed to create transform!\n"); 949 goto res_create_fail; 950 } 951 952 pool->base.opps[i] = dce120_opp_create( 953 ctx, 954 i); 955 if (pool->base.opps[i] == NULL) { 956 BREAK_TO_DEBUGGER(); 957 dm_error( 958 "DC: failed to create output pixel processor!\n"); 959 } 960 } 961 962 if (!resource_construct(num_virtual_links, dc, &pool->base, 963 &res_create_funcs)) 964 goto res_create_fail; 965 966 /* Create hardware sequencer */ 967 if (!dce120_hw_sequencer_create(dc)) 968 goto controller_create_fail; 969 970 dc->caps.max_planes = pool->base.pipe_count; 971 972 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 973 974 bw_calcs_data_update_from_pplib(dc); 975 976 return true; 977 978 irqs_create_fail: 979 controller_create_fail: 980 disp_clk_create_fail: 981 clk_src_create_fail: 982 res_create_fail: 983 984 destruct(pool); 985 986 return false; 987 } 988 989 struct resource_pool *dce120_create_resource_pool( 990 uint8_t num_virtual_links, 991 struct dc *dc) 992 { 993 struct dce110_resource_pool *pool = 994 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 995 996 if (!pool) 997 return NULL; 998 999 if (construct(num_virtual_links, dc, pool)) 1000 return &pool->base; 1001 1002 BREAK_TO_DEBUGGER(); 1003 return NULL; 1004 } 1005