1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc.cls 3 * 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 29 30 #include "stream_encoder.h" 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dce120_resource.h" 34 35 #include "dce112/dce112_resource.h" 36 37 #include "dce110/dce110_resource.h" 38 #include "../virtual/virtual_stream_encoder.h" 39 #include "dce120_timing_generator.h" 40 #include "irq/dce120/irq_service_dce120.h" 41 #include "dce/dce_opp.h" 42 #include "dce/dce_clock_source.h" 43 #include "dce/dce_ipp.h" 44 #include "dce/dce_mem_input.h" 45 #include "dce/dce_panel_cntl.h" 46 47 #include "dce110/dce110_hw_sequencer.h" 48 #include "dce120/dce120_hw_sequencer.h" 49 #include "dce/dce_transform.h" 50 #include "clk_mgr.h" 51 #include "dce/dce_audio.h" 52 #include "dce/dce_link_encoder.h" 53 #include "dce/dce_stream_encoder.h" 54 #include "dce/dce_hwseq.h" 55 #include "dce/dce_abm.h" 56 #include "dce/dce_dmcu.h" 57 #include "dce/dce_aux.h" 58 #include "dce/dce_i2c.h" 59 60 #include "dce/dce_12_0_offset.h" 61 #include "dce/dce_12_0_sh_mask.h" 62 #include "soc15_hw_ip.h" 63 #include "vega10_ip_offset.h" 64 #include "nbio/nbio_6_1_offset.h" 65 #include "mmhub/mmhub_1_0_offset.h" 66 #include "mmhub/mmhub_1_0_sh_mask.h" 67 #include "reg_helper.h" 68 69 #include "dce100/dce100_resource.h" 70 71 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 72 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 73 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 74 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 75 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 76 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 77 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 78 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 79 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 80 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 81 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 82 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 83 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 84 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 85 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 86 #endif 87 88 enum dce120_clk_src_array_id { 89 DCE120_CLK_SRC_PLL0, 90 DCE120_CLK_SRC_PLL1, 91 DCE120_CLK_SRC_PLL2, 92 DCE120_CLK_SRC_PLL3, 93 DCE120_CLK_SRC_PLL4, 94 DCE120_CLK_SRC_PLL5, 95 96 DCE120_CLK_SRC_TOTAL 97 }; 98 99 static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = { 100 { 101 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 102 }, 103 { 104 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 105 }, 106 { 107 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 108 }, 109 { 110 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 111 }, 112 { 113 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 114 }, 115 { 116 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 117 } 118 }; 119 120 /* begin ********************* 121 * macros to expend register list macro defined in HW object header file */ 122 123 #define BASE_INNER(seg) \ 124 DCE_BASE__INST0_SEG ## seg 125 126 #define NBIO_BASE_INNER(seg) \ 127 NBIF_BASE__INST0_SEG ## seg 128 129 #define NBIO_BASE(seg) \ 130 NBIO_BASE_INNER(seg) 131 132 /* compile time expand base address. */ 133 #define BASE(seg) \ 134 BASE_INNER(seg) 135 136 #define SR(reg_name)\ 137 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 138 mm ## reg_name 139 140 #define SRI(reg_name, block, id)\ 141 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 142 mm ## block ## id ## _ ## reg_name 143 144 /* MMHUB */ 145 #define MMHUB_BASE_INNER(seg) \ 146 MMHUB_BASE__INST0_SEG ## seg 147 148 #define MMHUB_BASE(seg) \ 149 MMHUB_BASE_INNER(seg) 150 151 #define MMHUB_SR(reg_name)\ 152 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 153 mm ## reg_name 154 155 /* macros to expend register list macro defined in HW object header file 156 * end *********************/ 157 158 159 static const struct dce_dmcu_registers dmcu_regs = { 160 DMCU_DCE110_COMMON_REG_LIST() 161 }; 162 163 static const struct dce_dmcu_shift dmcu_shift = { 164 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 165 }; 166 167 static const struct dce_dmcu_mask dmcu_mask = { 168 DMCU_MASK_SH_LIST_DCE110(_MASK) 169 }; 170 171 static const struct dce_abm_registers abm_regs = { 172 ABM_DCE110_COMMON_REG_LIST() 173 }; 174 175 static const struct dce_abm_shift abm_shift = { 176 ABM_MASK_SH_LIST_DCE110(__SHIFT) 177 }; 178 179 static const struct dce_abm_mask abm_mask = { 180 ABM_MASK_SH_LIST_DCE110(_MASK) 181 }; 182 183 #define ipp_regs(id)\ 184 [id] = {\ 185 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 186 } 187 188 static const struct dce_ipp_registers ipp_regs[] = { 189 ipp_regs(0), 190 ipp_regs(1), 191 ipp_regs(2), 192 ipp_regs(3), 193 ipp_regs(4), 194 ipp_regs(5) 195 }; 196 197 static const struct dce_ipp_shift ipp_shift = { 198 IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT) 199 }; 200 201 static const struct dce_ipp_mask ipp_mask = { 202 IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK) 203 }; 204 205 #define transform_regs(id)\ 206 [id] = {\ 207 XFM_COMMON_REG_LIST_DCE110(id)\ 208 } 209 210 static const struct dce_transform_registers xfm_regs[] = { 211 transform_regs(0), 212 transform_regs(1), 213 transform_regs(2), 214 transform_regs(3), 215 transform_regs(4), 216 transform_regs(5) 217 }; 218 219 static const struct dce_transform_shift xfm_shift = { 220 XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT) 221 }; 222 223 static const struct dce_transform_mask xfm_mask = { 224 XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK) 225 }; 226 227 #define aux_regs(id)\ 228 [id] = {\ 229 AUX_REG_LIST(id)\ 230 } 231 232 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 233 aux_regs(0), 234 aux_regs(1), 235 aux_regs(2), 236 aux_regs(3), 237 aux_regs(4), 238 aux_regs(5) 239 }; 240 241 #define hpd_regs(id)\ 242 [id] = {\ 243 HPD_REG_LIST(id)\ 244 } 245 246 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 247 hpd_regs(0), 248 hpd_regs(1), 249 hpd_regs(2), 250 hpd_regs(3), 251 hpd_regs(4), 252 hpd_regs(5) 253 }; 254 255 #define link_regs(id)\ 256 [id] = {\ 257 LE_DCE120_REG_LIST(id), \ 258 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 259 } 260 261 static const struct dce110_link_enc_registers link_enc_regs[] = { 262 link_regs(0), 263 link_regs(1), 264 link_regs(2), 265 link_regs(3), 266 link_regs(4), 267 link_regs(5), 268 link_regs(6), 269 }; 270 271 272 #define stream_enc_regs(id)\ 273 [id] = {\ 274 SE_COMMON_REG_LIST(id),\ 275 .TMDS_CNTL = 0,\ 276 } 277 278 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 279 stream_enc_regs(0), 280 stream_enc_regs(1), 281 stream_enc_regs(2), 282 stream_enc_regs(3), 283 stream_enc_regs(4), 284 stream_enc_regs(5) 285 }; 286 287 static const struct dce_stream_encoder_shift se_shift = { 288 SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT) 289 }; 290 291 static const struct dce_stream_encoder_mask se_mask = { 292 SE_COMMON_MASK_SH_LIST_DCE120(_MASK) 293 }; 294 295 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 296 { DCE_PANEL_CNTL_REG_LIST() } 297 }; 298 299 static const struct dce_panel_cntl_shift panel_cntl_shift = { 300 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 301 }; 302 303 static const struct dce_panel_cntl_mask panel_cntl_mask = { 304 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 305 }; 306 307 static const struct dce110_aux_registers_shift aux_shift = { 308 DCE12_AUX_MASK_SH_LIST(__SHIFT) 309 }; 310 311 static const struct dce110_aux_registers_mask aux_mask = { 312 DCE12_AUX_MASK_SH_LIST(_MASK) 313 }; 314 315 #define opp_regs(id)\ 316 [id] = {\ 317 OPP_DCE_120_REG_LIST(id),\ 318 } 319 320 static const struct dce_opp_registers opp_regs[] = { 321 opp_regs(0), 322 opp_regs(1), 323 opp_regs(2), 324 opp_regs(3), 325 opp_regs(4), 326 opp_regs(5) 327 }; 328 329 static const struct dce_opp_shift opp_shift = { 330 OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT) 331 }; 332 333 static const struct dce_opp_mask opp_mask = { 334 OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK) 335 }; 336 #define aux_engine_regs(id)\ 337 [id] = {\ 338 AUX_COMMON_REG_LIST(id), \ 339 .AUX_RESET_MASK = 0 \ 340 } 341 342 static const struct dce110_aux_registers aux_engine_regs[] = { 343 aux_engine_regs(0), 344 aux_engine_regs(1), 345 aux_engine_regs(2), 346 aux_engine_regs(3), 347 aux_engine_regs(4), 348 aux_engine_regs(5) 349 }; 350 351 #define audio_regs(id)\ 352 [id] = {\ 353 AUD_COMMON_REG_LIST(id)\ 354 } 355 356 static const struct dce_audio_registers audio_regs[] = { 357 audio_regs(0), 358 audio_regs(1), 359 audio_regs(2), 360 audio_regs(3), 361 audio_regs(4), 362 audio_regs(5) 363 }; 364 365 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 366 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 367 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 368 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 369 370 static const struct dce_audio_shift audio_shift = { 371 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 372 }; 373 374 static const struct dce_audio_mask audio_mask = { 375 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 376 }; 377 378 static int map_transmitter_id_to_phy_instance( 379 enum transmitter transmitter) 380 { 381 switch (transmitter) { 382 case TRANSMITTER_UNIPHY_A: 383 return 0; 384 case TRANSMITTER_UNIPHY_B: 385 return 1; 386 case TRANSMITTER_UNIPHY_C: 387 return 2; 388 case TRANSMITTER_UNIPHY_D: 389 return 3; 390 case TRANSMITTER_UNIPHY_E: 391 return 4; 392 case TRANSMITTER_UNIPHY_F: 393 return 5; 394 case TRANSMITTER_UNIPHY_G: 395 return 6; 396 default: 397 ASSERT(0); 398 return 0; 399 } 400 } 401 402 #define clk_src_regs(index, id)\ 403 [index] = {\ 404 CS_COMMON_REG_LIST_DCE_112(id),\ 405 } 406 407 static const struct dce110_clk_src_regs clk_src_regs[] = { 408 clk_src_regs(0, A), 409 clk_src_regs(1, B), 410 clk_src_regs(2, C), 411 clk_src_regs(3, D), 412 clk_src_regs(4, E), 413 clk_src_regs(5, F) 414 }; 415 416 static const struct dce110_clk_src_shift cs_shift = { 417 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 418 }; 419 420 static const struct dce110_clk_src_mask cs_mask = { 421 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) 422 }; 423 424 static struct output_pixel_processor *dce120_opp_create( 425 struct dc_context *ctx, 426 uint32_t inst) 427 { 428 struct dce110_opp *opp = 429 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 430 431 if (!opp) 432 return NULL; 433 434 dce110_opp_construct(opp, 435 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 436 return &opp->base; 437 } 438 static struct dce_aux *dce120_aux_engine_create( 439 struct dc_context *ctx, 440 uint32_t inst) 441 { 442 struct aux_engine_dce110 *aux_engine = 443 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 444 445 if (!aux_engine) 446 return NULL; 447 448 dce110_aux_engine_construct(aux_engine, ctx, inst, 449 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 450 &aux_engine_regs[inst], 451 &aux_mask, 452 &aux_shift, 453 ctx->dc->caps.extended_aux_timeout_support); 454 455 return &aux_engine->base; 456 } 457 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 458 459 static const struct dce_i2c_registers i2c_hw_regs[] = { 460 i2c_inst_regs(1), 461 i2c_inst_regs(2), 462 i2c_inst_regs(3), 463 i2c_inst_regs(4), 464 i2c_inst_regs(5), 465 i2c_inst_regs(6), 466 }; 467 468 static const struct dce_i2c_shift i2c_shifts = { 469 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 470 }; 471 472 static const struct dce_i2c_mask i2c_masks = { 473 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 474 }; 475 476 static struct dce_i2c_hw *dce120_i2c_hw_create( 477 struct dc_context *ctx, 478 uint32_t inst) 479 { 480 struct dce_i2c_hw *dce_i2c_hw = 481 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 482 483 if (!dce_i2c_hw) 484 return NULL; 485 486 dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst, 487 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 488 489 return dce_i2c_hw; 490 } 491 static const struct bios_registers bios_regs = { 492 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + NBIO_BASE(mmBIOS_SCRATCH_3_BASE_IDX), 493 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX) 494 }; 495 496 static const struct resource_caps res_cap = { 497 .num_timing_generator = 6, 498 .num_audio = 7, 499 .num_stream_encoder = 6, 500 .num_pll = 6, 501 .num_ddc = 6, 502 }; 503 504 static const struct dc_plane_cap plane_cap = { 505 .type = DC_PLANE_TYPE_DCE_RGB, 506 507 .pixel_format_support = { 508 .argb8888 = true, 509 .nv12 = false, 510 .fp16 = true 511 }, 512 513 .max_upscale_factor = { 514 .argb8888 = 16000, 515 .nv12 = 1, 516 .fp16 = 1 517 }, 518 519 .max_downscale_factor = { 520 .argb8888 = 250, 521 .nv12 = 1, 522 .fp16 = 1 523 } 524 }; 525 526 static const struct dc_debug_options debug_defaults = { 527 .disable_clock_gate = true, 528 }; 529 530 static struct clock_source *dce120_clock_source_create( 531 struct dc_context *ctx, 532 struct dc_bios *bios, 533 enum clock_source_id id, 534 const struct dce110_clk_src_regs *regs, 535 bool dp_clk_src) 536 { 537 struct dce110_clk_src *clk_src = 538 kzalloc(sizeof(*clk_src), GFP_KERNEL); 539 540 if (!clk_src) 541 return NULL; 542 543 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 544 regs, &cs_shift, &cs_mask)) { 545 clk_src->base.dp_clk_src = dp_clk_src; 546 return &clk_src->base; 547 } 548 549 kfree(clk_src); 550 BREAK_TO_DEBUGGER(); 551 return NULL; 552 } 553 554 static void dce120_clock_source_destroy(struct clock_source **clk_src) 555 { 556 kfree(TO_DCE110_CLK_SRC(*clk_src)); 557 *clk_src = NULL; 558 } 559 560 561 static bool dce120_hw_sequencer_create(struct dc *dc) 562 { 563 /* All registers used by dce11.2 match those in dce11 in offset and 564 * structure 565 */ 566 dce120_hw_sequencer_construct(dc); 567 568 /*TODO Move to separate file and Override what is needed */ 569 570 return true; 571 } 572 573 static struct timing_generator *dce120_timing_generator_create( 574 struct dc_context *ctx, 575 uint32_t instance, 576 const struct dce110_timing_generator_offsets *offsets) 577 { 578 struct dce110_timing_generator *tg110 = 579 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 580 581 if (!tg110) 582 return NULL; 583 584 dce120_timing_generator_construct(tg110, ctx, instance, offsets); 585 return &tg110->base; 586 } 587 588 static void dce120_transform_destroy(struct transform **xfm) 589 { 590 kfree(TO_DCE_TRANSFORM(*xfm)); 591 *xfm = NULL; 592 } 593 594 static void dce120_resource_destruct(struct dce110_resource_pool *pool) 595 { 596 unsigned int i; 597 598 for (i = 0; i < pool->base.pipe_count; i++) { 599 if (pool->base.opps[i] != NULL) 600 dce110_opp_destroy(&pool->base.opps[i]); 601 602 if (pool->base.transforms[i] != NULL) 603 dce120_transform_destroy(&pool->base.transforms[i]); 604 605 if (pool->base.ipps[i] != NULL) 606 dce_ipp_destroy(&pool->base.ipps[i]); 607 608 if (pool->base.mis[i] != NULL) { 609 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 610 pool->base.mis[i] = NULL; 611 } 612 613 if (pool->base.irqs != NULL) { 614 dal_irq_service_destroy(&pool->base.irqs); 615 } 616 617 if (pool->base.timing_generators[i] != NULL) { 618 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 619 pool->base.timing_generators[i] = NULL; 620 } 621 } 622 623 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 624 if (pool->base.engines[i] != NULL) 625 dce110_engine_destroy(&pool->base.engines[i]); 626 if (pool->base.hw_i2cs[i] != NULL) { 627 kfree(pool->base.hw_i2cs[i]); 628 pool->base.hw_i2cs[i] = NULL; 629 } 630 if (pool->base.sw_i2cs[i] != NULL) { 631 kfree(pool->base.sw_i2cs[i]); 632 pool->base.sw_i2cs[i] = NULL; 633 } 634 } 635 636 for (i = 0; i < pool->base.audio_count; i++) { 637 if (pool->base.audios[i]) 638 dce_aud_destroy(&pool->base.audios[i]); 639 } 640 641 for (i = 0; i < pool->base.stream_enc_count; i++) { 642 if (pool->base.stream_enc[i] != NULL) 643 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 644 } 645 646 for (i = 0; i < pool->base.clk_src_count; i++) { 647 if (pool->base.clock_sources[i] != NULL) 648 dce120_clock_source_destroy( 649 &pool->base.clock_sources[i]); 650 } 651 652 if (pool->base.dp_clock_source != NULL) 653 dce120_clock_source_destroy(&pool->base.dp_clock_source); 654 655 if (pool->base.abm != NULL) 656 dce_abm_destroy(&pool->base.abm); 657 658 if (pool->base.dmcu != NULL) 659 dce_dmcu_destroy(&pool->base.dmcu); 660 } 661 662 static void read_dce_straps( 663 struct dc_context *ctx, 664 struct resource_straps *straps) 665 { 666 uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0); 667 668 straps->audio_stream_number = get_reg_field_value(reg_val, 669 CC_DC_MISC_STRAPS, 670 AUDIO_STREAM_NUMBER); 671 straps->hdmi_disable = get_reg_field_value(reg_val, 672 CC_DC_MISC_STRAPS, 673 HDMI_DISABLE); 674 675 reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0); 676 straps->dc_pinstraps_audio = get_reg_field_value(reg_val, 677 DC_PINSTRAPS, 678 DC_PINSTRAPS_AUDIO); 679 } 680 681 static struct audio *create_audio( 682 struct dc_context *ctx, unsigned int inst) 683 { 684 return dce_audio_create(ctx, inst, 685 &audio_regs[inst], &audio_shift, &audio_mask); 686 } 687 688 static const struct encoder_feature_support link_enc_feature = { 689 .max_hdmi_deep_color = COLOR_DEPTH_121212, 690 .max_hdmi_pixel_clock = 600000, 691 .hdmi_ycbcr420_supported = true, 692 .dp_ycbcr420_supported = false, 693 .flags.bits.IS_HBR2_CAPABLE = true, 694 .flags.bits.IS_HBR3_CAPABLE = true, 695 .flags.bits.IS_TPS3_CAPABLE = true, 696 .flags.bits.IS_TPS4_CAPABLE = true, 697 }; 698 699 static struct link_encoder *dce120_link_encoder_create( 700 const struct encoder_init_data *enc_init_data) 701 { 702 struct dce110_link_encoder *enc110 = 703 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 704 int link_regs_id; 705 706 if (!enc110) 707 return NULL; 708 709 link_regs_id = 710 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 711 712 dce110_link_encoder_construct(enc110, 713 enc_init_data, 714 &link_enc_feature, 715 &link_enc_regs[link_regs_id], 716 &link_enc_aux_regs[enc_init_data->channel - 1], 717 &link_enc_hpd_regs[enc_init_data->hpd_source]); 718 719 return &enc110->base; 720 } 721 722 static struct panel_cntl *dce120_panel_cntl_create(const struct panel_cntl_init_data *init_data) 723 { 724 struct dce_panel_cntl *panel_cntl = 725 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 726 727 if (!panel_cntl) 728 return NULL; 729 730 dce_panel_cntl_construct(panel_cntl, 731 init_data, 732 &panel_cntl_regs[init_data->inst], 733 &panel_cntl_shift, 734 &panel_cntl_mask); 735 736 return &panel_cntl->base; 737 } 738 739 static struct input_pixel_processor *dce120_ipp_create( 740 struct dc_context *ctx, uint32_t inst) 741 { 742 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 743 744 if (!ipp) { 745 BREAK_TO_DEBUGGER(); 746 return NULL; 747 } 748 749 dce_ipp_construct(ipp, ctx, inst, 750 &ipp_regs[inst], &ipp_shift, &ipp_mask); 751 return &ipp->base; 752 } 753 754 static struct stream_encoder *dce120_stream_encoder_create( 755 enum engine_id eng_id, 756 struct dc_context *ctx) 757 { 758 struct dce110_stream_encoder *enc110 = 759 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 760 761 if (!enc110) 762 return NULL; 763 764 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 765 &stream_enc_regs[eng_id], 766 &se_shift, &se_mask); 767 return &enc110->base; 768 } 769 770 #define SRII(reg_name, block, id)\ 771 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 772 mm ## block ## id ## _ ## reg_name 773 774 static const struct dce_hwseq_registers hwseq_reg = { 775 HWSEQ_DCE120_REG_LIST() 776 }; 777 778 static const struct dce_hwseq_shift hwseq_shift = { 779 HWSEQ_DCE12_MASK_SH_LIST(__SHIFT) 780 }; 781 782 static const struct dce_hwseq_mask hwseq_mask = { 783 HWSEQ_DCE12_MASK_SH_LIST(_MASK) 784 }; 785 786 /* HWSEQ regs for VG20 */ 787 static const struct dce_hwseq_registers dce121_hwseq_reg = { 788 HWSEQ_VG20_REG_LIST() 789 }; 790 791 static const struct dce_hwseq_shift dce121_hwseq_shift = { 792 HWSEQ_VG20_MASK_SH_LIST(__SHIFT) 793 }; 794 795 static const struct dce_hwseq_mask dce121_hwseq_mask = { 796 HWSEQ_VG20_MASK_SH_LIST(_MASK) 797 }; 798 799 static struct dce_hwseq *dce120_hwseq_create( 800 struct dc_context *ctx) 801 { 802 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 803 804 if (hws) { 805 hws->ctx = ctx; 806 hws->regs = &hwseq_reg; 807 hws->shifts = &hwseq_shift; 808 hws->masks = &hwseq_mask; 809 } 810 return hws; 811 } 812 813 static struct dce_hwseq *dce121_hwseq_create( 814 struct dc_context *ctx) 815 { 816 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 817 818 if (hws) { 819 hws->ctx = ctx; 820 hws->regs = &dce121_hwseq_reg; 821 hws->shifts = &dce121_hwseq_shift; 822 hws->masks = &dce121_hwseq_mask; 823 } 824 return hws; 825 } 826 827 static const struct resource_create_funcs res_create_funcs = { 828 .read_dce_straps = read_dce_straps, 829 .create_audio = create_audio, 830 .create_stream_encoder = dce120_stream_encoder_create, 831 .create_hwseq = dce120_hwseq_create, 832 }; 833 834 static const struct resource_create_funcs dce121_res_create_funcs = { 835 .read_dce_straps = read_dce_straps, 836 .create_audio = create_audio, 837 .create_stream_encoder = dce120_stream_encoder_create, 838 .create_hwseq = dce121_hwseq_create, 839 }; 840 841 842 #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) } 843 static const struct dce_mem_input_registers mi_regs[] = { 844 mi_inst_regs(0), 845 mi_inst_regs(1), 846 mi_inst_regs(2), 847 mi_inst_regs(3), 848 mi_inst_regs(4), 849 mi_inst_regs(5), 850 }; 851 852 static const struct dce_mem_input_shift mi_shifts = { 853 MI_DCE12_MASK_SH_LIST(__SHIFT) 854 }; 855 856 static const struct dce_mem_input_mask mi_masks = { 857 MI_DCE12_MASK_SH_LIST(_MASK) 858 }; 859 860 static struct mem_input *dce120_mem_input_create( 861 struct dc_context *ctx, 862 uint32_t inst) 863 { 864 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 865 GFP_KERNEL); 866 867 if (!dce_mi) { 868 BREAK_TO_DEBUGGER(); 869 return NULL; 870 } 871 872 dce120_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 873 return &dce_mi->base; 874 } 875 876 static struct transform *dce120_transform_create( 877 struct dc_context *ctx, 878 uint32_t inst) 879 { 880 struct dce_transform *transform = 881 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 882 883 if (!transform) 884 return NULL; 885 886 dce_transform_construct(transform, ctx, inst, 887 &xfm_regs[inst], &xfm_shift, &xfm_mask); 888 transform->lb_memory_size = 0x1404; /*5124*/ 889 return &transform->base; 890 } 891 892 static void dce120_destroy_resource_pool(struct resource_pool **pool) 893 { 894 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 895 896 dce120_resource_destruct(dce110_pool); 897 kfree(dce110_pool); 898 *pool = NULL; 899 } 900 901 static const struct resource_funcs dce120_res_pool_funcs = { 902 .destroy = dce120_destroy_resource_pool, 903 .link_enc_create = dce120_link_encoder_create, 904 .panel_cntl_create = dce120_panel_cntl_create, 905 .validate_bandwidth = dce112_validate_bandwidth, 906 .validate_plane = dce100_validate_plane, 907 .add_stream_to_ctx = dce112_add_stream_to_ctx, 908 .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link 909 }; 910 911 static void bw_calcs_data_update_from_pplib(struct dc *dc) 912 { 913 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 914 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 915 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; 916 int i; 917 unsigned int clk; 918 unsigned int latency; 919 /*original logic in dal3*/ 920 int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ; 921 922 /*do system clock*/ 923 if (!dm_pp_get_clock_levels_by_type_with_latency( 924 dc->ctx, 925 DM_PP_CLOCK_TYPE_ENGINE_CLK, 926 &eng_clks) || eng_clks.num_levels == 0) { 927 928 eng_clks.num_levels = 8; 929 clk = 300000; 930 931 for (i = 0; i < eng_clks.num_levels; i++) { 932 eng_clks.data[i].clocks_in_khz = clk; 933 clk += 100000; 934 } 935 } 936 937 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ 938 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 939 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); 940 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 941 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); 942 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 943 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); 944 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 945 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); 946 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 947 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); 948 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 949 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); 950 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 951 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); 952 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 953 eng_clks.data[0].clocks_in_khz, 1000); 954 955 /*do memory clock*/ 956 if (!dm_pp_get_clock_levels_by_type_with_latency( 957 dc->ctx, 958 DM_PP_CLOCK_TYPE_MEMORY_CLK, 959 &mem_clks) || mem_clks.num_levels == 0) { 960 961 mem_clks.num_levels = 3; 962 clk = 250000; 963 latency = 45; 964 965 for (i = 0; i < eng_clks.num_levels; i++) { 966 mem_clks.data[i].clocks_in_khz = clk; 967 mem_clks.data[i].latency_in_us = latency; 968 clk += 500000; 969 latency -= 5; 970 } 971 972 } 973 974 /* we don't need to call PPLIB for validation clock since they 975 * also give us the highest sclk and highest mclk (UMA clock). 976 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): 977 * YCLK = UMACLK*m_memoryTypeMultiplier 978 */ 979 if (dc->bw_vbios->memory_type == bw_def_hbm) 980 memory_type_multiplier = MEMORY_TYPE_HBM; 981 982 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 983 mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000); 984 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 985 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier, 986 1000); 987 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 988 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier, 989 1000); 990 991 /* Now notify PPLib/SMU about which Watermarks sets they should select 992 * depending on DPM state they are in. And update BW MGR GFX Engine and 993 * Memory clock member variables for Watermarks calculations for each 994 * Watermark Set 995 */ 996 clk_ranges.num_wm_sets = 4; 997 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; 998 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = 999 eng_clks.data[0].clocks_in_khz; 1000 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = 1001 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 1002 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz = 1003 mem_clks.data[0].clocks_in_khz; 1004 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = 1005 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 1006 1007 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; 1008 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = 1009 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 1010 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 1011 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; 1012 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz = 1013 mem_clks.data[0].clocks_in_khz; 1014 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = 1015 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 1016 1017 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; 1018 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = 1019 eng_clks.data[0].clocks_in_khz; 1020 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = 1021 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 1022 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz = 1023 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 1024 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 1025 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; 1026 1027 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; 1028 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = 1029 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 1030 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 1031 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; 1032 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz = 1033 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 1034 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 1035 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; 1036 1037 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 1038 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); 1039 } 1040 1041 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1042 { 1043 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); 1044 /* VG20 support max 6 pipes */ 1045 value = value & 0x3f; 1046 return value; 1047 } 1048 1049 static bool dce120_resource_construct( 1050 uint8_t num_virtual_links, 1051 struct dc *dc, 1052 struct dce110_resource_pool *pool) 1053 { 1054 unsigned int i; 1055 int j; 1056 struct dc_context *ctx = dc->ctx; 1057 struct irq_service_init_data irq_init_data; 1058 static const struct resource_create_funcs *res_funcs; 1059 bool is_vg20 = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev); 1060 uint32_t pipe_fuses; 1061 1062 ctx->dc_bios->regs = &bios_regs; 1063 1064 pool->base.res_cap = &res_cap; 1065 pool->base.funcs = &dce120_res_pool_funcs; 1066 1067 /* TODO: Fill more data from GreenlandAsicCapability.cpp */ 1068 pool->base.pipe_count = res_cap.num_timing_generator; 1069 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1070 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1071 1072 dc->caps.max_downscale_ratio = 200; 1073 dc->caps.i2c_speed_in_khz = 100; 1074 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/ 1075 dc->caps.max_cursor_size = 128; 1076 dc->caps.min_horizontal_blanking_period = 80; 1077 dc->caps.dual_link_dvi = true; 1078 dc->caps.psp_setup_panel_mode = true; 1079 dc->caps.extended_aux_timeout_support = false; 1080 dc->debug = debug_defaults; 1081 1082 /************************************************* 1083 * Create resources * 1084 *************************************************/ 1085 1086 pool->base.clock_sources[DCE120_CLK_SRC_PLL0] = 1087 dce120_clock_source_create(ctx, ctx->dc_bios, 1088 CLOCK_SOURCE_COMBO_PHY_PLL0, 1089 &clk_src_regs[0], false); 1090 pool->base.clock_sources[DCE120_CLK_SRC_PLL1] = 1091 dce120_clock_source_create(ctx, ctx->dc_bios, 1092 CLOCK_SOURCE_COMBO_PHY_PLL1, 1093 &clk_src_regs[1], false); 1094 pool->base.clock_sources[DCE120_CLK_SRC_PLL2] = 1095 dce120_clock_source_create(ctx, ctx->dc_bios, 1096 CLOCK_SOURCE_COMBO_PHY_PLL2, 1097 &clk_src_regs[2], false); 1098 pool->base.clock_sources[DCE120_CLK_SRC_PLL3] = 1099 dce120_clock_source_create(ctx, ctx->dc_bios, 1100 CLOCK_SOURCE_COMBO_PHY_PLL3, 1101 &clk_src_regs[3], false); 1102 pool->base.clock_sources[DCE120_CLK_SRC_PLL4] = 1103 dce120_clock_source_create(ctx, ctx->dc_bios, 1104 CLOCK_SOURCE_COMBO_PHY_PLL4, 1105 &clk_src_regs[4], false); 1106 pool->base.clock_sources[DCE120_CLK_SRC_PLL5] = 1107 dce120_clock_source_create(ctx, ctx->dc_bios, 1108 CLOCK_SOURCE_COMBO_PHY_PLL5, 1109 &clk_src_regs[5], false); 1110 pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL; 1111 1112 pool->base.dp_clock_source = 1113 dce120_clock_source_create(ctx, ctx->dc_bios, 1114 CLOCK_SOURCE_ID_DP_DTO, 1115 &clk_src_regs[0], true); 1116 1117 for (i = 0; i < pool->base.clk_src_count; i++) { 1118 if (pool->base.clock_sources[i] == NULL) { 1119 dm_error("DC: failed to create clock sources!\n"); 1120 BREAK_TO_DEBUGGER(); 1121 goto clk_src_create_fail; 1122 } 1123 } 1124 1125 pool->base.dmcu = dce_dmcu_create(ctx, 1126 &dmcu_regs, 1127 &dmcu_shift, 1128 &dmcu_mask); 1129 if (pool->base.dmcu == NULL) { 1130 dm_error("DC: failed to create dmcu!\n"); 1131 BREAK_TO_DEBUGGER(); 1132 goto res_create_fail; 1133 } 1134 1135 pool->base.abm = dce_abm_create(ctx, 1136 &abm_regs, 1137 &abm_shift, 1138 &abm_mask); 1139 if (pool->base.abm == NULL) { 1140 dm_error("DC: failed to create abm!\n"); 1141 BREAK_TO_DEBUGGER(); 1142 goto res_create_fail; 1143 } 1144 1145 1146 irq_init_data.ctx = dc->ctx; 1147 pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data); 1148 if (!pool->base.irqs) 1149 goto irqs_create_fail; 1150 1151 /* VG20: Pipe harvesting enabled, retrieve valid pipe fuses */ 1152 if (is_vg20) 1153 pipe_fuses = read_pipe_fuses(ctx); 1154 1155 /* index to valid pipe resource */ 1156 j = 0; 1157 for (i = 0; i < pool->base.pipe_count; i++) { 1158 if (is_vg20) { 1159 if ((pipe_fuses & (1 << i)) != 0) { 1160 dm_error("DC: skip invalid pipe %d!\n", i); 1161 continue; 1162 } 1163 } 1164 1165 pool->base.timing_generators[j] = 1166 dce120_timing_generator_create( 1167 ctx, 1168 i, 1169 &dce120_tg_offsets[i]); 1170 if (pool->base.timing_generators[j] == NULL) { 1171 BREAK_TO_DEBUGGER(); 1172 dm_error("DC: failed to create tg!\n"); 1173 goto controller_create_fail; 1174 } 1175 1176 pool->base.mis[j] = dce120_mem_input_create(ctx, i); 1177 1178 if (pool->base.mis[j] == NULL) { 1179 BREAK_TO_DEBUGGER(); 1180 dm_error( 1181 "DC: failed to create memory input!\n"); 1182 goto controller_create_fail; 1183 } 1184 1185 pool->base.ipps[j] = dce120_ipp_create(ctx, i); 1186 if (pool->base.ipps[i] == NULL) { 1187 BREAK_TO_DEBUGGER(); 1188 dm_error( 1189 "DC: failed to create input pixel processor!\n"); 1190 goto controller_create_fail; 1191 } 1192 1193 pool->base.transforms[j] = dce120_transform_create(ctx, i); 1194 if (pool->base.transforms[i] == NULL) { 1195 BREAK_TO_DEBUGGER(); 1196 dm_error( 1197 "DC: failed to create transform!\n"); 1198 goto res_create_fail; 1199 } 1200 1201 pool->base.opps[j] = dce120_opp_create( 1202 ctx, 1203 i); 1204 if (pool->base.opps[j] == NULL) { 1205 BREAK_TO_DEBUGGER(); 1206 dm_error( 1207 "DC: failed to create output pixel processor!\n"); 1208 } 1209 1210 /* check next valid pipe */ 1211 j++; 1212 } 1213 1214 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1215 pool->base.engines[i] = dce120_aux_engine_create(ctx, i); 1216 if (pool->base.engines[i] == NULL) { 1217 BREAK_TO_DEBUGGER(); 1218 dm_error( 1219 "DC:failed to create aux engine!!\n"); 1220 goto res_create_fail; 1221 } 1222 pool->base.hw_i2cs[i] = dce120_i2c_hw_create(ctx, i); 1223 if (pool->base.hw_i2cs[i] == NULL) { 1224 BREAK_TO_DEBUGGER(); 1225 dm_error( 1226 "DC:failed to create i2c engine!!\n"); 1227 goto res_create_fail; 1228 } 1229 pool->base.sw_i2cs[i] = NULL; 1230 } 1231 1232 /* valid pipe num */ 1233 pool->base.pipe_count = j; 1234 pool->base.timing_generator_count = j; 1235 1236 if (is_vg20) 1237 res_funcs = &dce121_res_create_funcs; 1238 else 1239 res_funcs = &res_create_funcs; 1240 1241 if (!resource_construct(num_virtual_links, dc, &pool->base, res_funcs)) 1242 goto res_create_fail; 1243 1244 /* Create hardware sequencer */ 1245 if (!dce120_hw_sequencer_create(dc)) 1246 goto controller_create_fail; 1247 1248 dc->caps.max_planes = pool->base.pipe_count; 1249 1250 for (i = 0; i < dc->caps.max_planes; ++i) 1251 dc->caps.planes[i] = plane_cap; 1252 1253 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1254 1255 bw_calcs_data_update_from_pplib(dc); 1256 1257 return true; 1258 1259 irqs_create_fail: 1260 controller_create_fail: 1261 clk_src_create_fail: 1262 res_create_fail: 1263 1264 dce120_resource_destruct(pool); 1265 1266 return false; 1267 } 1268 1269 struct resource_pool *dce120_create_resource_pool( 1270 uint8_t num_virtual_links, 1271 struct dc *dc) 1272 { 1273 struct dce110_resource_pool *pool = 1274 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1275 1276 if (!pool) 1277 return NULL; 1278 1279 if (dce120_resource_construct(num_virtual_links, dc, pool)) 1280 return &pool->base; 1281 1282 kfree(pool); 1283 BREAK_TO_DEBUGGER(); 1284 return NULL; 1285 } 1286