1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc.cls 3 * 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 29 30 #include "stream_encoder.h" 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dce120_resource.h" 34 #include "dce112/dce112_resource.h" 35 36 #include "dce110/dce110_resource.h" 37 #include "../virtual/virtual_stream_encoder.h" 38 #include "dce120_timing_generator.h" 39 #include "irq/dce120/irq_service_dce120.h" 40 #include "dce/dce_opp.h" 41 #include "dce/dce_clock_source.h" 42 #include "dce/dce_clocks.h" 43 #include "dce/dce_ipp.h" 44 #include "dce/dce_mem_input.h" 45 46 #include "dce110/dce110_hw_sequencer.h" 47 #include "dce120/dce120_hw_sequencer.h" 48 #include "dce/dce_transform.h" 49 50 #include "dce/dce_audio.h" 51 #include "dce/dce_link_encoder.h" 52 #include "dce/dce_stream_encoder.h" 53 #include "dce/dce_hwseq.h" 54 #include "dce/dce_abm.h" 55 #include "dce/dce_dmcu.h" 56 57 #include "vega10/DC/dce_12_0_offset.h" 58 #include "vega10/DC/dce_12_0_sh_mask.h" 59 #include "vega10/soc15ip.h" 60 #include "vega10/NBIO/nbio_6_1_offset.h" 61 #include "reg_helper.h" 62 63 #include "dce100/dce100_resource.h" 64 65 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 66 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 67 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 68 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 69 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 70 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 71 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 72 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 73 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 74 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 75 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 76 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 77 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 78 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 79 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 80 #endif 81 82 enum dce120_clk_src_array_id { 83 DCE120_CLK_SRC_PLL0, 84 DCE120_CLK_SRC_PLL1, 85 DCE120_CLK_SRC_PLL2, 86 DCE120_CLK_SRC_PLL3, 87 DCE120_CLK_SRC_PLL4, 88 DCE120_CLK_SRC_PLL5, 89 90 DCE120_CLK_SRC_TOTAL 91 }; 92 93 static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = { 94 { 95 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 96 }, 97 { 98 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 99 }, 100 { 101 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 102 }, 103 { 104 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 105 }, 106 { 107 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 108 }, 109 { 110 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 111 } 112 }; 113 114 /* begin ********************* 115 * macros to expend register list macro defined in HW object header file */ 116 117 #define BASE_INNER(seg) \ 118 DCE_BASE__INST0_SEG ## seg 119 120 #define NBIO_BASE_INNER(seg) \ 121 NBIF_BASE__INST0_SEG ## seg 122 123 #define NBIO_BASE(seg) \ 124 NBIO_BASE_INNER(seg) 125 126 /* compile time expand base address. */ 127 #define BASE(seg) \ 128 BASE_INNER(seg) 129 130 #define SR(reg_name)\ 131 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 132 mm ## reg_name 133 134 #define SRI(reg_name, block, id)\ 135 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 136 mm ## block ## id ## _ ## reg_name 137 138 /* macros to expend register list macro defined in HW object header file 139 * end *********************/ 140 141 142 static const struct dce_dmcu_registers dmcu_regs = { 143 DMCU_DCE110_COMMON_REG_LIST() 144 }; 145 146 static const struct dce_dmcu_shift dmcu_shift = { 147 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 148 }; 149 150 static const struct dce_dmcu_mask dmcu_mask = { 151 DMCU_MASK_SH_LIST_DCE110(_MASK) 152 }; 153 154 static const struct dce_abm_registers abm_regs = { 155 ABM_DCE110_COMMON_REG_LIST() 156 }; 157 158 static const struct dce_abm_shift abm_shift = { 159 ABM_MASK_SH_LIST_DCE110(__SHIFT) 160 }; 161 162 static const struct dce_abm_mask abm_mask = { 163 ABM_MASK_SH_LIST_DCE110(_MASK) 164 }; 165 166 #define ipp_regs(id)\ 167 [id] = {\ 168 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 169 } 170 171 static const struct dce_ipp_registers ipp_regs[] = { 172 ipp_regs(0), 173 ipp_regs(1), 174 ipp_regs(2), 175 ipp_regs(3), 176 ipp_regs(4), 177 ipp_regs(5) 178 }; 179 180 static const struct dce_ipp_shift ipp_shift = { 181 IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT) 182 }; 183 184 static const struct dce_ipp_mask ipp_mask = { 185 IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK) 186 }; 187 188 #define transform_regs(id)\ 189 [id] = {\ 190 XFM_COMMON_REG_LIST_DCE110(id)\ 191 } 192 193 static const struct dce_transform_registers xfm_regs[] = { 194 transform_regs(0), 195 transform_regs(1), 196 transform_regs(2), 197 transform_regs(3), 198 transform_regs(4), 199 transform_regs(5) 200 }; 201 202 static const struct dce_transform_shift xfm_shift = { 203 XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT) 204 }; 205 206 static const struct dce_transform_mask xfm_mask = { 207 XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK) 208 }; 209 210 #define aux_regs(id)\ 211 [id] = {\ 212 AUX_REG_LIST(id)\ 213 } 214 215 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 216 aux_regs(0), 217 aux_regs(1), 218 aux_regs(2), 219 aux_regs(3), 220 aux_regs(4), 221 aux_regs(5) 222 }; 223 224 #define hpd_regs(id)\ 225 [id] = {\ 226 HPD_REG_LIST(id)\ 227 } 228 229 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 230 hpd_regs(0), 231 hpd_regs(1), 232 hpd_regs(2), 233 hpd_regs(3), 234 hpd_regs(4), 235 hpd_regs(5) 236 }; 237 238 #define link_regs(id)\ 239 [id] = {\ 240 LE_DCE120_REG_LIST(id), \ 241 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 242 } 243 244 static const struct dce110_link_enc_registers link_enc_regs[] = { 245 link_regs(0), 246 link_regs(1), 247 link_regs(2), 248 link_regs(3), 249 link_regs(4), 250 link_regs(5), 251 link_regs(6), 252 }; 253 254 255 #define stream_enc_regs(id)\ 256 [id] = {\ 257 SE_COMMON_REG_LIST(id),\ 258 .TMDS_CNTL = 0,\ 259 } 260 261 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 262 stream_enc_regs(0), 263 stream_enc_regs(1), 264 stream_enc_regs(2), 265 stream_enc_regs(3), 266 stream_enc_regs(4), 267 stream_enc_regs(5) 268 }; 269 270 static const struct dce_stream_encoder_shift se_shift = { 271 SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT) 272 }; 273 274 static const struct dce_stream_encoder_mask se_mask = { 275 SE_COMMON_MASK_SH_LIST_DCE120(_MASK) 276 }; 277 278 #define opp_regs(id)\ 279 [id] = {\ 280 OPP_DCE_120_REG_LIST(id),\ 281 } 282 283 static const struct dce_opp_registers opp_regs[] = { 284 opp_regs(0), 285 opp_regs(1), 286 opp_regs(2), 287 opp_regs(3), 288 opp_regs(4), 289 opp_regs(5) 290 }; 291 292 static const struct dce_opp_shift opp_shift = { 293 OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT) 294 }; 295 296 static const struct dce_opp_mask opp_mask = { 297 OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK) 298 }; 299 300 #define audio_regs(id)\ 301 [id] = {\ 302 AUD_COMMON_REG_LIST(id)\ 303 } 304 305 static const struct dce_audio_registers audio_regs[] = { 306 audio_regs(0), 307 audio_regs(1), 308 audio_regs(2), 309 audio_regs(3), 310 audio_regs(4), 311 audio_regs(5) 312 }; 313 314 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 315 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 316 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 317 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 318 319 static const struct dce_audio_shift audio_shift = { 320 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 321 }; 322 323 static const struct dce_aduio_mask audio_mask = { 324 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 325 }; 326 327 #define clk_src_regs(index, id)\ 328 [index] = {\ 329 CS_COMMON_REG_LIST_DCE_112(id),\ 330 } 331 332 static const struct dce110_clk_src_regs clk_src_regs[] = { 333 clk_src_regs(0, A), 334 clk_src_regs(1, B), 335 clk_src_regs(2, C), 336 clk_src_regs(3, D), 337 clk_src_regs(4, E), 338 clk_src_regs(5, F) 339 }; 340 341 static const struct dce110_clk_src_shift cs_shift = { 342 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 343 }; 344 345 static const struct dce110_clk_src_mask cs_mask = { 346 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) 347 }; 348 349 struct output_pixel_processor *dce120_opp_create( 350 struct dc_context *ctx, 351 uint32_t inst) 352 { 353 struct dce110_opp *opp = 354 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 355 356 if (!opp) 357 return NULL; 358 359 dce110_opp_construct(opp, 360 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 361 return &opp->base; 362 } 363 364 static const struct bios_registers bios_regs = { 365 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX) 366 }; 367 368 static const struct resource_caps res_cap = { 369 .num_timing_generator = 6, 370 .num_audio = 7, 371 .num_stream_encoder = 6, 372 .num_pll = 6, 373 }; 374 375 static const struct dc_debug debug_defaults = { 376 .disable_clock_gate = true, 377 }; 378 379 struct clock_source *dce120_clock_source_create( 380 struct dc_context *ctx, 381 struct dc_bios *bios, 382 enum clock_source_id id, 383 const struct dce110_clk_src_regs *regs, 384 bool dp_clk_src) 385 { 386 struct dce110_clk_src *clk_src = 387 kzalloc(sizeof(*clk_src), GFP_KERNEL); 388 389 if (!clk_src) 390 return NULL; 391 392 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 393 regs, &cs_shift, &cs_mask)) { 394 clk_src->base.dp_clk_src = dp_clk_src; 395 return &clk_src->base; 396 } 397 398 BREAK_TO_DEBUGGER(); 399 return NULL; 400 } 401 402 void dce120_clock_source_destroy(struct clock_source **clk_src) 403 { 404 kfree(TO_DCE110_CLK_SRC(*clk_src)); 405 *clk_src = NULL; 406 } 407 408 409 bool dce120_hw_sequencer_create(struct dc *dc) 410 { 411 /* All registers used by dce11.2 match those in dce11 in offset and 412 * structure 413 */ 414 dce120_hw_sequencer_construct(dc); 415 416 /*TODO Move to separate file and Override what is needed */ 417 418 return true; 419 } 420 421 static struct timing_generator *dce120_timing_generator_create( 422 struct dc_context *ctx, 423 uint32_t instance, 424 const struct dce110_timing_generator_offsets *offsets) 425 { 426 struct dce110_timing_generator *tg110 = 427 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 428 429 if (!tg110) 430 return NULL; 431 432 dce120_timing_generator_construct(tg110, ctx, instance, offsets); 433 return &tg110->base; 434 } 435 436 static void dce120_transform_destroy(struct transform **xfm) 437 { 438 kfree(TO_DCE_TRANSFORM(*xfm)); 439 *xfm = NULL; 440 } 441 442 static void destruct(struct dce110_resource_pool *pool) 443 { 444 unsigned int i; 445 446 for (i = 0; i < pool->base.pipe_count; i++) { 447 if (pool->base.opps[i] != NULL) 448 dce110_opp_destroy(&pool->base.opps[i]); 449 450 if (pool->base.transforms[i] != NULL) 451 dce120_transform_destroy(&pool->base.transforms[i]); 452 453 if (pool->base.ipps[i] != NULL) 454 dce_ipp_destroy(&pool->base.ipps[i]); 455 456 if (pool->base.mis[i] != NULL) { 457 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 458 pool->base.mis[i] = NULL; 459 } 460 461 if (pool->base.irqs != NULL) { 462 dal_irq_service_destroy(&pool->base.irqs); 463 } 464 465 if (pool->base.timing_generators[i] != NULL) { 466 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 467 pool->base.timing_generators[i] = NULL; 468 } 469 } 470 471 for (i = 0; i < pool->base.audio_count; i++) { 472 if (pool->base.audios[i]) 473 dce_aud_destroy(&pool->base.audios[i]); 474 } 475 476 for (i = 0; i < pool->base.stream_enc_count; i++) { 477 if (pool->base.stream_enc[i] != NULL) 478 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 479 } 480 481 for (i = 0; i < pool->base.clk_src_count; i++) { 482 if (pool->base.clock_sources[i] != NULL) 483 dce120_clock_source_destroy( 484 &pool->base.clock_sources[i]); 485 } 486 487 if (pool->base.dp_clock_source != NULL) 488 dce120_clock_source_destroy(&pool->base.dp_clock_source); 489 490 if (pool->base.abm != NULL) 491 dce_abm_destroy(&pool->base.abm); 492 493 if (pool->base.dmcu != NULL) 494 dce_dmcu_destroy(&pool->base.dmcu); 495 496 if (pool->base.display_clock != NULL) 497 dce_disp_clk_destroy(&pool->base.display_clock); 498 } 499 500 static void read_dce_straps( 501 struct dc_context *ctx, 502 struct resource_straps *straps) 503 { 504 /* TODO: Registers are missing */ 505 /*REG_GET_2(CC_DC_HDMI_STRAPS, 506 HDMI_DISABLE, &straps->hdmi_disable, 507 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 508 509 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);*/ 510 } 511 512 static struct audio *create_audio( 513 struct dc_context *ctx, unsigned int inst) 514 { 515 return dce_audio_create(ctx, inst, 516 &audio_regs[inst], &audio_shift, &audio_mask); 517 } 518 519 static const struct encoder_feature_support link_enc_feature = { 520 .max_hdmi_deep_color = COLOR_DEPTH_121212, 521 .max_hdmi_pixel_clock = 600000, 522 .ycbcr420_supported = true, 523 .flags.bits.IS_HBR2_CAPABLE = true, 524 .flags.bits.IS_HBR3_CAPABLE = true, 525 .flags.bits.IS_TPS3_CAPABLE = true, 526 .flags.bits.IS_TPS4_CAPABLE = true, 527 .flags.bits.IS_YCBCR_CAPABLE = true 528 }; 529 530 static struct link_encoder *dce120_link_encoder_create( 531 const struct encoder_init_data *enc_init_data) 532 { 533 struct dce110_link_encoder *enc110 = 534 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 535 536 if (!enc110) 537 return NULL; 538 539 dce110_link_encoder_construct(enc110, 540 enc_init_data, 541 &link_enc_feature, 542 &link_enc_regs[enc_init_data->transmitter], 543 &link_enc_aux_regs[enc_init_data->channel - 1], 544 &link_enc_hpd_regs[enc_init_data->hpd_source]); 545 546 return &enc110->base; 547 } 548 549 static struct input_pixel_processor *dce120_ipp_create( 550 struct dc_context *ctx, uint32_t inst) 551 { 552 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 553 554 if (!ipp) { 555 BREAK_TO_DEBUGGER(); 556 return NULL; 557 } 558 559 dce_ipp_construct(ipp, ctx, inst, 560 &ipp_regs[inst], &ipp_shift, &ipp_mask); 561 return &ipp->base; 562 } 563 564 static struct stream_encoder *dce120_stream_encoder_create( 565 enum engine_id eng_id, 566 struct dc_context *ctx) 567 { 568 struct dce110_stream_encoder *enc110 = 569 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 570 571 if (!enc110) 572 return NULL; 573 574 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 575 &stream_enc_regs[eng_id], 576 &se_shift, &se_mask); 577 return &enc110->base; 578 } 579 580 #define SRII(reg_name, block, id)\ 581 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 582 mm ## block ## id ## _ ## reg_name 583 584 static const struct dce_hwseq_registers hwseq_reg = { 585 HWSEQ_DCE120_REG_LIST() 586 }; 587 588 static const struct dce_hwseq_shift hwseq_shift = { 589 HWSEQ_DCE12_MASK_SH_LIST(__SHIFT) 590 }; 591 592 static const struct dce_hwseq_mask hwseq_mask = { 593 HWSEQ_DCE12_MASK_SH_LIST(_MASK) 594 }; 595 596 static struct dce_hwseq *dce120_hwseq_create( 597 struct dc_context *ctx) 598 { 599 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 600 601 if (hws) { 602 hws->ctx = ctx; 603 hws->regs = &hwseq_reg; 604 hws->shifts = &hwseq_shift; 605 hws->masks = &hwseq_mask; 606 } 607 return hws; 608 } 609 610 static const struct resource_create_funcs res_create_funcs = { 611 .read_dce_straps = read_dce_straps, 612 .create_audio = create_audio, 613 .create_stream_encoder = dce120_stream_encoder_create, 614 .create_hwseq = dce120_hwseq_create, 615 }; 616 617 #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) } 618 static const struct dce_mem_input_registers mi_regs[] = { 619 mi_inst_regs(0), 620 mi_inst_regs(1), 621 mi_inst_regs(2), 622 mi_inst_regs(3), 623 mi_inst_regs(4), 624 mi_inst_regs(5), 625 }; 626 627 static const struct dce_mem_input_shift mi_shifts = { 628 MI_DCE12_MASK_SH_LIST(__SHIFT) 629 }; 630 631 static const struct dce_mem_input_mask mi_masks = { 632 MI_DCE12_MASK_SH_LIST(_MASK) 633 }; 634 635 static struct mem_input *dce120_mem_input_create( 636 struct dc_context *ctx, 637 uint32_t inst) 638 { 639 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 640 GFP_KERNEL); 641 642 if (!dce_mi) { 643 BREAK_TO_DEBUGGER(); 644 return NULL; 645 } 646 647 dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 648 return &dce_mi->base; 649 } 650 651 static struct transform *dce120_transform_create( 652 struct dc_context *ctx, 653 uint32_t inst) 654 { 655 struct dce_transform *transform = 656 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 657 658 if (!transform) 659 return NULL; 660 661 dce_transform_construct(transform, ctx, inst, 662 &xfm_regs[inst], &xfm_shift, &xfm_mask); 663 transform->lb_memory_size = 0x1404; /*5124*/ 664 return &transform->base; 665 } 666 667 static void dce120_destroy_resource_pool(struct resource_pool **pool) 668 { 669 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 670 671 destruct(dce110_pool); 672 kfree(dce110_pool); 673 *pool = NULL; 674 } 675 676 static const struct resource_funcs dce120_res_pool_funcs = { 677 .destroy = dce120_destroy_resource_pool, 678 .link_enc_create = dce120_link_encoder_create, 679 .validate_guaranteed = dce112_validate_guaranteed, 680 .validate_bandwidth = dce112_validate_bandwidth, 681 .validate_plane = dce100_validate_plane, 682 .add_stream_to_ctx = dce112_add_stream_to_ctx 683 }; 684 685 static void bw_calcs_data_update_from_pplib(struct dc *dc) 686 { 687 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 688 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 689 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; 690 int i; 691 unsigned int clk; 692 unsigned int latency; 693 694 /*do system clock*/ 695 if (!dm_pp_get_clock_levels_by_type_with_latency( 696 dc->ctx, 697 DM_PP_CLOCK_TYPE_ENGINE_CLK, 698 &eng_clks) || eng_clks.num_levels == 0) { 699 700 eng_clks.num_levels = 8; 701 clk = 300000; 702 703 for (i = 0; i < eng_clks.num_levels; i++) { 704 eng_clks.data[i].clocks_in_khz = clk; 705 clk += 100000; 706 } 707 } 708 709 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ 710 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 711 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); 712 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 713 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); 714 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 715 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); 716 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 717 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); 718 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 719 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); 720 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 721 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); 722 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 723 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); 724 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 725 eng_clks.data[0].clocks_in_khz, 1000); 726 727 /*do memory clock*/ 728 if (!dm_pp_get_clock_levels_by_type_with_latency( 729 dc->ctx, 730 DM_PP_CLOCK_TYPE_MEMORY_CLK, 731 &mem_clks) || mem_clks.num_levels == 0) { 732 733 mem_clks.num_levels = 3; 734 clk = 250000; 735 latency = 45; 736 737 for (i = 0; i < eng_clks.num_levels; i++) { 738 mem_clks.data[i].clocks_in_khz = clk; 739 mem_clks.data[i].latency_in_us = latency; 740 clk += 500000; 741 latency -= 5; 742 } 743 744 } 745 746 /* we don't need to call PPLIB for validation clock since they 747 * also give us the highest sclk and highest mclk (UMA clock). 748 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): 749 * YCLK = UMACLK*m_memoryTypeMultiplier 750 */ 751 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 752 mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000); 753 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 754 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 755 1000); 756 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 757 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 758 1000); 759 760 /* Now notify PPLib/SMU about which Watermarks sets they should select 761 * depending on DPM state they are in. And update BW MGR GFX Engine and 762 * Memory clock member variables for Watermarks calculations for each 763 * Watermark Set 764 */ 765 clk_ranges.num_wm_sets = 4; 766 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; 767 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = 768 eng_clks.data[0].clocks_in_khz; 769 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = 770 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 771 clk_ranges.wm_clk_ranges[0].wm_min_memg_clk_in_khz = 772 mem_clks.data[0].clocks_in_khz; 773 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = 774 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 775 776 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; 777 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = 778 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 779 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 780 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; 781 clk_ranges.wm_clk_ranges[1].wm_min_memg_clk_in_khz = 782 mem_clks.data[0].clocks_in_khz; 783 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = 784 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 785 786 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; 787 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = 788 eng_clks.data[0].clocks_in_khz; 789 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = 790 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 791 clk_ranges.wm_clk_ranges[2].wm_min_memg_clk_in_khz = 792 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 793 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 794 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; 795 796 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; 797 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = 798 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 799 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 800 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; 801 clk_ranges.wm_clk_ranges[3].wm_min_memg_clk_in_khz = 802 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 803 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 804 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; 805 806 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 807 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); 808 } 809 810 static bool construct( 811 uint8_t num_virtual_links, 812 struct dc *dc, 813 struct dce110_resource_pool *pool) 814 { 815 unsigned int i; 816 struct dc_context *ctx = dc->ctx; 817 struct irq_service_init_data irq_init_data; 818 819 ctx->dc_bios->regs = &bios_regs; 820 821 pool->base.res_cap = &res_cap; 822 pool->base.funcs = &dce120_res_pool_funcs; 823 824 /* TODO: Fill more data from GreenlandAsicCapability.cpp */ 825 pool->base.pipe_count = res_cap.num_timing_generator; 826 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 827 828 dc->caps.max_downscale_ratio = 200; 829 dc->caps.i2c_speed_in_khz = 100; 830 dc->caps.max_cursor_size = 128; 831 dc->debug = debug_defaults; 832 833 /************************************************* 834 * Create resources * 835 *************************************************/ 836 837 pool->base.clock_sources[DCE120_CLK_SRC_PLL0] = 838 dce120_clock_source_create(ctx, ctx->dc_bios, 839 CLOCK_SOURCE_COMBO_PHY_PLL0, 840 &clk_src_regs[0], false); 841 pool->base.clock_sources[DCE120_CLK_SRC_PLL1] = 842 dce120_clock_source_create(ctx, ctx->dc_bios, 843 CLOCK_SOURCE_COMBO_PHY_PLL1, 844 &clk_src_regs[1], false); 845 pool->base.clock_sources[DCE120_CLK_SRC_PLL2] = 846 dce120_clock_source_create(ctx, ctx->dc_bios, 847 CLOCK_SOURCE_COMBO_PHY_PLL2, 848 &clk_src_regs[2], false); 849 pool->base.clock_sources[DCE120_CLK_SRC_PLL3] = 850 dce120_clock_source_create(ctx, ctx->dc_bios, 851 CLOCK_SOURCE_COMBO_PHY_PLL3, 852 &clk_src_regs[3], false); 853 pool->base.clock_sources[DCE120_CLK_SRC_PLL4] = 854 dce120_clock_source_create(ctx, ctx->dc_bios, 855 CLOCK_SOURCE_COMBO_PHY_PLL4, 856 &clk_src_regs[4], false); 857 pool->base.clock_sources[DCE120_CLK_SRC_PLL5] = 858 dce120_clock_source_create(ctx, ctx->dc_bios, 859 CLOCK_SOURCE_COMBO_PHY_PLL5, 860 &clk_src_regs[5], false); 861 pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL; 862 863 pool->base.dp_clock_source = 864 dce120_clock_source_create(ctx, ctx->dc_bios, 865 CLOCK_SOURCE_ID_DP_DTO, 866 &clk_src_regs[0], true); 867 868 for (i = 0; i < pool->base.clk_src_count; i++) { 869 if (pool->base.clock_sources[i] == NULL) { 870 dm_error("DC: failed to create clock sources!\n"); 871 BREAK_TO_DEBUGGER(); 872 goto clk_src_create_fail; 873 } 874 } 875 876 pool->base.display_clock = dce120_disp_clk_create(ctx); 877 if (pool->base.display_clock == NULL) { 878 dm_error("DC: failed to create display clock!\n"); 879 BREAK_TO_DEBUGGER(); 880 goto disp_clk_create_fail; 881 } 882 883 pool->base.dmcu = dce_dmcu_create(ctx, 884 &dmcu_regs, 885 &dmcu_shift, 886 &dmcu_mask); 887 if (pool->base.dmcu == NULL) { 888 dm_error("DC: failed to create dmcu!\n"); 889 BREAK_TO_DEBUGGER(); 890 goto res_create_fail; 891 } 892 893 pool->base.abm = dce_abm_create(ctx, 894 &abm_regs, 895 &abm_shift, 896 &abm_mask); 897 if (pool->base.abm == NULL) { 898 dm_error("DC: failed to create abm!\n"); 899 BREAK_TO_DEBUGGER(); 900 goto res_create_fail; 901 } 902 903 irq_init_data.ctx = dc->ctx; 904 pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data); 905 if (!pool->base.irqs) 906 goto irqs_create_fail; 907 908 for (i = 0; i < pool->base.pipe_count; i++) { 909 pool->base.timing_generators[i] = 910 dce120_timing_generator_create( 911 ctx, 912 i, 913 &dce120_tg_offsets[i]); 914 if (pool->base.timing_generators[i] == NULL) { 915 BREAK_TO_DEBUGGER(); 916 dm_error("DC: failed to create tg!\n"); 917 goto controller_create_fail; 918 } 919 920 pool->base.mis[i] = dce120_mem_input_create(ctx, i); 921 922 if (pool->base.mis[i] == NULL) { 923 BREAK_TO_DEBUGGER(); 924 dm_error( 925 "DC: failed to create memory input!\n"); 926 goto controller_create_fail; 927 } 928 929 pool->base.ipps[i] = dce120_ipp_create(ctx, i); 930 if (pool->base.ipps[i] == NULL) { 931 BREAK_TO_DEBUGGER(); 932 dm_error( 933 "DC: failed to create input pixel processor!\n"); 934 goto controller_create_fail; 935 } 936 937 pool->base.transforms[i] = dce120_transform_create(ctx, i); 938 if (pool->base.transforms[i] == NULL) { 939 BREAK_TO_DEBUGGER(); 940 dm_error( 941 "DC: failed to create transform!\n"); 942 goto res_create_fail; 943 } 944 945 pool->base.opps[i] = dce120_opp_create( 946 ctx, 947 i); 948 if (pool->base.opps[i] == NULL) { 949 BREAK_TO_DEBUGGER(); 950 dm_error( 951 "DC: failed to create output pixel processor!\n"); 952 } 953 } 954 955 if (!resource_construct(num_virtual_links, dc, &pool->base, 956 &res_create_funcs)) 957 goto res_create_fail; 958 959 /* Create hardware sequencer */ 960 if (!dce120_hw_sequencer_create(dc)) 961 goto controller_create_fail; 962 963 dc->caps.max_planes = pool->base.pipe_count; 964 965 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 966 967 bw_calcs_data_update_from_pplib(dc); 968 969 return true; 970 971 irqs_create_fail: 972 controller_create_fail: 973 disp_clk_create_fail: 974 clk_src_create_fail: 975 res_create_fail: 976 977 destruct(pool); 978 979 return false; 980 } 981 982 struct resource_pool *dce120_create_resource_pool( 983 uint8_t num_virtual_links, 984 struct dc *dc) 985 { 986 struct dce110_resource_pool *pool = 987 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 988 989 if (!pool) 990 return NULL; 991 992 if (construct(num_virtual_links, dc, pool)) 993 return &pool->base; 994 995 BREAK_TO_DEBUGGER(); 996 return NULL; 997 } 998