1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc.cls 3 * 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include <linux/slab.h> 28 29 #include "dm_services.h" 30 31 32 #include "stream_encoder.h" 33 #include "resource.h" 34 #include "include/irq_service_interface.h" 35 #include "dce120_resource.h" 36 37 #include "dce112/dce112_resource.h" 38 39 #include "dce110/dce110_resource.h" 40 #include "../virtual/virtual_stream_encoder.h" 41 #include "dce120_timing_generator.h" 42 #include "irq/dce120/irq_service_dce120.h" 43 #include "dce/dce_opp.h" 44 #include "dce/dce_clock_source.h" 45 #include "dce/dce_ipp.h" 46 #include "dce/dce_mem_input.h" 47 48 #include "dce110/dce110_hw_sequencer.h" 49 #include "dce120/dce120_hw_sequencer.h" 50 #include "dce/dce_transform.h" 51 #include "clk_mgr.h" 52 #include "dce/dce_audio.h" 53 #include "dce/dce_link_encoder.h" 54 #include "dce/dce_stream_encoder.h" 55 #include "dce/dce_hwseq.h" 56 #include "dce/dce_abm.h" 57 #include "dce/dce_dmcu.h" 58 #include "dce/dce_aux.h" 59 #include "dce/dce_i2c.h" 60 61 #include "dce/dce_12_0_offset.h" 62 #include "dce/dce_12_0_sh_mask.h" 63 #include "soc15_hw_ip.h" 64 #include "vega10_ip_offset.h" 65 #include "nbio/nbio_6_1_offset.h" 66 #include "mmhub/mmhub_9_4_0_offset.h" 67 #include "mmhub/mmhub_9_4_0_sh_mask.h" 68 #include "reg_helper.h" 69 70 #include "dce100/dce100_resource.h" 71 72 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 73 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 74 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 75 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 76 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 77 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 78 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 79 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 80 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 81 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 82 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 83 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 84 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 85 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 86 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 87 #endif 88 89 enum dce120_clk_src_array_id { 90 DCE120_CLK_SRC_PLL0, 91 DCE120_CLK_SRC_PLL1, 92 DCE120_CLK_SRC_PLL2, 93 DCE120_CLK_SRC_PLL3, 94 DCE120_CLK_SRC_PLL4, 95 DCE120_CLK_SRC_PLL5, 96 97 DCE120_CLK_SRC_TOTAL 98 }; 99 100 static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = { 101 { 102 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 103 }, 104 { 105 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 106 }, 107 { 108 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 109 }, 110 { 111 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 112 }, 113 { 114 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 115 }, 116 { 117 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 118 } 119 }; 120 121 /* begin ********************* 122 * macros to expend register list macro defined in HW object header file */ 123 124 #define BASE_INNER(seg) \ 125 DCE_BASE__INST0_SEG ## seg 126 127 #define NBIO_BASE_INNER(seg) \ 128 NBIF_BASE__INST0_SEG ## seg 129 130 #define NBIO_BASE(seg) \ 131 NBIO_BASE_INNER(seg) 132 133 /* compile time expand base address. */ 134 #define BASE(seg) \ 135 BASE_INNER(seg) 136 137 #define SR(reg_name)\ 138 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 139 mm ## reg_name 140 141 #define SRI(reg_name, block, id)\ 142 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 143 mm ## block ## id ## _ ## reg_name 144 145 /* MMHUB */ 146 #define MMHUB_BASE_INNER(seg) \ 147 MMHUB_BASE__INST0_SEG ## seg 148 149 #define MMHUB_BASE(seg) \ 150 MMHUB_BASE_INNER(seg) 151 152 #define MMHUB_SR(reg_name)\ 153 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 154 mm ## reg_name 155 156 /* macros to expend register list macro defined in HW object header file 157 * end *********************/ 158 159 160 static const struct dce_dmcu_registers dmcu_regs = { 161 DMCU_DCE110_COMMON_REG_LIST() 162 }; 163 164 static const struct dce_dmcu_shift dmcu_shift = { 165 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 166 }; 167 168 static const struct dce_dmcu_mask dmcu_mask = { 169 DMCU_MASK_SH_LIST_DCE110(_MASK) 170 }; 171 172 static const struct dce_abm_registers abm_regs = { 173 ABM_DCE110_COMMON_REG_LIST() 174 }; 175 176 static const struct dce_abm_shift abm_shift = { 177 ABM_MASK_SH_LIST_DCE110(__SHIFT) 178 }; 179 180 static const struct dce_abm_mask abm_mask = { 181 ABM_MASK_SH_LIST_DCE110(_MASK) 182 }; 183 184 #define ipp_regs(id)\ 185 [id] = {\ 186 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 187 } 188 189 static const struct dce_ipp_registers ipp_regs[] = { 190 ipp_regs(0), 191 ipp_regs(1), 192 ipp_regs(2), 193 ipp_regs(3), 194 ipp_regs(4), 195 ipp_regs(5) 196 }; 197 198 static const struct dce_ipp_shift ipp_shift = { 199 IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT) 200 }; 201 202 static const struct dce_ipp_mask ipp_mask = { 203 IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK) 204 }; 205 206 #define transform_regs(id)\ 207 [id] = {\ 208 XFM_COMMON_REG_LIST_DCE110(id)\ 209 } 210 211 static const struct dce_transform_registers xfm_regs[] = { 212 transform_regs(0), 213 transform_regs(1), 214 transform_regs(2), 215 transform_regs(3), 216 transform_regs(4), 217 transform_regs(5) 218 }; 219 220 static const struct dce_transform_shift xfm_shift = { 221 XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT) 222 }; 223 224 static const struct dce_transform_mask xfm_mask = { 225 XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK) 226 }; 227 228 #define aux_regs(id)\ 229 [id] = {\ 230 AUX_REG_LIST(id)\ 231 } 232 233 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 234 aux_regs(0), 235 aux_regs(1), 236 aux_regs(2), 237 aux_regs(3), 238 aux_regs(4), 239 aux_regs(5) 240 }; 241 242 #define hpd_regs(id)\ 243 [id] = {\ 244 HPD_REG_LIST(id)\ 245 } 246 247 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 248 hpd_regs(0), 249 hpd_regs(1), 250 hpd_regs(2), 251 hpd_regs(3), 252 hpd_regs(4), 253 hpd_regs(5) 254 }; 255 256 #define link_regs(id)\ 257 [id] = {\ 258 LE_DCE120_REG_LIST(id), \ 259 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 260 } 261 262 static const struct dce110_link_enc_registers link_enc_regs[] = { 263 link_regs(0), 264 link_regs(1), 265 link_regs(2), 266 link_regs(3), 267 link_regs(4), 268 link_regs(5), 269 link_regs(6), 270 }; 271 272 273 #define stream_enc_regs(id)\ 274 [id] = {\ 275 SE_COMMON_REG_LIST(id),\ 276 .TMDS_CNTL = 0,\ 277 } 278 279 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 280 stream_enc_regs(0), 281 stream_enc_regs(1), 282 stream_enc_regs(2), 283 stream_enc_regs(3), 284 stream_enc_regs(4), 285 stream_enc_regs(5) 286 }; 287 288 static const struct dce_stream_encoder_shift se_shift = { 289 SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT) 290 }; 291 292 static const struct dce_stream_encoder_mask se_mask = { 293 SE_COMMON_MASK_SH_LIST_DCE120(_MASK) 294 }; 295 296 static const struct dce110_aux_registers_shift aux_shift = { 297 DCE12_AUX_MASK_SH_LIST(__SHIFT) 298 }; 299 300 static const struct dce110_aux_registers_mask aux_mask = { 301 DCE12_AUX_MASK_SH_LIST(_MASK) 302 }; 303 304 #define opp_regs(id)\ 305 [id] = {\ 306 OPP_DCE_120_REG_LIST(id),\ 307 } 308 309 static const struct dce_opp_registers opp_regs[] = { 310 opp_regs(0), 311 opp_regs(1), 312 opp_regs(2), 313 opp_regs(3), 314 opp_regs(4), 315 opp_regs(5) 316 }; 317 318 static const struct dce_opp_shift opp_shift = { 319 OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT) 320 }; 321 322 static const struct dce_opp_mask opp_mask = { 323 OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK) 324 }; 325 #define aux_engine_regs(id)\ 326 [id] = {\ 327 AUX_COMMON_REG_LIST(id), \ 328 .AUX_RESET_MASK = 0 \ 329 } 330 331 static const struct dce110_aux_registers aux_engine_regs[] = { 332 aux_engine_regs(0), 333 aux_engine_regs(1), 334 aux_engine_regs(2), 335 aux_engine_regs(3), 336 aux_engine_regs(4), 337 aux_engine_regs(5) 338 }; 339 340 #define audio_regs(id)\ 341 [id] = {\ 342 AUD_COMMON_REG_LIST(id)\ 343 } 344 345 static const struct dce_audio_registers audio_regs[] = { 346 audio_regs(0), 347 audio_regs(1), 348 audio_regs(2), 349 audio_regs(3), 350 audio_regs(4), 351 audio_regs(5) 352 }; 353 354 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 355 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 356 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 357 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 358 359 static const struct dce_audio_shift audio_shift = { 360 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 361 }; 362 363 static const struct dce_audio_mask audio_mask = { 364 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 365 }; 366 367 #define clk_src_regs(index, id)\ 368 [index] = {\ 369 CS_COMMON_REG_LIST_DCE_112(id),\ 370 } 371 372 static const struct dce110_clk_src_regs clk_src_regs[] = { 373 clk_src_regs(0, A), 374 clk_src_regs(1, B), 375 clk_src_regs(2, C), 376 clk_src_regs(3, D), 377 clk_src_regs(4, E), 378 clk_src_regs(5, F) 379 }; 380 381 static const struct dce110_clk_src_shift cs_shift = { 382 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 383 }; 384 385 static const struct dce110_clk_src_mask cs_mask = { 386 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) 387 }; 388 389 struct output_pixel_processor *dce120_opp_create( 390 struct dc_context *ctx, 391 uint32_t inst) 392 { 393 struct dce110_opp *opp = 394 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 395 396 if (!opp) 397 return NULL; 398 399 dce110_opp_construct(opp, 400 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 401 return &opp->base; 402 } 403 struct dce_aux *dce120_aux_engine_create( 404 struct dc_context *ctx, 405 uint32_t inst) 406 { 407 struct aux_engine_dce110 *aux_engine = 408 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 409 410 if (!aux_engine) 411 return NULL; 412 413 dce110_aux_engine_construct(aux_engine, ctx, inst, 414 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 415 &aux_engine_regs[inst], 416 &aux_mask, 417 &aux_shift, 418 ctx->dc->caps.extended_aux_timeout_support); 419 420 return &aux_engine->base; 421 } 422 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 423 424 static const struct dce_i2c_registers i2c_hw_regs[] = { 425 i2c_inst_regs(1), 426 i2c_inst_regs(2), 427 i2c_inst_regs(3), 428 i2c_inst_regs(4), 429 i2c_inst_regs(5), 430 i2c_inst_regs(6), 431 }; 432 433 static const struct dce_i2c_shift i2c_shifts = { 434 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 435 }; 436 437 static const struct dce_i2c_mask i2c_masks = { 438 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 439 }; 440 441 struct dce_i2c_hw *dce120_i2c_hw_create( 442 struct dc_context *ctx, 443 uint32_t inst) 444 { 445 struct dce_i2c_hw *dce_i2c_hw = 446 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 447 448 if (!dce_i2c_hw) 449 return NULL; 450 451 dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst, 452 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 453 454 return dce_i2c_hw; 455 } 456 static const struct bios_registers bios_regs = { 457 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + NBIO_BASE(mmBIOS_SCRATCH_3_BASE_IDX), 458 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX) 459 }; 460 461 static const struct resource_caps res_cap = { 462 .num_timing_generator = 6, 463 .num_audio = 7, 464 .num_stream_encoder = 6, 465 .num_pll = 6, 466 .num_ddc = 6, 467 }; 468 469 static const struct dc_plane_cap plane_cap = { 470 .type = DC_PLANE_TYPE_DCE_RGB, 471 472 .pixel_format_support = { 473 .argb8888 = true, 474 .nv12 = false, 475 .fp16 = false 476 }, 477 478 .max_upscale_factor = { 479 .argb8888 = 16000, 480 .nv12 = 1, 481 .fp16 = 1 482 }, 483 484 .max_downscale_factor = { 485 .argb8888 = 250, 486 .nv12 = 1, 487 .fp16 = 1 488 } 489 }; 490 491 static const struct dc_debug_options debug_defaults = { 492 .disable_clock_gate = true, 493 }; 494 495 static struct clock_source *dce120_clock_source_create( 496 struct dc_context *ctx, 497 struct dc_bios *bios, 498 enum clock_source_id id, 499 const struct dce110_clk_src_regs *regs, 500 bool dp_clk_src) 501 { 502 struct dce110_clk_src *clk_src = 503 kzalloc(sizeof(*clk_src), GFP_KERNEL); 504 505 if (!clk_src) 506 return NULL; 507 508 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 509 regs, &cs_shift, &cs_mask)) { 510 clk_src->base.dp_clk_src = dp_clk_src; 511 return &clk_src->base; 512 } 513 514 kfree(clk_src); 515 BREAK_TO_DEBUGGER(); 516 return NULL; 517 } 518 519 static void dce120_clock_source_destroy(struct clock_source **clk_src) 520 { 521 kfree(TO_DCE110_CLK_SRC(*clk_src)); 522 *clk_src = NULL; 523 } 524 525 526 static bool dce120_hw_sequencer_create(struct dc *dc) 527 { 528 /* All registers used by dce11.2 match those in dce11 in offset and 529 * structure 530 */ 531 dce120_hw_sequencer_construct(dc); 532 533 /*TODO Move to separate file and Override what is needed */ 534 535 return true; 536 } 537 538 static struct timing_generator *dce120_timing_generator_create( 539 struct dc_context *ctx, 540 uint32_t instance, 541 const struct dce110_timing_generator_offsets *offsets) 542 { 543 struct dce110_timing_generator *tg110 = 544 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 545 546 if (!tg110) 547 return NULL; 548 549 dce120_timing_generator_construct(tg110, ctx, instance, offsets); 550 return &tg110->base; 551 } 552 553 static void dce120_transform_destroy(struct transform **xfm) 554 { 555 kfree(TO_DCE_TRANSFORM(*xfm)); 556 *xfm = NULL; 557 } 558 559 static void destruct(struct dce110_resource_pool *pool) 560 { 561 unsigned int i; 562 563 for (i = 0; i < pool->base.pipe_count; i++) { 564 if (pool->base.opps[i] != NULL) 565 dce110_opp_destroy(&pool->base.opps[i]); 566 567 if (pool->base.transforms[i] != NULL) 568 dce120_transform_destroy(&pool->base.transforms[i]); 569 570 if (pool->base.ipps[i] != NULL) 571 dce_ipp_destroy(&pool->base.ipps[i]); 572 573 if (pool->base.mis[i] != NULL) { 574 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 575 pool->base.mis[i] = NULL; 576 } 577 578 if (pool->base.irqs != NULL) { 579 dal_irq_service_destroy(&pool->base.irqs); 580 } 581 582 if (pool->base.timing_generators[i] != NULL) { 583 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 584 pool->base.timing_generators[i] = NULL; 585 } 586 } 587 588 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 589 if (pool->base.engines[i] != NULL) 590 dce110_engine_destroy(&pool->base.engines[i]); 591 if (pool->base.hw_i2cs[i] != NULL) { 592 kfree(pool->base.hw_i2cs[i]); 593 pool->base.hw_i2cs[i] = NULL; 594 } 595 if (pool->base.sw_i2cs[i] != NULL) { 596 kfree(pool->base.sw_i2cs[i]); 597 pool->base.sw_i2cs[i] = NULL; 598 } 599 } 600 601 for (i = 0; i < pool->base.audio_count; i++) { 602 if (pool->base.audios[i]) 603 dce_aud_destroy(&pool->base.audios[i]); 604 } 605 606 for (i = 0; i < pool->base.stream_enc_count; i++) { 607 if (pool->base.stream_enc[i] != NULL) 608 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 609 } 610 611 for (i = 0; i < pool->base.clk_src_count; i++) { 612 if (pool->base.clock_sources[i] != NULL) 613 dce120_clock_source_destroy( 614 &pool->base.clock_sources[i]); 615 } 616 617 if (pool->base.dp_clock_source != NULL) 618 dce120_clock_source_destroy(&pool->base.dp_clock_source); 619 620 if (pool->base.abm != NULL) 621 dce_abm_destroy(&pool->base.abm); 622 623 if (pool->base.dmcu != NULL) 624 dce_dmcu_destroy(&pool->base.dmcu); 625 } 626 627 static void read_dce_straps( 628 struct dc_context *ctx, 629 struct resource_straps *straps) 630 { 631 uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0); 632 633 straps->audio_stream_number = get_reg_field_value(reg_val, 634 CC_DC_MISC_STRAPS, 635 AUDIO_STREAM_NUMBER); 636 straps->hdmi_disable = get_reg_field_value(reg_val, 637 CC_DC_MISC_STRAPS, 638 HDMI_DISABLE); 639 640 reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0); 641 straps->dc_pinstraps_audio = get_reg_field_value(reg_val, 642 DC_PINSTRAPS, 643 DC_PINSTRAPS_AUDIO); 644 } 645 646 static struct audio *create_audio( 647 struct dc_context *ctx, unsigned int inst) 648 { 649 return dce_audio_create(ctx, inst, 650 &audio_regs[inst], &audio_shift, &audio_mask); 651 } 652 653 static const struct encoder_feature_support link_enc_feature = { 654 .max_hdmi_deep_color = COLOR_DEPTH_121212, 655 .max_hdmi_pixel_clock = 600000, 656 .hdmi_ycbcr420_supported = true, 657 .dp_ycbcr420_supported = false, 658 .flags.bits.IS_HBR2_CAPABLE = true, 659 .flags.bits.IS_HBR3_CAPABLE = true, 660 .flags.bits.IS_TPS3_CAPABLE = true, 661 .flags.bits.IS_TPS4_CAPABLE = true, 662 }; 663 664 static struct link_encoder *dce120_link_encoder_create( 665 const struct encoder_init_data *enc_init_data) 666 { 667 struct dce110_link_encoder *enc110 = 668 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 669 670 if (!enc110) 671 return NULL; 672 673 dce110_link_encoder_construct(enc110, 674 enc_init_data, 675 &link_enc_feature, 676 &link_enc_regs[enc_init_data->transmitter], 677 &link_enc_aux_regs[enc_init_data->channel - 1], 678 &link_enc_hpd_regs[enc_init_data->hpd_source]); 679 680 return &enc110->base; 681 } 682 683 static struct input_pixel_processor *dce120_ipp_create( 684 struct dc_context *ctx, uint32_t inst) 685 { 686 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 687 688 if (!ipp) { 689 BREAK_TO_DEBUGGER(); 690 return NULL; 691 } 692 693 dce_ipp_construct(ipp, ctx, inst, 694 &ipp_regs[inst], &ipp_shift, &ipp_mask); 695 return &ipp->base; 696 } 697 698 static struct stream_encoder *dce120_stream_encoder_create( 699 enum engine_id eng_id, 700 struct dc_context *ctx) 701 { 702 struct dce110_stream_encoder *enc110 = 703 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 704 705 if (!enc110) 706 return NULL; 707 708 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 709 &stream_enc_regs[eng_id], 710 &se_shift, &se_mask); 711 return &enc110->base; 712 } 713 714 #define SRII(reg_name, block, id)\ 715 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 716 mm ## block ## id ## _ ## reg_name 717 718 static const struct dce_hwseq_registers hwseq_reg = { 719 HWSEQ_DCE120_REG_LIST() 720 }; 721 722 static const struct dce_hwseq_shift hwseq_shift = { 723 HWSEQ_DCE12_MASK_SH_LIST(__SHIFT) 724 }; 725 726 static const struct dce_hwseq_mask hwseq_mask = { 727 HWSEQ_DCE12_MASK_SH_LIST(_MASK) 728 }; 729 730 /* HWSEQ regs for VG20 */ 731 static const struct dce_hwseq_registers dce121_hwseq_reg = { 732 HWSEQ_VG20_REG_LIST() 733 }; 734 735 static const struct dce_hwseq_shift dce121_hwseq_shift = { 736 HWSEQ_VG20_MASK_SH_LIST(__SHIFT) 737 }; 738 739 static const struct dce_hwseq_mask dce121_hwseq_mask = { 740 HWSEQ_VG20_MASK_SH_LIST(_MASK) 741 }; 742 743 static struct dce_hwseq *dce120_hwseq_create( 744 struct dc_context *ctx) 745 { 746 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 747 748 if (hws) { 749 hws->ctx = ctx; 750 hws->regs = &hwseq_reg; 751 hws->shifts = &hwseq_shift; 752 hws->masks = &hwseq_mask; 753 } 754 return hws; 755 } 756 757 static struct dce_hwseq *dce121_hwseq_create( 758 struct dc_context *ctx) 759 { 760 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 761 762 if (hws) { 763 hws->ctx = ctx; 764 hws->regs = &dce121_hwseq_reg; 765 hws->shifts = &dce121_hwseq_shift; 766 hws->masks = &dce121_hwseq_mask; 767 } 768 return hws; 769 } 770 771 static const struct resource_create_funcs res_create_funcs = { 772 .read_dce_straps = read_dce_straps, 773 .create_audio = create_audio, 774 .create_stream_encoder = dce120_stream_encoder_create, 775 .create_hwseq = dce120_hwseq_create, 776 }; 777 778 static const struct resource_create_funcs dce121_res_create_funcs = { 779 .read_dce_straps = read_dce_straps, 780 .create_audio = create_audio, 781 .create_stream_encoder = dce120_stream_encoder_create, 782 .create_hwseq = dce121_hwseq_create, 783 }; 784 785 786 #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) } 787 static const struct dce_mem_input_registers mi_regs[] = { 788 mi_inst_regs(0), 789 mi_inst_regs(1), 790 mi_inst_regs(2), 791 mi_inst_regs(3), 792 mi_inst_regs(4), 793 mi_inst_regs(5), 794 }; 795 796 static const struct dce_mem_input_shift mi_shifts = { 797 MI_DCE12_MASK_SH_LIST(__SHIFT) 798 }; 799 800 static const struct dce_mem_input_mask mi_masks = { 801 MI_DCE12_MASK_SH_LIST(_MASK) 802 }; 803 804 static struct mem_input *dce120_mem_input_create( 805 struct dc_context *ctx, 806 uint32_t inst) 807 { 808 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 809 GFP_KERNEL); 810 811 if (!dce_mi) { 812 BREAK_TO_DEBUGGER(); 813 return NULL; 814 } 815 816 dce120_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 817 return &dce_mi->base; 818 } 819 820 static struct transform *dce120_transform_create( 821 struct dc_context *ctx, 822 uint32_t inst) 823 { 824 struct dce_transform *transform = 825 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 826 827 if (!transform) 828 return NULL; 829 830 dce_transform_construct(transform, ctx, inst, 831 &xfm_regs[inst], &xfm_shift, &xfm_mask); 832 transform->lb_memory_size = 0x1404; /*5124*/ 833 return &transform->base; 834 } 835 836 static void dce120_destroy_resource_pool(struct resource_pool **pool) 837 { 838 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 839 840 destruct(dce110_pool); 841 kfree(dce110_pool); 842 *pool = NULL; 843 } 844 845 static const struct resource_funcs dce120_res_pool_funcs = { 846 .destroy = dce120_destroy_resource_pool, 847 .link_enc_create = dce120_link_encoder_create, 848 .validate_bandwidth = dce112_validate_bandwidth, 849 .validate_plane = dce100_validate_plane, 850 .add_stream_to_ctx = dce112_add_stream_to_ctx, 851 .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link 852 }; 853 854 static void bw_calcs_data_update_from_pplib(struct dc *dc) 855 { 856 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 857 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 858 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; 859 int i; 860 unsigned int clk; 861 unsigned int latency; 862 /*original logic in dal3*/ 863 int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ; 864 865 /*do system clock*/ 866 if (!dm_pp_get_clock_levels_by_type_with_latency( 867 dc->ctx, 868 DM_PP_CLOCK_TYPE_ENGINE_CLK, 869 &eng_clks) || eng_clks.num_levels == 0) { 870 871 eng_clks.num_levels = 8; 872 clk = 300000; 873 874 for (i = 0; i < eng_clks.num_levels; i++) { 875 eng_clks.data[i].clocks_in_khz = clk; 876 clk += 100000; 877 } 878 } 879 880 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ 881 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 882 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); 883 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 884 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); 885 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 886 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); 887 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 888 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); 889 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 890 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); 891 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 892 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); 893 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 894 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); 895 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 896 eng_clks.data[0].clocks_in_khz, 1000); 897 898 /*do memory clock*/ 899 if (!dm_pp_get_clock_levels_by_type_with_latency( 900 dc->ctx, 901 DM_PP_CLOCK_TYPE_MEMORY_CLK, 902 &mem_clks) || mem_clks.num_levels == 0) { 903 904 mem_clks.num_levels = 3; 905 clk = 250000; 906 latency = 45; 907 908 for (i = 0; i < eng_clks.num_levels; i++) { 909 mem_clks.data[i].clocks_in_khz = clk; 910 mem_clks.data[i].latency_in_us = latency; 911 clk += 500000; 912 latency -= 5; 913 } 914 915 } 916 917 /* we don't need to call PPLIB for validation clock since they 918 * also give us the highest sclk and highest mclk (UMA clock). 919 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): 920 * YCLK = UMACLK*m_memoryTypeMultiplier 921 */ 922 if (dc->bw_vbios->memory_type == bw_def_hbm) 923 memory_type_multiplier = MEMORY_TYPE_HBM; 924 925 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 926 mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000); 927 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 928 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier, 929 1000); 930 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 931 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier, 932 1000); 933 934 /* Now notify PPLib/SMU about which Watermarks sets they should select 935 * depending on DPM state they are in. And update BW MGR GFX Engine and 936 * Memory clock member variables for Watermarks calculations for each 937 * Watermark Set 938 */ 939 clk_ranges.num_wm_sets = 4; 940 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; 941 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = 942 eng_clks.data[0].clocks_in_khz; 943 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = 944 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 945 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz = 946 mem_clks.data[0].clocks_in_khz; 947 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = 948 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 949 950 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; 951 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = 952 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 953 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 954 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; 955 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz = 956 mem_clks.data[0].clocks_in_khz; 957 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = 958 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 959 960 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; 961 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = 962 eng_clks.data[0].clocks_in_khz; 963 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = 964 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 965 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz = 966 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 967 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 968 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; 969 970 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; 971 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = 972 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 973 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 974 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; 975 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz = 976 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 977 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 978 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; 979 980 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 981 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); 982 } 983 984 static uint32_t read_pipe_fuses(struct dc_context *ctx) 985 { 986 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); 987 /* VG20 support max 6 pipes */ 988 value = value & 0x3f; 989 return value; 990 } 991 992 static bool construct( 993 uint8_t num_virtual_links, 994 struct dc *dc, 995 struct dce110_resource_pool *pool) 996 { 997 unsigned int i; 998 int j; 999 struct dc_context *ctx = dc->ctx; 1000 struct irq_service_init_data irq_init_data; 1001 static const struct resource_create_funcs *res_funcs; 1002 bool is_vg20 = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev); 1003 uint32_t pipe_fuses; 1004 1005 ctx->dc_bios->regs = &bios_regs; 1006 1007 pool->base.res_cap = &res_cap; 1008 pool->base.funcs = &dce120_res_pool_funcs; 1009 1010 /* TODO: Fill more data from GreenlandAsicCapability.cpp */ 1011 pool->base.pipe_count = res_cap.num_timing_generator; 1012 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1013 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1014 1015 dc->caps.max_downscale_ratio = 200; 1016 dc->caps.i2c_speed_in_khz = 100; 1017 dc->caps.max_cursor_size = 128; 1018 dc->caps.dual_link_dvi = true; 1019 dc->caps.psp_setup_panel_mode = true; 1020 dc->caps.extended_aux_timeout_support = false; 1021 dc->debug = debug_defaults; 1022 1023 /************************************************* 1024 * Create resources * 1025 *************************************************/ 1026 1027 pool->base.clock_sources[DCE120_CLK_SRC_PLL0] = 1028 dce120_clock_source_create(ctx, ctx->dc_bios, 1029 CLOCK_SOURCE_COMBO_PHY_PLL0, 1030 &clk_src_regs[0], false); 1031 pool->base.clock_sources[DCE120_CLK_SRC_PLL1] = 1032 dce120_clock_source_create(ctx, ctx->dc_bios, 1033 CLOCK_SOURCE_COMBO_PHY_PLL1, 1034 &clk_src_regs[1], false); 1035 pool->base.clock_sources[DCE120_CLK_SRC_PLL2] = 1036 dce120_clock_source_create(ctx, ctx->dc_bios, 1037 CLOCK_SOURCE_COMBO_PHY_PLL2, 1038 &clk_src_regs[2], false); 1039 pool->base.clock_sources[DCE120_CLK_SRC_PLL3] = 1040 dce120_clock_source_create(ctx, ctx->dc_bios, 1041 CLOCK_SOURCE_COMBO_PHY_PLL3, 1042 &clk_src_regs[3], false); 1043 pool->base.clock_sources[DCE120_CLK_SRC_PLL4] = 1044 dce120_clock_source_create(ctx, ctx->dc_bios, 1045 CLOCK_SOURCE_COMBO_PHY_PLL4, 1046 &clk_src_regs[4], false); 1047 pool->base.clock_sources[DCE120_CLK_SRC_PLL5] = 1048 dce120_clock_source_create(ctx, ctx->dc_bios, 1049 CLOCK_SOURCE_COMBO_PHY_PLL5, 1050 &clk_src_regs[5], false); 1051 pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL; 1052 1053 pool->base.dp_clock_source = 1054 dce120_clock_source_create(ctx, ctx->dc_bios, 1055 CLOCK_SOURCE_ID_DP_DTO, 1056 &clk_src_regs[0], true); 1057 1058 for (i = 0; i < pool->base.clk_src_count; i++) { 1059 if (pool->base.clock_sources[i] == NULL) { 1060 dm_error("DC: failed to create clock sources!\n"); 1061 BREAK_TO_DEBUGGER(); 1062 goto clk_src_create_fail; 1063 } 1064 } 1065 1066 pool->base.dmcu = dce_dmcu_create(ctx, 1067 &dmcu_regs, 1068 &dmcu_shift, 1069 &dmcu_mask); 1070 if (pool->base.dmcu == NULL) { 1071 dm_error("DC: failed to create dmcu!\n"); 1072 BREAK_TO_DEBUGGER(); 1073 goto res_create_fail; 1074 } 1075 1076 pool->base.abm = dce_abm_create(ctx, 1077 &abm_regs, 1078 &abm_shift, 1079 &abm_mask); 1080 if (pool->base.abm == NULL) { 1081 dm_error("DC: failed to create abm!\n"); 1082 BREAK_TO_DEBUGGER(); 1083 goto res_create_fail; 1084 } 1085 1086 1087 irq_init_data.ctx = dc->ctx; 1088 pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data); 1089 if (!pool->base.irqs) 1090 goto irqs_create_fail; 1091 1092 /* VG20: Pipe harvesting enabled, retrieve valid pipe fuses */ 1093 if (is_vg20) 1094 pipe_fuses = read_pipe_fuses(ctx); 1095 1096 /* index to valid pipe resource */ 1097 j = 0; 1098 for (i = 0; i < pool->base.pipe_count; i++) { 1099 if (is_vg20) { 1100 if ((pipe_fuses & (1 << i)) != 0) { 1101 dm_error("DC: skip invalid pipe %d!\n", i); 1102 continue; 1103 } 1104 } 1105 1106 pool->base.timing_generators[j] = 1107 dce120_timing_generator_create( 1108 ctx, 1109 i, 1110 &dce120_tg_offsets[i]); 1111 if (pool->base.timing_generators[j] == NULL) { 1112 BREAK_TO_DEBUGGER(); 1113 dm_error("DC: failed to create tg!\n"); 1114 goto controller_create_fail; 1115 } 1116 1117 pool->base.mis[j] = dce120_mem_input_create(ctx, i); 1118 1119 if (pool->base.mis[j] == NULL) { 1120 BREAK_TO_DEBUGGER(); 1121 dm_error( 1122 "DC: failed to create memory input!\n"); 1123 goto controller_create_fail; 1124 } 1125 1126 pool->base.ipps[j] = dce120_ipp_create(ctx, i); 1127 if (pool->base.ipps[i] == NULL) { 1128 BREAK_TO_DEBUGGER(); 1129 dm_error( 1130 "DC: failed to create input pixel processor!\n"); 1131 goto controller_create_fail; 1132 } 1133 1134 pool->base.transforms[j] = dce120_transform_create(ctx, i); 1135 if (pool->base.transforms[i] == NULL) { 1136 BREAK_TO_DEBUGGER(); 1137 dm_error( 1138 "DC: failed to create transform!\n"); 1139 goto res_create_fail; 1140 } 1141 1142 pool->base.opps[j] = dce120_opp_create( 1143 ctx, 1144 i); 1145 if (pool->base.opps[j] == NULL) { 1146 BREAK_TO_DEBUGGER(); 1147 dm_error( 1148 "DC: failed to create output pixel processor!\n"); 1149 } 1150 1151 /* check next valid pipe */ 1152 j++; 1153 } 1154 1155 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1156 pool->base.engines[i] = dce120_aux_engine_create(ctx, i); 1157 if (pool->base.engines[i] == NULL) { 1158 BREAK_TO_DEBUGGER(); 1159 dm_error( 1160 "DC:failed to create aux engine!!\n"); 1161 goto res_create_fail; 1162 } 1163 pool->base.hw_i2cs[i] = dce120_i2c_hw_create(ctx, i); 1164 if (pool->base.hw_i2cs[i] == NULL) { 1165 BREAK_TO_DEBUGGER(); 1166 dm_error( 1167 "DC:failed to create i2c engine!!\n"); 1168 goto res_create_fail; 1169 } 1170 pool->base.sw_i2cs[i] = NULL; 1171 } 1172 1173 /* valid pipe num */ 1174 pool->base.pipe_count = j; 1175 pool->base.timing_generator_count = j; 1176 1177 if (is_vg20) 1178 res_funcs = &dce121_res_create_funcs; 1179 else 1180 res_funcs = &res_create_funcs; 1181 1182 if (!resource_construct(num_virtual_links, dc, &pool->base, res_funcs)) 1183 goto res_create_fail; 1184 1185 /* Create hardware sequencer */ 1186 if (!dce120_hw_sequencer_create(dc)) 1187 goto controller_create_fail; 1188 1189 dc->caps.max_planes = pool->base.pipe_count; 1190 1191 for (i = 0; i < dc->caps.max_planes; ++i) 1192 dc->caps.planes[i] = plane_cap; 1193 1194 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1195 1196 bw_calcs_data_update_from_pplib(dc); 1197 1198 return true; 1199 1200 irqs_create_fail: 1201 controller_create_fail: 1202 clk_src_create_fail: 1203 res_create_fail: 1204 1205 destruct(pool); 1206 1207 return false; 1208 } 1209 1210 struct resource_pool *dce120_create_resource_pool( 1211 uint8_t num_virtual_links, 1212 struct dc *dc) 1213 { 1214 struct dce110_resource_pool *pool = 1215 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1216 1217 if (!pool) 1218 return NULL; 1219 1220 if (construct(num_virtual_links, dc, pool)) 1221 return &pool->base; 1222 1223 kfree(pool); 1224 BREAK_TO_DEBUGGER(); 1225 return NULL; 1226 } 1227