1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc.cls 3 * 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 29 30 #include "stream_encoder.h" 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dce120_resource.h" 34 35 #include "dce112/dce112_resource.h" 36 37 #include "dce110/dce110_resource.h" 38 #include "../virtual/virtual_stream_encoder.h" 39 #include "dce120_timing_generator.h" 40 #include "irq/dce120/irq_service_dce120.h" 41 #include "dce/dce_opp.h" 42 #include "dce/dce_clock_source.h" 43 #include "dce/dce_ipp.h" 44 #include "dce/dce_mem_input.h" 45 46 #include "dce110/dce110_hw_sequencer.h" 47 #include "dce120/dce120_hw_sequencer.h" 48 #include "dce/dce_transform.h" 49 50 #include "dce/dce_clk_mgr.h" 51 #include "dce/dce_audio.h" 52 #include "dce/dce_link_encoder.h" 53 #include "dce/dce_stream_encoder.h" 54 #include "dce/dce_hwseq.h" 55 #include "dce/dce_abm.h" 56 #include "dce/dce_dmcu.h" 57 #include "dce/dce_aux.h" 58 #include "dce/dce_i2c.h" 59 60 #include "dce/dce_12_0_offset.h" 61 #include "dce/dce_12_0_sh_mask.h" 62 #include "soc15_hw_ip.h" 63 #include "vega10_ip_offset.h" 64 #include "nbio/nbio_6_1_offset.h" 65 #include "mmhub/mmhub_9_4_0_offset.h" 66 #include "mmhub/mmhub_9_4_0_sh_mask.h" 67 #include "reg_helper.h" 68 69 #include "dce100/dce100_resource.h" 70 71 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 72 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 73 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 74 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 75 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 76 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 77 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 78 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 79 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 80 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 81 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 82 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 83 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 84 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 85 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 86 #endif 87 88 enum dce120_clk_src_array_id { 89 DCE120_CLK_SRC_PLL0, 90 DCE120_CLK_SRC_PLL1, 91 DCE120_CLK_SRC_PLL2, 92 DCE120_CLK_SRC_PLL3, 93 DCE120_CLK_SRC_PLL4, 94 DCE120_CLK_SRC_PLL5, 95 96 DCE120_CLK_SRC_TOTAL 97 }; 98 99 static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = { 100 { 101 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 102 }, 103 { 104 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 105 }, 106 { 107 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 108 }, 109 { 110 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 111 }, 112 { 113 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 114 }, 115 { 116 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 117 } 118 }; 119 120 /* begin ********************* 121 * macros to expend register list macro defined in HW object header file */ 122 123 #define BASE_INNER(seg) \ 124 DCE_BASE__INST0_SEG ## seg 125 126 #define NBIO_BASE_INNER(seg) \ 127 NBIF_BASE__INST0_SEG ## seg 128 129 #define NBIO_BASE(seg) \ 130 NBIO_BASE_INNER(seg) 131 132 /* compile time expand base address. */ 133 #define BASE(seg) \ 134 BASE_INNER(seg) 135 136 #define SR(reg_name)\ 137 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 138 mm ## reg_name 139 140 #define SRI(reg_name, block, id)\ 141 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 142 mm ## block ## id ## _ ## reg_name 143 144 /* MMHUB */ 145 #define MMHUB_BASE_INNER(seg) \ 146 MMHUB_BASE__INST0_SEG ## seg 147 148 #define MMHUB_BASE(seg) \ 149 MMHUB_BASE_INNER(seg) 150 151 #define MMHUB_SR(reg_name)\ 152 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 153 mm ## reg_name 154 155 /* macros to expend register list macro defined in HW object header file 156 * end *********************/ 157 158 159 static const struct dce_dmcu_registers dmcu_regs = { 160 DMCU_DCE110_COMMON_REG_LIST() 161 }; 162 163 static const struct dce_dmcu_shift dmcu_shift = { 164 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 165 }; 166 167 static const struct dce_dmcu_mask dmcu_mask = { 168 DMCU_MASK_SH_LIST_DCE110(_MASK) 169 }; 170 171 static const struct dce_abm_registers abm_regs = { 172 ABM_DCE110_COMMON_REG_LIST() 173 }; 174 175 static const struct dce_abm_shift abm_shift = { 176 ABM_MASK_SH_LIST_DCE110(__SHIFT) 177 }; 178 179 static const struct dce_abm_mask abm_mask = { 180 ABM_MASK_SH_LIST_DCE110(_MASK) 181 }; 182 183 #define ipp_regs(id)\ 184 [id] = {\ 185 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 186 } 187 188 static const struct dce_ipp_registers ipp_regs[] = { 189 ipp_regs(0), 190 ipp_regs(1), 191 ipp_regs(2), 192 ipp_regs(3), 193 ipp_regs(4), 194 ipp_regs(5) 195 }; 196 197 static const struct dce_ipp_shift ipp_shift = { 198 IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT) 199 }; 200 201 static const struct dce_ipp_mask ipp_mask = { 202 IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK) 203 }; 204 205 #define transform_regs(id)\ 206 [id] = {\ 207 XFM_COMMON_REG_LIST_DCE110(id)\ 208 } 209 210 static const struct dce_transform_registers xfm_regs[] = { 211 transform_regs(0), 212 transform_regs(1), 213 transform_regs(2), 214 transform_regs(3), 215 transform_regs(4), 216 transform_regs(5) 217 }; 218 219 static const struct dce_transform_shift xfm_shift = { 220 XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT) 221 }; 222 223 static const struct dce_transform_mask xfm_mask = { 224 XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK) 225 }; 226 227 #define aux_regs(id)\ 228 [id] = {\ 229 AUX_REG_LIST(id)\ 230 } 231 232 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 233 aux_regs(0), 234 aux_regs(1), 235 aux_regs(2), 236 aux_regs(3), 237 aux_regs(4), 238 aux_regs(5) 239 }; 240 241 #define hpd_regs(id)\ 242 [id] = {\ 243 HPD_REG_LIST(id)\ 244 } 245 246 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 247 hpd_regs(0), 248 hpd_regs(1), 249 hpd_regs(2), 250 hpd_regs(3), 251 hpd_regs(4), 252 hpd_regs(5) 253 }; 254 255 #define link_regs(id)\ 256 [id] = {\ 257 LE_DCE120_REG_LIST(id), \ 258 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 259 } 260 261 static const struct dce110_link_enc_registers link_enc_regs[] = { 262 link_regs(0), 263 link_regs(1), 264 link_regs(2), 265 link_regs(3), 266 link_regs(4), 267 link_regs(5), 268 link_regs(6), 269 }; 270 271 272 #define stream_enc_regs(id)\ 273 [id] = {\ 274 SE_COMMON_REG_LIST(id),\ 275 .TMDS_CNTL = 0,\ 276 } 277 278 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 279 stream_enc_regs(0), 280 stream_enc_regs(1), 281 stream_enc_regs(2), 282 stream_enc_regs(3), 283 stream_enc_regs(4), 284 stream_enc_regs(5) 285 }; 286 287 static const struct dce_stream_encoder_shift se_shift = { 288 SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT) 289 }; 290 291 static const struct dce_stream_encoder_mask se_mask = { 292 SE_COMMON_MASK_SH_LIST_DCE120(_MASK) 293 }; 294 295 #define opp_regs(id)\ 296 [id] = {\ 297 OPP_DCE_120_REG_LIST(id),\ 298 } 299 300 static const struct dce_opp_registers opp_regs[] = { 301 opp_regs(0), 302 opp_regs(1), 303 opp_regs(2), 304 opp_regs(3), 305 opp_regs(4), 306 opp_regs(5) 307 }; 308 309 static const struct dce_opp_shift opp_shift = { 310 OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT) 311 }; 312 313 static const struct dce_opp_mask opp_mask = { 314 OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK) 315 }; 316 #define aux_engine_regs(id)\ 317 [id] = {\ 318 AUX_COMMON_REG_LIST(id), \ 319 .AUX_RESET_MASK = 0 \ 320 } 321 322 static const struct dce110_aux_registers aux_engine_regs[] = { 323 aux_engine_regs(0), 324 aux_engine_regs(1), 325 aux_engine_regs(2), 326 aux_engine_regs(3), 327 aux_engine_regs(4), 328 aux_engine_regs(5) 329 }; 330 331 #define audio_regs(id)\ 332 [id] = {\ 333 AUD_COMMON_REG_LIST(id)\ 334 } 335 336 static const struct dce_audio_registers audio_regs[] = { 337 audio_regs(0), 338 audio_regs(1), 339 audio_regs(2), 340 audio_regs(3), 341 audio_regs(4), 342 audio_regs(5) 343 }; 344 345 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 346 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 347 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 348 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 349 350 static const struct dce_audio_shift audio_shift = { 351 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 352 }; 353 354 static const struct dce_aduio_mask audio_mask = { 355 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 356 }; 357 358 #define clk_src_regs(index, id)\ 359 [index] = {\ 360 CS_COMMON_REG_LIST_DCE_112(id),\ 361 } 362 363 static const struct dce110_clk_src_regs clk_src_regs[] = { 364 clk_src_regs(0, A), 365 clk_src_regs(1, B), 366 clk_src_regs(2, C), 367 clk_src_regs(3, D), 368 clk_src_regs(4, E), 369 clk_src_regs(5, F) 370 }; 371 372 static const struct dce110_clk_src_shift cs_shift = { 373 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 374 }; 375 376 static const struct dce110_clk_src_mask cs_mask = { 377 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) 378 }; 379 380 struct output_pixel_processor *dce120_opp_create( 381 struct dc_context *ctx, 382 uint32_t inst) 383 { 384 struct dce110_opp *opp = 385 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 386 387 if (!opp) 388 return NULL; 389 390 dce110_opp_construct(opp, 391 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 392 return &opp->base; 393 } 394 struct dce_aux *dce120_aux_engine_create( 395 struct dc_context *ctx, 396 uint32_t inst) 397 { 398 struct aux_engine_dce110 *aux_engine = 399 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 400 401 if (!aux_engine) 402 return NULL; 403 404 dce110_aux_engine_construct(aux_engine, ctx, inst, 405 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 406 &aux_engine_regs[inst]); 407 408 return &aux_engine->base; 409 } 410 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 411 412 static const struct dce_i2c_registers i2c_hw_regs[] = { 413 i2c_inst_regs(1), 414 i2c_inst_regs(2), 415 i2c_inst_regs(3), 416 i2c_inst_regs(4), 417 i2c_inst_regs(5), 418 i2c_inst_regs(6), 419 }; 420 421 static const struct dce_i2c_shift i2c_shifts = { 422 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 423 }; 424 425 static const struct dce_i2c_mask i2c_masks = { 426 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 427 }; 428 429 struct dce_i2c_hw *dce120_i2c_hw_create( 430 struct dc_context *ctx, 431 uint32_t inst) 432 { 433 struct dce_i2c_hw *dce_i2c_hw = 434 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 435 436 if (!dce_i2c_hw) 437 return NULL; 438 439 dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst, 440 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 441 442 return dce_i2c_hw; 443 } 444 static const struct bios_registers bios_regs = { 445 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + NBIO_BASE(mmBIOS_SCRATCH_3_BASE_IDX), 446 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX) 447 }; 448 449 static const struct resource_caps res_cap = { 450 .num_timing_generator = 6, 451 .num_audio = 7, 452 .num_stream_encoder = 6, 453 .num_pll = 6, 454 .num_ddc = 6, 455 }; 456 457 static const struct dc_plane_cap plane_cap = { 458 .type = DC_PLANE_TYPE_DCE_RGB, 459 460 .pixel_format_support = { 461 .argb8888 = true, 462 .nv12 = false, 463 .fp16 = false 464 }, 465 466 .max_upscale_factor = { 467 .argb8888 = 16000, 468 .nv12 = 1, 469 .fp16 = 1 470 }, 471 472 .max_downscale_factor = { 473 .argb8888 = 250, 474 .nv12 = 1, 475 .fp16 = 1 476 } 477 }; 478 479 static const struct dc_debug_options debug_defaults = { 480 .disable_clock_gate = true, 481 }; 482 483 struct clock_source *dce120_clock_source_create( 484 struct dc_context *ctx, 485 struct dc_bios *bios, 486 enum clock_source_id id, 487 const struct dce110_clk_src_regs *regs, 488 bool dp_clk_src) 489 { 490 struct dce110_clk_src *clk_src = 491 kzalloc(sizeof(*clk_src), GFP_KERNEL); 492 493 if (!clk_src) 494 return NULL; 495 496 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 497 regs, &cs_shift, &cs_mask)) { 498 clk_src->base.dp_clk_src = dp_clk_src; 499 return &clk_src->base; 500 } 501 502 BREAK_TO_DEBUGGER(); 503 return NULL; 504 } 505 506 void dce120_clock_source_destroy(struct clock_source **clk_src) 507 { 508 kfree(TO_DCE110_CLK_SRC(*clk_src)); 509 *clk_src = NULL; 510 } 511 512 513 bool dce120_hw_sequencer_create(struct dc *dc) 514 { 515 /* All registers used by dce11.2 match those in dce11 in offset and 516 * structure 517 */ 518 dce120_hw_sequencer_construct(dc); 519 520 /*TODO Move to separate file and Override what is needed */ 521 522 return true; 523 } 524 525 static struct timing_generator *dce120_timing_generator_create( 526 struct dc_context *ctx, 527 uint32_t instance, 528 const struct dce110_timing_generator_offsets *offsets) 529 { 530 struct dce110_timing_generator *tg110 = 531 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 532 533 if (!tg110) 534 return NULL; 535 536 dce120_timing_generator_construct(tg110, ctx, instance, offsets); 537 return &tg110->base; 538 } 539 540 static void dce120_transform_destroy(struct transform **xfm) 541 { 542 kfree(TO_DCE_TRANSFORM(*xfm)); 543 *xfm = NULL; 544 } 545 546 static void destruct(struct dce110_resource_pool *pool) 547 { 548 unsigned int i; 549 550 for (i = 0; i < pool->base.pipe_count; i++) { 551 if (pool->base.opps[i] != NULL) 552 dce110_opp_destroy(&pool->base.opps[i]); 553 554 if (pool->base.transforms[i] != NULL) 555 dce120_transform_destroy(&pool->base.transforms[i]); 556 557 if (pool->base.ipps[i] != NULL) 558 dce_ipp_destroy(&pool->base.ipps[i]); 559 560 if (pool->base.mis[i] != NULL) { 561 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 562 pool->base.mis[i] = NULL; 563 } 564 565 if (pool->base.irqs != NULL) { 566 dal_irq_service_destroy(&pool->base.irqs); 567 } 568 569 if (pool->base.timing_generators[i] != NULL) { 570 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 571 pool->base.timing_generators[i] = NULL; 572 } 573 } 574 575 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 576 if (pool->base.engines[i] != NULL) 577 dce110_engine_destroy(&pool->base.engines[i]); 578 if (pool->base.hw_i2cs[i] != NULL) { 579 kfree(pool->base.hw_i2cs[i]); 580 pool->base.hw_i2cs[i] = NULL; 581 } 582 if (pool->base.sw_i2cs[i] != NULL) { 583 kfree(pool->base.sw_i2cs[i]); 584 pool->base.sw_i2cs[i] = NULL; 585 } 586 } 587 588 for (i = 0; i < pool->base.audio_count; i++) { 589 if (pool->base.audios[i]) 590 dce_aud_destroy(&pool->base.audios[i]); 591 } 592 593 for (i = 0; i < pool->base.stream_enc_count; i++) { 594 if (pool->base.stream_enc[i] != NULL) 595 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 596 } 597 598 for (i = 0; i < pool->base.clk_src_count; i++) { 599 if (pool->base.clock_sources[i] != NULL) 600 dce120_clock_source_destroy( 601 &pool->base.clock_sources[i]); 602 } 603 604 if (pool->base.dp_clock_source != NULL) 605 dce120_clock_source_destroy(&pool->base.dp_clock_source); 606 607 if (pool->base.abm != NULL) 608 dce_abm_destroy(&pool->base.abm); 609 610 if (pool->base.dmcu != NULL) 611 dce_dmcu_destroy(&pool->base.dmcu); 612 613 if (pool->base.clk_mgr != NULL) 614 dce_clk_mgr_destroy(&pool->base.clk_mgr); 615 } 616 617 static void read_dce_straps( 618 struct dc_context *ctx, 619 struct resource_straps *straps) 620 { 621 uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0); 622 623 straps->audio_stream_number = get_reg_field_value(reg_val, 624 CC_DC_MISC_STRAPS, 625 AUDIO_STREAM_NUMBER); 626 straps->hdmi_disable = get_reg_field_value(reg_val, 627 CC_DC_MISC_STRAPS, 628 HDMI_DISABLE); 629 630 reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0); 631 straps->dc_pinstraps_audio = get_reg_field_value(reg_val, 632 DC_PINSTRAPS, 633 DC_PINSTRAPS_AUDIO); 634 } 635 636 static struct audio *create_audio( 637 struct dc_context *ctx, unsigned int inst) 638 { 639 return dce_audio_create(ctx, inst, 640 &audio_regs[inst], &audio_shift, &audio_mask); 641 } 642 643 static const struct encoder_feature_support link_enc_feature = { 644 .max_hdmi_deep_color = COLOR_DEPTH_121212, 645 .max_hdmi_pixel_clock = 600000, 646 .hdmi_ycbcr420_supported = true, 647 .dp_ycbcr420_supported = false, 648 .flags.bits.IS_HBR2_CAPABLE = true, 649 .flags.bits.IS_HBR3_CAPABLE = true, 650 .flags.bits.IS_TPS3_CAPABLE = true, 651 .flags.bits.IS_TPS4_CAPABLE = true, 652 }; 653 654 static struct link_encoder *dce120_link_encoder_create( 655 const struct encoder_init_data *enc_init_data) 656 { 657 struct dce110_link_encoder *enc110 = 658 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 659 660 if (!enc110) 661 return NULL; 662 663 dce110_link_encoder_construct(enc110, 664 enc_init_data, 665 &link_enc_feature, 666 &link_enc_regs[enc_init_data->transmitter], 667 &link_enc_aux_regs[enc_init_data->channel - 1], 668 &link_enc_hpd_regs[enc_init_data->hpd_source]); 669 670 return &enc110->base; 671 } 672 673 static struct input_pixel_processor *dce120_ipp_create( 674 struct dc_context *ctx, uint32_t inst) 675 { 676 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 677 678 if (!ipp) { 679 BREAK_TO_DEBUGGER(); 680 return NULL; 681 } 682 683 dce_ipp_construct(ipp, ctx, inst, 684 &ipp_regs[inst], &ipp_shift, &ipp_mask); 685 return &ipp->base; 686 } 687 688 static struct stream_encoder *dce120_stream_encoder_create( 689 enum engine_id eng_id, 690 struct dc_context *ctx) 691 { 692 struct dce110_stream_encoder *enc110 = 693 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 694 695 if (!enc110) 696 return NULL; 697 698 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 699 &stream_enc_regs[eng_id], 700 &se_shift, &se_mask); 701 return &enc110->base; 702 } 703 704 #define SRII(reg_name, block, id)\ 705 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 706 mm ## block ## id ## _ ## reg_name 707 708 static const struct dce_hwseq_registers hwseq_reg = { 709 HWSEQ_DCE120_REG_LIST() 710 }; 711 712 static const struct dce_hwseq_shift hwseq_shift = { 713 HWSEQ_DCE12_MASK_SH_LIST(__SHIFT) 714 }; 715 716 static const struct dce_hwseq_mask hwseq_mask = { 717 HWSEQ_DCE12_MASK_SH_LIST(_MASK) 718 }; 719 720 /* HWSEQ regs for VG20 */ 721 static const struct dce_hwseq_registers dce121_hwseq_reg = { 722 HWSEQ_VG20_REG_LIST() 723 }; 724 725 static const struct dce_hwseq_shift dce121_hwseq_shift = { 726 HWSEQ_VG20_MASK_SH_LIST(__SHIFT) 727 }; 728 729 static const struct dce_hwseq_mask dce121_hwseq_mask = { 730 HWSEQ_VG20_MASK_SH_LIST(_MASK) 731 }; 732 733 static struct dce_hwseq *dce120_hwseq_create( 734 struct dc_context *ctx) 735 { 736 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 737 738 if (hws) { 739 hws->ctx = ctx; 740 hws->regs = &hwseq_reg; 741 hws->shifts = &hwseq_shift; 742 hws->masks = &hwseq_mask; 743 } 744 return hws; 745 } 746 747 static struct dce_hwseq *dce121_hwseq_create( 748 struct dc_context *ctx) 749 { 750 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 751 752 if (hws) { 753 hws->ctx = ctx; 754 hws->regs = &dce121_hwseq_reg; 755 hws->shifts = &dce121_hwseq_shift; 756 hws->masks = &dce121_hwseq_mask; 757 } 758 return hws; 759 } 760 761 static const struct resource_create_funcs res_create_funcs = { 762 .read_dce_straps = read_dce_straps, 763 .create_audio = create_audio, 764 .create_stream_encoder = dce120_stream_encoder_create, 765 .create_hwseq = dce120_hwseq_create, 766 }; 767 768 static const struct resource_create_funcs dce121_res_create_funcs = { 769 .read_dce_straps = read_dce_straps, 770 .create_audio = create_audio, 771 .create_stream_encoder = dce120_stream_encoder_create, 772 .create_hwseq = dce121_hwseq_create, 773 }; 774 775 776 #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) } 777 static const struct dce_mem_input_registers mi_regs[] = { 778 mi_inst_regs(0), 779 mi_inst_regs(1), 780 mi_inst_regs(2), 781 mi_inst_regs(3), 782 mi_inst_regs(4), 783 mi_inst_regs(5), 784 }; 785 786 static const struct dce_mem_input_shift mi_shifts = { 787 MI_DCE12_MASK_SH_LIST(__SHIFT) 788 }; 789 790 static const struct dce_mem_input_mask mi_masks = { 791 MI_DCE12_MASK_SH_LIST(_MASK) 792 }; 793 794 static struct mem_input *dce120_mem_input_create( 795 struct dc_context *ctx, 796 uint32_t inst) 797 { 798 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 799 GFP_KERNEL); 800 801 if (!dce_mi) { 802 BREAK_TO_DEBUGGER(); 803 return NULL; 804 } 805 806 dce120_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 807 return &dce_mi->base; 808 } 809 810 static struct transform *dce120_transform_create( 811 struct dc_context *ctx, 812 uint32_t inst) 813 { 814 struct dce_transform *transform = 815 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 816 817 if (!transform) 818 return NULL; 819 820 dce_transform_construct(transform, ctx, inst, 821 &xfm_regs[inst], &xfm_shift, &xfm_mask); 822 transform->lb_memory_size = 0x1404; /*5124*/ 823 return &transform->base; 824 } 825 826 static void dce120_destroy_resource_pool(struct resource_pool **pool) 827 { 828 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 829 830 destruct(dce110_pool); 831 kfree(dce110_pool); 832 *pool = NULL; 833 } 834 835 static const struct resource_funcs dce120_res_pool_funcs = { 836 .destroy = dce120_destroy_resource_pool, 837 .link_enc_create = dce120_link_encoder_create, 838 .validate_bandwidth = dce112_validate_bandwidth, 839 .validate_plane = dce100_validate_plane, 840 .add_stream_to_ctx = dce112_add_stream_to_ctx 841 }; 842 843 static void bw_calcs_data_update_from_pplib(struct dc *dc) 844 { 845 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 846 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 847 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; 848 int i; 849 unsigned int clk; 850 unsigned int latency; 851 852 /*do system clock*/ 853 if (!dm_pp_get_clock_levels_by_type_with_latency( 854 dc->ctx, 855 DM_PP_CLOCK_TYPE_ENGINE_CLK, 856 &eng_clks) || eng_clks.num_levels == 0) { 857 858 eng_clks.num_levels = 8; 859 clk = 300000; 860 861 for (i = 0; i < eng_clks.num_levels; i++) { 862 eng_clks.data[i].clocks_in_khz = clk; 863 clk += 100000; 864 } 865 } 866 867 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ 868 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 869 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); 870 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 871 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); 872 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 873 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); 874 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 875 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); 876 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 877 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); 878 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 879 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); 880 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 881 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); 882 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 883 eng_clks.data[0].clocks_in_khz, 1000); 884 885 /*do memory clock*/ 886 if (!dm_pp_get_clock_levels_by_type_with_latency( 887 dc->ctx, 888 DM_PP_CLOCK_TYPE_MEMORY_CLK, 889 &mem_clks) || mem_clks.num_levels == 0) { 890 891 mem_clks.num_levels = 3; 892 clk = 250000; 893 latency = 45; 894 895 for (i = 0; i < eng_clks.num_levels; i++) { 896 mem_clks.data[i].clocks_in_khz = clk; 897 mem_clks.data[i].latency_in_us = latency; 898 clk += 500000; 899 latency -= 5; 900 } 901 902 } 903 904 /* we don't need to call PPLIB for validation clock since they 905 * also give us the highest sclk and highest mclk (UMA clock). 906 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): 907 * YCLK = UMACLK*m_memoryTypeMultiplier 908 */ 909 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 910 mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 1000); 911 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 912 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 913 1000); 914 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 915 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 916 1000); 917 918 /* Now notify PPLib/SMU about which Watermarks sets they should select 919 * depending on DPM state they are in. And update BW MGR GFX Engine and 920 * Memory clock member variables for Watermarks calculations for each 921 * Watermark Set 922 */ 923 clk_ranges.num_wm_sets = 4; 924 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; 925 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = 926 eng_clks.data[0].clocks_in_khz; 927 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = 928 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 929 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz = 930 mem_clks.data[0].clocks_in_khz; 931 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = 932 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 933 934 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; 935 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = 936 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 937 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 938 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; 939 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz = 940 mem_clks.data[0].clocks_in_khz; 941 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = 942 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 943 944 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; 945 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = 946 eng_clks.data[0].clocks_in_khz; 947 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = 948 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 949 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz = 950 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 951 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 952 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; 953 954 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; 955 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = 956 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 957 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 958 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; 959 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz = 960 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 961 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 962 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; 963 964 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 965 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); 966 } 967 968 static uint32_t read_pipe_fuses(struct dc_context *ctx) 969 { 970 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); 971 /* VG20 support max 6 pipes */ 972 value = value & 0x3f; 973 return value; 974 } 975 976 static bool construct( 977 uint8_t num_virtual_links, 978 struct dc *dc, 979 struct dce110_resource_pool *pool) 980 { 981 unsigned int i; 982 int j; 983 struct dc_context *ctx = dc->ctx; 984 struct irq_service_init_data irq_init_data; 985 static const struct resource_create_funcs *res_funcs; 986 bool is_vg20 = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev); 987 uint32_t pipe_fuses; 988 989 ctx->dc_bios->regs = &bios_regs; 990 991 pool->base.res_cap = &res_cap; 992 pool->base.funcs = &dce120_res_pool_funcs; 993 994 /* TODO: Fill more data from GreenlandAsicCapability.cpp */ 995 pool->base.pipe_count = res_cap.num_timing_generator; 996 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 997 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 998 999 dc->caps.max_downscale_ratio = 200; 1000 dc->caps.i2c_speed_in_khz = 100; 1001 dc->caps.max_cursor_size = 128; 1002 dc->caps.dual_link_dvi = true; 1003 dc->caps.psp_setup_panel_mode = true; 1004 1005 dc->debug = debug_defaults; 1006 1007 /************************************************* 1008 * Create resources * 1009 *************************************************/ 1010 1011 pool->base.clock_sources[DCE120_CLK_SRC_PLL0] = 1012 dce120_clock_source_create(ctx, ctx->dc_bios, 1013 CLOCK_SOURCE_COMBO_PHY_PLL0, 1014 &clk_src_regs[0], false); 1015 pool->base.clock_sources[DCE120_CLK_SRC_PLL1] = 1016 dce120_clock_source_create(ctx, ctx->dc_bios, 1017 CLOCK_SOURCE_COMBO_PHY_PLL1, 1018 &clk_src_regs[1], false); 1019 pool->base.clock_sources[DCE120_CLK_SRC_PLL2] = 1020 dce120_clock_source_create(ctx, ctx->dc_bios, 1021 CLOCK_SOURCE_COMBO_PHY_PLL2, 1022 &clk_src_regs[2], false); 1023 pool->base.clock_sources[DCE120_CLK_SRC_PLL3] = 1024 dce120_clock_source_create(ctx, ctx->dc_bios, 1025 CLOCK_SOURCE_COMBO_PHY_PLL3, 1026 &clk_src_regs[3], false); 1027 pool->base.clock_sources[DCE120_CLK_SRC_PLL4] = 1028 dce120_clock_source_create(ctx, ctx->dc_bios, 1029 CLOCK_SOURCE_COMBO_PHY_PLL4, 1030 &clk_src_regs[4], false); 1031 pool->base.clock_sources[DCE120_CLK_SRC_PLL5] = 1032 dce120_clock_source_create(ctx, ctx->dc_bios, 1033 CLOCK_SOURCE_COMBO_PHY_PLL5, 1034 &clk_src_regs[5], false); 1035 pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL; 1036 1037 pool->base.dp_clock_source = 1038 dce120_clock_source_create(ctx, ctx->dc_bios, 1039 CLOCK_SOURCE_ID_DP_DTO, 1040 &clk_src_regs[0], true); 1041 1042 for (i = 0; i < pool->base.clk_src_count; i++) { 1043 if (pool->base.clock_sources[i] == NULL) { 1044 dm_error("DC: failed to create clock sources!\n"); 1045 BREAK_TO_DEBUGGER(); 1046 goto clk_src_create_fail; 1047 } 1048 } 1049 1050 if (is_vg20) 1051 pool->base.clk_mgr = dce121_clk_mgr_create(ctx); 1052 else 1053 pool->base.clk_mgr = dce120_clk_mgr_create(ctx); 1054 1055 if (pool->base.clk_mgr == NULL) { 1056 dm_error("DC: failed to create display clock!\n"); 1057 BREAK_TO_DEBUGGER(); 1058 goto dccg_create_fail; 1059 } 1060 1061 pool->base.dmcu = dce_dmcu_create(ctx, 1062 &dmcu_regs, 1063 &dmcu_shift, 1064 &dmcu_mask); 1065 if (pool->base.dmcu == NULL) { 1066 dm_error("DC: failed to create dmcu!\n"); 1067 BREAK_TO_DEBUGGER(); 1068 goto res_create_fail; 1069 } 1070 1071 pool->base.abm = dce_abm_create(ctx, 1072 &abm_regs, 1073 &abm_shift, 1074 &abm_mask); 1075 if (pool->base.abm == NULL) { 1076 dm_error("DC: failed to create abm!\n"); 1077 BREAK_TO_DEBUGGER(); 1078 goto res_create_fail; 1079 } 1080 1081 1082 irq_init_data.ctx = dc->ctx; 1083 pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data); 1084 if (!pool->base.irqs) 1085 goto irqs_create_fail; 1086 1087 /* VG20: Pipe harvesting enabled, retrieve valid pipe fuses */ 1088 if (is_vg20) 1089 pipe_fuses = read_pipe_fuses(ctx); 1090 1091 /* index to valid pipe resource */ 1092 j = 0; 1093 for (i = 0; i < pool->base.pipe_count; i++) { 1094 if (is_vg20) { 1095 if ((pipe_fuses & (1 << i)) != 0) { 1096 dm_error("DC: skip invalid pipe %d!\n", i); 1097 continue; 1098 } 1099 } 1100 1101 pool->base.timing_generators[j] = 1102 dce120_timing_generator_create( 1103 ctx, 1104 i, 1105 &dce120_tg_offsets[i]); 1106 if (pool->base.timing_generators[j] == NULL) { 1107 BREAK_TO_DEBUGGER(); 1108 dm_error("DC: failed to create tg!\n"); 1109 goto controller_create_fail; 1110 } 1111 1112 pool->base.mis[j] = dce120_mem_input_create(ctx, i); 1113 1114 if (pool->base.mis[j] == NULL) { 1115 BREAK_TO_DEBUGGER(); 1116 dm_error( 1117 "DC: failed to create memory input!\n"); 1118 goto controller_create_fail; 1119 } 1120 1121 pool->base.ipps[j] = dce120_ipp_create(ctx, i); 1122 if (pool->base.ipps[i] == NULL) { 1123 BREAK_TO_DEBUGGER(); 1124 dm_error( 1125 "DC: failed to create input pixel processor!\n"); 1126 goto controller_create_fail; 1127 } 1128 1129 pool->base.transforms[j] = dce120_transform_create(ctx, i); 1130 if (pool->base.transforms[i] == NULL) { 1131 BREAK_TO_DEBUGGER(); 1132 dm_error( 1133 "DC: failed to create transform!\n"); 1134 goto res_create_fail; 1135 } 1136 1137 pool->base.opps[j] = dce120_opp_create( 1138 ctx, 1139 i); 1140 if (pool->base.opps[j] == NULL) { 1141 BREAK_TO_DEBUGGER(); 1142 dm_error( 1143 "DC: failed to create output pixel processor!\n"); 1144 } 1145 1146 /* check next valid pipe */ 1147 j++; 1148 } 1149 1150 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1151 pool->base.engines[i] = dce120_aux_engine_create(ctx, i); 1152 if (pool->base.engines[i] == NULL) { 1153 BREAK_TO_DEBUGGER(); 1154 dm_error( 1155 "DC:failed to create aux engine!!\n"); 1156 goto res_create_fail; 1157 } 1158 pool->base.hw_i2cs[i] = dce120_i2c_hw_create(ctx, i); 1159 if (pool->base.hw_i2cs[i] == NULL) { 1160 BREAK_TO_DEBUGGER(); 1161 dm_error( 1162 "DC:failed to create i2c engine!!\n"); 1163 goto res_create_fail; 1164 } 1165 pool->base.sw_i2cs[i] = NULL; 1166 } 1167 1168 /* valid pipe num */ 1169 pool->base.pipe_count = j; 1170 pool->base.timing_generator_count = j; 1171 1172 if (is_vg20) 1173 res_funcs = &dce121_res_create_funcs; 1174 else 1175 res_funcs = &res_create_funcs; 1176 1177 if (!resource_construct(num_virtual_links, dc, &pool->base, res_funcs)) 1178 goto res_create_fail; 1179 1180 /* 1181 * This is a bit of a hack. The xGMI enabled info is used to determine 1182 * if audio and display clocks need to be adjusted with the WAFL link's 1183 * SS info. This is a responsiblity of the clk_mgr. But since MMHUB is 1184 * under hwseq, and the relevant register is in MMHUB, we have to do it 1185 * here. 1186 */ 1187 if (is_vg20 && dce121_xgmi_enabled(dc->hwseq)) 1188 dce121_clock_patch_xgmi_ss_info(pool->base.clk_mgr); 1189 1190 /* Create hardware sequencer */ 1191 if (!dce120_hw_sequencer_create(dc)) 1192 goto controller_create_fail; 1193 1194 dc->caps.max_planes = pool->base.pipe_count; 1195 1196 for (i = 0; i < dc->caps.max_planes; ++i) 1197 dc->caps.planes[i] = plane_cap; 1198 1199 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1200 1201 bw_calcs_data_update_from_pplib(dc); 1202 1203 return true; 1204 1205 irqs_create_fail: 1206 controller_create_fail: 1207 dccg_create_fail: 1208 clk_src_create_fail: 1209 res_create_fail: 1210 1211 destruct(pool); 1212 1213 return false; 1214 } 1215 1216 struct resource_pool *dce120_create_resource_pool( 1217 uint8_t num_virtual_links, 1218 struct dc *dc) 1219 { 1220 struct dce110_resource_pool *pool = 1221 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1222 1223 if (!pool) 1224 return NULL; 1225 1226 if (construct(num_virtual_links, dc, pool)) 1227 return &pool->base; 1228 1229 BREAK_TO_DEBUGGER(); 1230 return NULL; 1231 } 1232