1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc.cls 3 * 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 29 30 #include "stream_encoder.h" 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dce120_resource.h" 34 35 #include "dce112/dce112_resource.h" 36 37 #include "dce110/dce110_resource.h" 38 #include "../virtual/virtual_stream_encoder.h" 39 #include "dce120_timing_generator.h" 40 #include "irq/dce120/irq_service_dce120.h" 41 #include "dce/dce_opp.h" 42 #include "dce/dce_clock_source.h" 43 #include "dce/dce_ipp.h" 44 #include "dce/dce_mem_input.h" 45 46 #include "dce110/dce110_hw_sequencer.h" 47 #include "dce120/dce120_hw_sequencer.h" 48 #include "dce/dce_transform.h" 49 50 #include "dce/dce_clk_mgr.h" 51 #include "dce/dce_audio.h" 52 #include "dce/dce_link_encoder.h" 53 #include "dce/dce_stream_encoder.h" 54 #include "dce/dce_hwseq.h" 55 #include "dce/dce_abm.h" 56 #include "dce/dce_dmcu.h" 57 #include "dce/dce_aux.h" 58 #include "dce/dce_i2c.h" 59 60 #include "dce/dce_12_0_offset.h" 61 #include "dce/dce_12_0_sh_mask.h" 62 #include "soc15_hw_ip.h" 63 #include "vega10_ip_offset.h" 64 #include "nbio/nbio_6_1_offset.h" 65 #include "mmhub/mmhub_9_4_0_offset.h" 66 #include "mmhub/mmhub_9_4_0_sh_mask.h" 67 #include "reg_helper.h" 68 69 #include "dce100/dce100_resource.h" 70 71 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 72 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 73 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 74 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 75 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 76 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 77 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 78 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 79 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 80 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 81 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 82 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 83 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 84 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 85 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 86 #endif 87 88 enum dce120_clk_src_array_id { 89 DCE120_CLK_SRC_PLL0, 90 DCE120_CLK_SRC_PLL1, 91 DCE120_CLK_SRC_PLL2, 92 DCE120_CLK_SRC_PLL3, 93 DCE120_CLK_SRC_PLL4, 94 DCE120_CLK_SRC_PLL5, 95 96 DCE120_CLK_SRC_TOTAL 97 }; 98 99 static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = { 100 { 101 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 102 }, 103 { 104 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 105 }, 106 { 107 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 108 }, 109 { 110 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 111 }, 112 { 113 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 114 }, 115 { 116 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL), 117 } 118 }; 119 120 /* begin ********************* 121 * macros to expend register list macro defined in HW object header file */ 122 123 #define BASE_INNER(seg) \ 124 DCE_BASE__INST0_SEG ## seg 125 126 #define NBIO_BASE_INNER(seg) \ 127 NBIF_BASE__INST0_SEG ## seg 128 129 #define NBIO_BASE(seg) \ 130 NBIO_BASE_INNER(seg) 131 132 /* compile time expand base address. */ 133 #define BASE(seg) \ 134 BASE_INNER(seg) 135 136 #define SR(reg_name)\ 137 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 138 mm ## reg_name 139 140 #define SRI(reg_name, block, id)\ 141 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 142 mm ## block ## id ## _ ## reg_name 143 144 /* MMHUB */ 145 #define MMHUB_BASE_INNER(seg) \ 146 MMHUB_BASE__INST0_SEG ## seg 147 148 #define MMHUB_BASE(seg) \ 149 MMHUB_BASE_INNER(seg) 150 151 #define MMHUB_SR(reg_name)\ 152 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 153 mm ## reg_name 154 155 /* macros to expend register list macro defined in HW object header file 156 * end *********************/ 157 158 159 static const struct dce_dmcu_registers dmcu_regs = { 160 DMCU_DCE110_COMMON_REG_LIST() 161 }; 162 163 static const struct dce_dmcu_shift dmcu_shift = { 164 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 165 }; 166 167 static const struct dce_dmcu_mask dmcu_mask = { 168 DMCU_MASK_SH_LIST_DCE110(_MASK) 169 }; 170 171 static const struct dce_abm_registers abm_regs = { 172 ABM_DCE110_COMMON_REG_LIST() 173 }; 174 175 static const struct dce_abm_shift abm_shift = { 176 ABM_MASK_SH_LIST_DCE110(__SHIFT) 177 }; 178 179 static const struct dce_abm_mask abm_mask = { 180 ABM_MASK_SH_LIST_DCE110(_MASK) 181 }; 182 183 #define ipp_regs(id)\ 184 [id] = {\ 185 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 186 } 187 188 static const struct dce_ipp_registers ipp_regs[] = { 189 ipp_regs(0), 190 ipp_regs(1), 191 ipp_regs(2), 192 ipp_regs(3), 193 ipp_regs(4), 194 ipp_regs(5) 195 }; 196 197 static const struct dce_ipp_shift ipp_shift = { 198 IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT) 199 }; 200 201 static const struct dce_ipp_mask ipp_mask = { 202 IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK) 203 }; 204 205 #define transform_regs(id)\ 206 [id] = {\ 207 XFM_COMMON_REG_LIST_DCE110(id)\ 208 } 209 210 static const struct dce_transform_registers xfm_regs[] = { 211 transform_regs(0), 212 transform_regs(1), 213 transform_regs(2), 214 transform_regs(3), 215 transform_regs(4), 216 transform_regs(5) 217 }; 218 219 static const struct dce_transform_shift xfm_shift = { 220 XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT) 221 }; 222 223 static const struct dce_transform_mask xfm_mask = { 224 XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK) 225 }; 226 227 #define aux_regs(id)\ 228 [id] = {\ 229 AUX_REG_LIST(id)\ 230 } 231 232 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 233 aux_regs(0), 234 aux_regs(1), 235 aux_regs(2), 236 aux_regs(3), 237 aux_regs(4), 238 aux_regs(5) 239 }; 240 241 #define hpd_regs(id)\ 242 [id] = {\ 243 HPD_REG_LIST(id)\ 244 } 245 246 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 247 hpd_regs(0), 248 hpd_regs(1), 249 hpd_regs(2), 250 hpd_regs(3), 251 hpd_regs(4), 252 hpd_regs(5) 253 }; 254 255 #define link_regs(id)\ 256 [id] = {\ 257 LE_DCE120_REG_LIST(id), \ 258 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 259 } 260 261 static const struct dce110_link_enc_registers link_enc_regs[] = { 262 link_regs(0), 263 link_regs(1), 264 link_regs(2), 265 link_regs(3), 266 link_regs(4), 267 link_regs(5), 268 link_regs(6), 269 }; 270 271 272 #define stream_enc_regs(id)\ 273 [id] = {\ 274 SE_COMMON_REG_LIST(id),\ 275 .TMDS_CNTL = 0,\ 276 } 277 278 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 279 stream_enc_regs(0), 280 stream_enc_regs(1), 281 stream_enc_regs(2), 282 stream_enc_regs(3), 283 stream_enc_regs(4), 284 stream_enc_regs(5) 285 }; 286 287 static const struct dce_stream_encoder_shift se_shift = { 288 SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT) 289 }; 290 291 static const struct dce_stream_encoder_mask se_mask = { 292 SE_COMMON_MASK_SH_LIST_DCE120(_MASK) 293 }; 294 295 #define opp_regs(id)\ 296 [id] = {\ 297 OPP_DCE_120_REG_LIST(id),\ 298 } 299 300 static const struct dce_opp_registers opp_regs[] = { 301 opp_regs(0), 302 opp_regs(1), 303 opp_regs(2), 304 opp_regs(3), 305 opp_regs(4), 306 opp_regs(5) 307 }; 308 309 static const struct dce_opp_shift opp_shift = { 310 OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT) 311 }; 312 313 static const struct dce_opp_mask opp_mask = { 314 OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK) 315 }; 316 #define aux_engine_regs(id)\ 317 [id] = {\ 318 AUX_COMMON_REG_LIST(id), \ 319 .AUX_RESET_MASK = 0 \ 320 } 321 322 static const struct dce110_aux_registers aux_engine_regs[] = { 323 aux_engine_regs(0), 324 aux_engine_regs(1), 325 aux_engine_regs(2), 326 aux_engine_regs(3), 327 aux_engine_regs(4), 328 aux_engine_regs(5) 329 }; 330 331 #define audio_regs(id)\ 332 [id] = {\ 333 AUD_COMMON_REG_LIST(id)\ 334 } 335 336 static const struct dce_audio_registers audio_regs[] = { 337 audio_regs(0), 338 audio_regs(1), 339 audio_regs(2), 340 audio_regs(3), 341 audio_regs(4), 342 audio_regs(5) 343 }; 344 345 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 346 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 347 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 348 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 349 350 static const struct dce_audio_shift audio_shift = { 351 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 352 }; 353 354 static const struct dce_aduio_mask audio_mask = { 355 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 356 }; 357 358 #define clk_src_regs(index, id)\ 359 [index] = {\ 360 CS_COMMON_REG_LIST_DCE_112(id),\ 361 } 362 363 static const struct dce110_clk_src_regs clk_src_regs[] = { 364 clk_src_regs(0, A), 365 clk_src_regs(1, B), 366 clk_src_regs(2, C), 367 clk_src_regs(3, D), 368 clk_src_regs(4, E), 369 clk_src_regs(5, F) 370 }; 371 372 static const struct dce110_clk_src_shift cs_shift = { 373 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 374 }; 375 376 static const struct dce110_clk_src_mask cs_mask = { 377 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) 378 }; 379 380 struct output_pixel_processor *dce120_opp_create( 381 struct dc_context *ctx, 382 uint32_t inst) 383 { 384 struct dce110_opp *opp = 385 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 386 387 if (!opp) 388 return NULL; 389 390 dce110_opp_construct(opp, 391 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 392 return &opp->base; 393 } 394 struct dce_aux *dce120_aux_engine_create( 395 struct dc_context *ctx, 396 uint32_t inst) 397 { 398 struct aux_engine_dce110 *aux_engine = 399 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 400 401 if (!aux_engine) 402 return NULL; 403 404 dce110_aux_engine_construct(aux_engine, ctx, inst, 405 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 406 &aux_engine_regs[inst]); 407 408 return &aux_engine->base; 409 } 410 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 411 412 static const struct dce_i2c_registers i2c_hw_regs[] = { 413 i2c_inst_regs(1), 414 i2c_inst_regs(2), 415 i2c_inst_regs(3), 416 i2c_inst_regs(4), 417 i2c_inst_regs(5), 418 i2c_inst_regs(6), 419 }; 420 421 static const struct dce_i2c_shift i2c_shifts = { 422 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 423 }; 424 425 static const struct dce_i2c_mask i2c_masks = { 426 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 427 }; 428 429 struct dce_i2c_hw *dce120_i2c_hw_create( 430 struct dc_context *ctx, 431 uint32_t inst) 432 { 433 struct dce_i2c_hw *dce_i2c_hw = 434 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 435 436 if (!dce_i2c_hw) 437 return NULL; 438 439 dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst, 440 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 441 442 return dce_i2c_hw; 443 } 444 static const struct bios_registers bios_regs = { 445 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + NBIO_BASE(mmBIOS_SCRATCH_3_BASE_IDX), 446 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX) 447 }; 448 449 static const struct resource_caps res_cap = { 450 .num_timing_generator = 6, 451 .num_audio = 7, 452 .num_stream_encoder = 6, 453 .num_pll = 6, 454 .num_ddc = 6, 455 }; 456 457 static const struct dc_debug_options debug_defaults = { 458 .disable_clock_gate = true, 459 }; 460 461 struct clock_source *dce120_clock_source_create( 462 struct dc_context *ctx, 463 struct dc_bios *bios, 464 enum clock_source_id id, 465 const struct dce110_clk_src_regs *regs, 466 bool dp_clk_src) 467 { 468 struct dce110_clk_src *clk_src = 469 kzalloc(sizeof(*clk_src), GFP_KERNEL); 470 471 if (!clk_src) 472 return NULL; 473 474 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 475 regs, &cs_shift, &cs_mask)) { 476 clk_src->base.dp_clk_src = dp_clk_src; 477 return &clk_src->base; 478 } 479 480 BREAK_TO_DEBUGGER(); 481 return NULL; 482 } 483 484 void dce120_clock_source_destroy(struct clock_source **clk_src) 485 { 486 kfree(TO_DCE110_CLK_SRC(*clk_src)); 487 *clk_src = NULL; 488 } 489 490 491 bool dce120_hw_sequencer_create(struct dc *dc) 492 { 493 /* All registers used by dce11.2 match those in dce11 in offset and 494 * structure 495 */ 496 dce120_hw_sequencer_construct(dc); 497 498 /*TODO Move to separate file and Override what is needed */ 499 500 return true; 501 } 502 503 static struct timing_generator *dce120_timing_generator_create( 504 struct dc_context *ctx, 505 uint32_t instance, 506 const struct dce110_timing_generator_offsets *offsets) 507 { 508 struct dce110_timing_generator *tg110 = 509 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 510 511 if (!tg110) 512 return NULL; 513 514 dce120_timing_generator_construct(tg110, ctx, instance, offsets); 515 return &tg110->base; 516 } 517 518 static void dce120_transform_destroy(struct transform **xfm) 519 { 520 kfree(TO_DCE_TRANSFORM(*xfm)); 521 *xfm = NULL; 522 } 523 524 static void destruct(struct dce110_resource_pool *pool) 525 { 526 unsigned int i; 527 528 for (i = 0; i < pool->base.pipe_count; i++) { 529 if (pool->base.opps[i] != NULL) 530 dce110_opp_destroy(&pool->base.opps[i]); 531 532 if (pool->base.transforms[i] != NULL) 533 dce120_transform_destroy(&pool->base.transforms[i]); 534 535 if (pool->base.ipps[i] != NULL) 536 dce_ipp_destroy(&pool->base.ipps[i]); 537 538 if (pool->base.mis[i] != NULL) { 539 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 540 pool->base.mis[i] = NULL; 541 } 542 543 if (pool->base.irqs != NULL) { 544 dal_irq_service_destroy(&pool->base.irqs); 545 } 546 547 if (pool->base.timing_generators[i] != NULL) { 548 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 549 pool->base.timing_generators[i] = NULL; 550 } 551 } 552 553 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 554 if (pool->base.engines[i] != NULL) 555 dce110_engine_destroy(&pool->base.engines[i]); 556 if (pool->base.hw_i2cs[i] != NULL) { 557 kfree(pool->base.hw_i2cs[i]); 558 pool->base.hw_i2cs[i] = NULL; 559 } 560 if (pool->base.sw_i2cs[i] != NULL) { 561 kfree(pool->base.sw_i2cs[i]); 562 pool->base.sw_i2cs[i] = NULL; 563 } 564 } 565 566 for (i = 0; i < pool->base.audio_count; i++) { 567 if (pool->base.audios[i]) 568 dce_aud_destroy(&pool->base.audios[i]); 569 } 570 571 for (i = 0; i < pool->base.stream_enc_count; i++) { 572 if (pool->base.stream_enc[i] != NULL) 573 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 574 } 575 576 for (i = 0; i < pool->base.clk_src_count; i++) { 577 if (pool->base.clock_sources[i] != NULL) 578 dce120_clock_source_destroy( 579 &pool->base.clock_sources[i]); 580 } 581 582 if (pool->base.dp_clock_source != NULL) 583 dce120_clock_source_destroy(&pool->base.dp_clock_source); 584 585 if (pool->base.abm != NULL) 586 dce_abm_destroy(&pool->base.abm); 587 588 if (pool->base.dmcu != NULL) 589 dce_dmcu_destroy(&pool->base.dmcu); 590 591 if (pool->base.clk_mgr != NULL) 592 dce_clk_mgr_destroy(&pool->base.clk_mgr); 593 } 594 595 static void read_dce_straps( 596 struct dc_context *ctx, 597 struct resource_straps *straps) 598 { 599 uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0); 600 601 straps->audio_stream_number = get_reg_field_value(reg_val, 602 CC_DC_MISC_STRAPS, 603 AUDIO_STREAM_NUMBER); 604 straps->hdmi_disable = get_reg_field_value(reg_val, 605 CC_DC_MISC_STRAPS, 606 HDMI_DISABLE); 607 608 reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0); 609 straps->dc_pinstraps_audio = get_reg_field_value(reg_val, 610 DC_PINSTRAPS, 611 DC_PINSTRAPS_AUDIO); 612 } 613 614 static struct audio *create_audio( 615 struct dc_context *ctx, unsigned int inst) 616 { 617 return dce_audio_create(ctx, inst, 618 &audio_regs[inst], &audio_shift, &audio_mask); 619 } 620 621 static const struct encoder_feature_support link_enc_feature = { 622 .max_hdmi_deep_color = COLOR_DEPTH_121212, 623 .max_hdmi_pixel_clock = 600000, 624 .hdmi_ycbcr420_supported = true, 625 .dp_ycbcr420_supported = false, 626 .flags.bits.IS_HBR2_CAPABLE = true, 627 .flags.bits.IS_HBR3_CAPABLE = true, 628 .flags.bits.IS_TPS3_CAPABLE = true, 629 .flags.bits.IS_TPS4_CAPABLE = true, 630 }; 631 632 static struct link_encoder *dce120_link_encoder_create( 633 const struct encoder_init_data *enc_init_data) 634 { 635 struct dce110_link_encoder *enc110 = 636 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 637 638 if (!enc110) 639 return NULL; 640 641 dce110_link_encoder_construct(enc110, 642 enc_init_data, 643 &link_enc_feature, 644 &link_enc_regs[enc_init_data->transmitter], 645 &link_enc_aux_regs[enc_init_data->channel - 1], 646 &link_enc_hpd_regs[enc_init_data->hpd_source]); 647 648 return &enc110->base; 649 } 650 651 static struct input_pixel_processor *dce120_ipp_create( 652 struct dc_context *ctx, uint32_t inst) 653 { 654 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 655 656 if (!ipp) { 657 BREAK_TO_DEBUGGER(); 658 return NULL; 659 } 660 661 dce_ipp_construct(ipp, ctx, inst, 662 &ipp_regs[inst], &ipp_shift, &ipp_mask); 663 return &ipp->base; 664 } 665 666 static struct stream_encoder *dce120_stream_encoder_create( 667 enum engine_id eng_id, 668 struct dc_context *ctx) 669 { 670 struct dce110_stream_encoder *enc110 = 671 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 672 673 if (!enc110) 674 return NULL; 675 676 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 677 &stream_enc_regs[eng_id], 678 &se_shift, &se_mask); 679 return &enc110->base; 680 } 681 682 #define SRII(reg_name, block, id)\ 683 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 684 mm ## block ## id ## _ ## reg_name 685 686 static const struct dce_hwseq_registers hwseq_reg = { 687 HWSEQ_DCE120_REG_LIST() 688 }; 689 690 static const struct dce_hwseq_shift hwseq_shift = { 691 HWSEQ_DCE12_MASK_SH_LIST(__SHIFT) 692 }; 693 694 static const struct dce_hwseq_mask hwseq_mask = { 695 HWSEQ_DCE12_MASK_SH_LIST(_MASK) 696 }; 697 698 /* HWSEQ regs for VG20 */ 699 static const struct dce_hwseq_registers dce121_hwseq_reg = { 700 HWSEQ_VG20_REG_LIST() 701 }; 702 703 static const struct dce_hwseq_shift dce121_hwseq_shift = { 704 HWSEQ_VG20_MASK_SH_LIST(__SHIFT) 705 }; 706 707 static const struct dce_hwseq_mask dce121_hwseq_mask = { 708 HWSEQ_VG20_MASK_SH_LIST(_MASK) 709 }; 710 711 static struct dce_hwseq *dce120_hwseq_create( 712 struct dc_context *ctx) 713 { 714 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 715 716 if (hws) { 717 hws->ctx = ctx; 718 hws->regs = &hwseq_reg; 719 hws->shifts = &hwseq_shift; 720 hws->masks = &hwseq_mask; 721 } 722 return hws; 723 } 724 725 static struct dce_hwseq *dce121_hwseq_create( 726 struct dc_context *ctx) 727 { 728 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 729 730 if (hws) { 731 hws->ctx = ctx; 732 hws->regs = &dce121_hwseq_reg; 733 hws->shifts = &dce121_hwseq_shift; 734 hws->masks = &dce121_hwseq_mask; 735 } 736 return hws; 737 } 738 739 static const struct resource_create_funcs res_create_funcs = { 740 .read_dce_straps = read_dce_straps, 741 .create_audio = create_audio, 742 .create_stream_encoder = dce120_stream_encoder_create, 743 .create_hwseq = dce120_hwseq_create, 744 }; 745 746 static const struct resource_create_funcs dce121_res_create_funcs = { 747 .read_dce_straps = read_dce_straps, 748 .create_audio = create_audio, 749 .create_stream_encoder = dce120_stream_encoder_create, 750 .create_hwseq = dce121_hwseq_create, 751 }; 752 753 754 #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) } 755 static const struct dce_mem_input_registers mi_regs[] = { 756 mi_inst_regs(0), 757 mi_inst_regs(1), 758 mi_inst_regs(2), 759 mi_inst_regs(3), 760 mi_inst_regs(4), 761 mi_inst_regs(5), 762 }; 763 764 static const struct dce_mem_input_shift mi_shifts = { 765 MI_DCE12_MASK_SH_LIST(__SHIFT) 766 }; 767 768 static const struct dce_mem_input_mask mi_masks = { 769 MI_DCE12_MASK_SH_LIST(_MASK) 770 }; 771 772 static struct mem_input *dce120_mem_input_create( 773 struct dc_context *ctx, 774 uint32_t inst) 775 { 776 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 777 GFP_KERNEL); 778 779 if (!dce_mi) { 780 BREAK_TO_DEBUGGER(); 781 return NULL; 782 } 783 784 dce120_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 785 return &dce_mi->base; 786 } 787 788 static struct transform *dce120_transform_create( 789 struct dc_context *ctx, 790 uint32_t inst) 791 { 792 struct dce_transform *transform = 793 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 794 795 if (!transform) 796 return NULL; 797 798 dce_transform_construct(transform, ctx, inst, 799 &xfm_regs[inst], &xfm_shift, &xfm_mask); 800 transform->lb_memory_size = 0x1404; /*5124*/ 801 return &transform->base; 802 } 803 804 static void dce120_destroy_resource_pool(struct resource_pool **pool) 805 { 806 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 807 808 destruct(dce110_pool); 809 kfree(dce110_pool); 810 *pool = NULL; 811 } 812 813 static const struct resource_funcs dce120_res_pool_funcs = { 814 .destroy = dce120_destroy_resource_pool, 815 .link_enc_create = dce120_link_encoder_create, 816 .validate_bandwidth = dce112_validate_bandwidth, 817 .validate_plane = dce100_validate_plane, 818 .add_stream_to_ctx = dce112_add_stream_to_ctx 819 }; 820 821 static void bw_calcs_data_update_from_pplib(struct dc *dc) 822 { 823 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 824 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 825 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; 826 int i; 827 unsigned int clk; 828 unsigned int latency; 829 830 /*do system clock*/ 831 if (!dm_pp_get_clock_levels_by_type_with_latency( 832 dc->ctx, 833 DM_PP_CLOCK_TYPE_ENGINE_CLK, 834 &eng_clks) || eng_clks.num_levels == 0) { 835 836 eng_clks.num_levels = 8; 837 clk = 300000; 838 839 for (i = 0; i < eng_clks.num_levels; i++) { 840 eng_clks.data[i].clocks_in_khz = clk; 841 clk += 100000; 842 } 843 } 844 845 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ 846 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 847 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); 848 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 849 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); 850 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 851 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); 852 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 853 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); 854 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 855 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); 856 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 857 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); 858 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 859 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); 860 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 861 eng_clks.data[0].clocks_in_khz, 1000); 862 863 /*do memory clock*/ 864 if (!dm_pp_get_clock_levels_by_type_with_latency( 865 dc->ctx, 866 DM_PP_CLOCK_TYPE_MEMORY_CLK, 867 &mem_clks) || mem_clks.num_levels == 0) { 868 869 mem_clks.num_levels = 3; 870 clk = 250000; 871 latency = 45; 872 873 for (i = 0; i < eng_clks.num_levels; i++) { 874 mem_clks.data[i].clocks_in_khz = clk; 875 mem_clks.data[i].latency_in_us = latency; 876 clk += 500000; 877 latency -= 5; 878 } 879 880 } 881 882 /* we don't need to call PPLIB for validation clock since they 883 * also give us the highest sclk and highest mclk (UMA clock). 884 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): 885 * YCLK = UMACLK*m_memoryTypeMultiplier 886 */ 887 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 888 mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 1000); 889 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 890 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 891 1000); 892 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 893 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 894 1000); 895 896 /* Now notify PPLib/SMU about which Watermarks sets they should select 897 * depending on DPM state they are in. And update BW MGR GFX Engine and 898 * Memory clock member variables for Watermarks calculations for each 899 * Watermark Set 900 */ 901 clk_ranges.num_wm_sets = 4; 902 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; 903 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = 904 eng_clks.data[0].clocks_in_khz; 905 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = 906 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 907 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz = 908 mem_clks.data[0].clocks_in_khz; 909 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = 910 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 911 912 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; 913 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = 914 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 915 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 916 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; 917 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz = 918 mem_clks.data[0].clocks_in_khz; 919 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = 920 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 921 922 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; 923 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = 924 eng_clks.data[0].clocks_in_khz; 925 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = 926 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 927 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz = 928 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 929 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 930 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; 931 932 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; 933 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = 934 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 935 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 936 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; 937 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz = 938 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 939 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 940 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; 941 942 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 943 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); 944 } 945 946 static uint32_t read_pipe_fuses(struct dc_context *ctx) 947 { 948 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); 949 /* VG20 support max 6 pipes */ 950 value = value & 0x3f; 951 return value; 952 } 953 954 static bool construct( 955 uint8_t num_virtual_links, 956 struct dc *dc, 957 struct dce110_resource_pool *pool) 958 { 959 unsigned int i; 960 int j; 961 struct dc_context *ctx = dc->ctx; 962 struct irq_service_init_data irq_init_data; 963 static const struct resource_create_funcs *res_funcs; 964 bool is_vg20 = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev); 965 uint32_t pipe_fuses; 966 967 ctx->dc_bios->regs = &bios_regs; 968 969 pool->base.res_cap = &res_cap; 970 pool->base.funcs = &dce120_res_pool_funcs; 971 972 /* TODO: Fill more data from GreenlandAsicCapability.cpp */ 973 pool->base.pipe_count = res_cap.num_timing_generator; 974 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 975 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 976 977 dc->caps.max_downscale_ratio = 200; 978 dc->caps.i2c_speed_in_khz = 100; 979 dc->caps.max_cursor_size = 128; 980 dc->caps.dual_link_dvi = true; 981 dc->caps.psp_setup_panel_mode = true; 982 983 dc->debug = debug_defaults; 984 985 /************************************************* 986 * Create resources * 987 *************************************************/ 988 989 pool->base.clock_sources[DCE120_CLK_SRC_PLL0] = 990 dce120_clock_source_create(ctx, ctx->dc_bios, 991 CLOCK_SOURCE_COMBO_PHY_PLL0, 992 &clk_src_regs[0], false); 993 pool->base.clock_sources[DCE120_CLK_SRC_PLL1] = 994 dce120_clock_source_create(ctx, ctx->dc_bios, 995 CLOCK_SOURCE_COMBO_PHY_PLL1, 996 &clk_src_regs[1], false); 997 pool->base.clock_sources[DCE120_CLK_SRC_PLL2] = 998 dce120_clock_source_create(ctx, ctx->dc_bios, 999 CLOCK_SOURCE_COMBO_PHY_PLL2, 1000 &clk_src_regs[2], false); 1001 pool->base.clock_sources[DCE120_CLK_SRC_PLL3] = 1002 dce120_clock_source_create(ctx, ctx->dc_bios, 1003 CLOCK_SOURCE_COMBO_PHY_PLL3, 1004 &clk_src_regs[3], false); 1005 pool->base.clock_sources[DCE120_CLK_SRC_PLL4] = 1006 dce120_clock_source_create(ctx, ctx->dc_bios, 1007 CLOCK_SOURCE_COMBO_PHY_PLL4, 1008 &clk_src_regs[4], false); 1009 pool->base.clock_sources[DCE120_CLK_SRC_PLL5] = 1010 dce120_clock_source_create(ctx, ctx->dc_bios, 1011 CLOCK_SOURCE_COMBO_PHY_PLL5, 1012 &clk_src_regs[5], false); 1013 pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL; 1014 1015 pool->base.dp_clock_source = 1016 dce120_clock_source_create(ctx, ctx->dc_bios, 1017 CLOCK_SOURCE_ID_DP_DTO, 1018 &clk_src_regs[0], true); 1019 1020 for (i = 0; i < pool->base.clk_src_count; i++) { 1021 if (pool->base.clock_sources[i] == NULL) { 1022 dm_error("DC: failed to create clock sources!\n"); 1023 BREAK_TO_DEBUGGER(); 1024 goto clk_src_create_fail; 1025 } 1026 } 1027 1028 if (is_vg20) 1029 pool->base.clk_mgr = dce121_clk_mgr_create(ctx); 1030 else 1031 pool->base.clk_mgr = dce120_clk_mgr_create(ctx); 1032 1033 if (pool->base.clk_mgr == NULL) { 1034 dm_error("DC: failed to create display clock!\n"); 1035 BREAK_TO_DEBUGGER(); 1036 goto dccg_create_fail; 1037 } 1038 1039 pool->base.dmcu = dce_dmcu_create(ctx, 1040 &dmcu_regs, 1041 &dmcu_shift, 1042 &dmcu_mask); 1043 if (pool->base.dmcu == NULL) { 1044 dm_error("DC: failed to create dmcu!\n"); 1045 BREAK_TO_DEBUGGER(); 1046 goto res_create_fail; 1047 } 1048 1049 pool->base.abm = dce_abm_create(ctx, 1050 &abm_regs, 1051 &abm_shift, 1052 &abm_mask); 1053 if (pool->base.abm == NULL) { 1054 dm_error("DC: failed to create abm!\n"); 1055 BREAK_TO_DEBUGGER(); 1056 goto res_create_fail; 1057 } 1058 1059 1060 irq_init_data.ctx = dc->ctx; 1061 pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data); 1062 if (!pool->base.irqs) 1063 goto irqs_create_fail; 1064 1065 /* VG20: Pipe harvesting enabled, retrieve valid pipe fuses */ 1066 if (is_vg20) 1067 pipe_fuses = read_pipe_fuses(ctx); 1068 1069 /* index to valid pipe resource */ 1070 j = 0; 1071 for (i = 0; i < pool->base.pipe_count; i++) { 1072 if (is_vg20) { 1073 if ((pipe_fuses & (1 << i)) != 0) { 1074 dm_error("DC: skip invalid pipe %d!\n", i); 1075 continue; 1076 } 1077 } 1078 1079 pool->base.timing_generators[j] = 1080 dce120_timing_generator_create( 1081 ctx, 1082 i, 1083 &dce120_tg_offsets[i]); 1084 if (pool->base.timing_generators[j] == NULL) { 1085 BREAK_TO_DEBUGGER(); 1086 dm_error("DC: failed to create tg!\n"); 1087 goto controller_create_fail; 1088 } 1089 1090 pool->base.mis[j] = dce120_mem_input_create(ctx, i); 1091 1092 if (pool->base.mis[j] == NULL) { 1093 BREAK_TO_DEBUGGER(); 1094 dm_error( 1095 "DC: failed to create memory input!\n"); 1096 goto controller_create_fail; 1097 } 1098 1099 pool->base.ipps[j] = dce120_ipp_create(ctx, i); 1100 if (pool->base.ipps[i] == NULL) { 1101 BREAK_TO_DEBUGGER(); 1102 dm_error( 1103 "DC: failed to create input pixel processor!\n"); 1104 goto controller_create_fail; 1105 } 1106 1107 pool->base.transforms[j] = dce120_transform_create(ctx, i); 1108 if (pool->base.transforms[i] == NULL) { 1109 BREAK_TO_DEBUGGER(); 1110 dm_error( 1111 "DC: failed to create transform!\n"); 1112 goto res_create_fail; 1113 } 1114 1115 pool->base.opps[j] = dce120_opp_create( 1116 ctx, 1117 i); 1118 if (pool->base.opps[j] == NULL) { 1119 BREAK_TO_DEBUGGER(); 1120 dm_error( 1121 "DC: failed to create output pixel processor!\n"); 1122 } 1123 1124 /* check next valid pipe */ 1125 j++; 1126 } 1127 1128 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1129 pool->base.engines[i] = dce120_aux_engine_create(ctx, i); 1130 if (pool->base.engines[i] == NULL) { 1131 BREAK_TO_DEBUGGER(); 1132 dm_error( 1133 "DC:failed to create aux engine!!\n"); 1134 goto res_create_fail; 1135 } 1136 pool->base.hw_i2cs[i] = dce120_i2c_hw_create(ctx, i); 1137 if (pool->base.hw_i2cs[i] == NULL) { 1138 BREAK_TO_DEBUGGER(); 1139 dm_error( 1140 "DC:failed to create i2c engine!!\n"); 1141 goto res_create_fail; 1142 } 1143 pool->base.sw_i2cs[i] = NULL; 1144 } 1145 1146 /* valid pipe num */ 1147 pool->base.pipe_count = j; 1148 pool->base.timing_generator_count = j; 1149 1150 if (is_vg20) 1151 res_funcs = &dce121_res_create_funcs; 1152 else 1153 res_funcs = &res_create_funcs; 1154 1155 if (!resource_construct(num_virtual_links, dc, &pool->base, res_funcs)) 1156 goto res_create_fail; 1157 1158 /* 1159 * This is a bit of a hack. The xGMI enabled info is used to determine 1160 * if audio and display clocks need to be adjusted with the WAFL link's 1161 * SS info. This is a responsiblity of the clk_mgr. But since MMHUB is 1162 * under hwseq, and the relevant register is in MMHUB, we have to do it 1163 * here. 1164 */ 1165 if (is_vg20 && dce121_xgmi_enabled(dc->hwseq)) 1166 dce121_clock_patch_xgmi_ss_info(pool->base.clk_mgr); 1167 1168 /* Create hardware sequencer */ 1169 if (!dce120_hw_sequencer_create(dc)) 1170 goto controller_create_fail; 1171 1172 dc->caps.max_planes = pool->base.pipe_count; 1173 1174 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1175 1176 bw_calcs_data_update_from_pplib(dc); 1177 1178 return true; 1179 1180 irqs_create_fail: 1181 controller_create_fail: 1182 dccg_create_fail: 1183 clk_src_create_fail: 1184 res_create_fail: 1185 1186 destruct(pool); 1187 1188 return false; 1189 } 1190 1191 struct resource_pool *dce120_create_resource_pool( 1192 uint8_t num_virtual_links, 1193 struct dc *dc) 1194 { 1195 struct dce110_resource_pool *pool = 1196 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1197 1198 if (!pool) 1199 return NULL; 1200 1201 if (construct(num_virtual_links, dc, pool)) 1202 return &pool->base; 1203 1204 BREAK_TO_DEBUGGER(); 1205 return NULL; 1206 } 1207