1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "link_encoder.h" 29 #include "stream_encoder.h" 30 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dce110/dce110_resource.h" 34 #include "dce110/dce110_timing_generator.h" 35 36 #include "irq/dce110/irq_service_dce110.h" 37 #include "dce/dce_mem_input.h" 38 #include "dce/dce_transform.h" 39 #include "dce/dce_link_encoder.h" 40 #include "dce/dce_stream_encoder.h" 41 #include "dce/dce_audio.h" 42 #include "dce/dce_opp.h" 43 #include "dce/dce_ipp.h" 44 #include "dce/dce_clock_source.h" 45 46 #include "dce/dce_hwseq.h" 47 #include "dce112/dce112_hw_sequencer.h" 48 #include "dce/dce_abm.h" 49 #include "dce/dce_dmcu.h" 50 #include "dce/dce_aux.h" 51 #include "dce/dce_i2c.h" 52 53 #include "reg_helper.h" 54 55 #include "dce/dce_11_2_d.h" 56 #include "dce/dce_11_2_sh_mask.h" 57 58 #include "dce100/dce100_resource.h" 59 #define DC_LOGGER \ 60 dc->ctx->logger 61 62 #ifndef mmDP_DPHY_INTERNAL_CTRL 63 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 64 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 65 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 66 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 67 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 68 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 69 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 70 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 71 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 72 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 73 #endif 74 75 #ifndef mmBIOS_SCRATCH_2 76 #define mmBIOS_SCRATCH_2 0x05CB 77 #define mmBIOS_SCRATCH_3 0x05CC 78 #define mmBIOS_SCRATCH_6 0x05CF 79 #endif 80 81 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 82 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 83 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 84 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 85 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 86 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 87 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 88 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 89 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 90 #endif 91 92 #ifndef mmDP_DPHY_FAST_TRAINING 93 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 94 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 95 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 96 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 97 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 98 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 99 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 100 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 101 #endif 102 103 enum dce112_clk_src_array_id { 104 DCE112_CLK_SRC_PLL0, 105 DCE112_CLK_SRC_PLL1, 106 DCE112_CLK_SRC_PLL2, 107 DCE112_CLK_SRC_PLL3, 108 DCE112_CLK_SRC_PLL4, 109 DCE112_CLK_SRC_PLL5, 110 111 DCE112_CLK_SRC_TOTAL 112 }; 113 114 static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = { 115 { 116 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 117 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 118 }, 119 { 120 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 121 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 122 }, 123 { 124 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 125 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 126 }, 127 { 128 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 129 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 130 }, 131 { 132 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 133 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 134 }, 135 { 136 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 137 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 138 } 139 }; 140 141 /* set register offset */ 142 #define SR(reg_name)\ 143 .reg_name = mm ## reg_name 144 145 /* set register offset with instance */ 146 #define SRI(reg_name, block, id)\ 147 .reg_name = mm ## block ## id ## _ ## reg_name 148 149 static const struct dce_dmcu_registers dmcu_regs = { 150 DMCU_DCE110_COMMON_REG_LIST() 151 }; 152 153 static const struct dce_dmcu_shift dmcu_shift = { 154 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 155 }; 156 157 static const struct dce_dmcu_mask dmcu_mask = { 158 DMCU_MASK_SH_LIST_DCE110(_MASK) 159 }; 160 161 static const struct dce_abm_registers abm_regs = { 162 ABM_DCE110_COMMON_REG_LIST() 163 }; 164 165 static const struct dce_abm_shift abm_shift = { 166 ABM_MASK_SH_LIST_DCE110(__SHIFT) 167 }; 168 169 static const struct dce_abm_mask abm_mask = { 170 ABM_MASK_SH_LIST_DCE110(_MASK) 171 }; 172 173 #define ipp_regs(id)\ 174 [id] = {\ 175 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 176 } 177 178 static const struct dce_ipp_registers ipp_regs[] = { 179 ipp_regs(0), 180 ipp_regs(1), 181 ipp_regs(2), 182 ipp_regs(3), 183 ipp_regs(4), 184 ipp_regs(5) 185 }; 186 187 static const struct dce_ipp_shift ipp_shift = { 188 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 189 }; 190 191 static const struct dce_ipp_mask ipp_mask = { 192 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 193 }; 194 195 #define transform_regs(id)\ 196 [id] = {\ 197 XFM_COMMON_REG_LIST_DCE110(id)\ 198 } 199 200 static const struct dce_transform_registers xfm_regs[] = { 201 transform_regs(0), 202 transform_regs(1), 203 transform_regs(2), 204 transform_regs(3), 205 transform_regs(4), 206 transform_regs(5) 207 }; 208 209 static const struct dce_transform_shift xfm_shift = { 210 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 211 }; 212 213 static const struct dce_transform_mask xfm_mask = { 214 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 215 }; 216 217 #define aux_regs(id)\ 218 [id] = {\ 219 AUX_REG_LIST(id)\ 220 } 221 222 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 223 aux_regs(0), 224 aux_regs(1), 225 aux_regs(2), 226 aux_regs(3), 227 aux_regs(4), 228 aux_regs(5) 229 }; 230 231 #define hpd_regs(id)\ 232 [id] = {\ 233 HPD_REG_LIST(id)\ 234 } 235 236 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 237 hpd_regs(0), 238 hpd_regs(1), 239 hpd_regs(2), 240 hpd_regs(3), 241 hpd_regs(4), 242 hpd_regs(5) 243 }; 244 245 #define link_regs(id)\ 246 [id] = {\ 247 LE_DCE110_REG_LIST(id)\ 248 } 249 250 static const struct dce110_link_enc_registers link_enc_regs[] = { 251 link_regs(0), 252 link_regs(1), 253 link_regs(2), 254 link_regs(3), 255 link_regs(4), 256 link_regs(5), 257 link_regs(6), 258 }; 259 260 #define stream_enc_regs(id)\ 261 [id] = {\ 262 SE_COMMON_REG_LIST(id),\ 263 .TMDS_CNTL = 0,\ 264 } 265 266 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 267 stream_enc_regs(0), 268 stream_enc_regs(1), 269 stream_enc_regs(2), 270 stream_enc_regs(3), 271 stream_enc_regs(4), 272 stream_enc_regs(5) 273 }; 274 275 static const struct dce_stream_encoder_shift se_shift = { 276 SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT) 277 }; 278 279 static const struct dce_stream_encoder_mask se_mask = { 280 SE_COMMON_MASK_SH_LIST_DCE112(_MASK) 281 }; 282 283 #define opp_regs(id)\ 284 [id] = {\ 285 OPP_DCE_112_REG_LIST(id),\ 286 } 287 288 static const struct dce_opp_registers opp_regs[] = { 289 opp_regs(0), 290 opp_regs(1), 291 opp_regs(2), 292 opp_regs(3), 293 opp_regs(4), 294 opp_regs(5) 295 }; 296 297 static const struct dce_opp_shift opp_shift = { 298 OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 299 }; 300 301 static const struct dce_opp_mask opp_mask = { 302 OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK) 303 }; 304 305 #define aux_engine_regs(id)\ 306 [id] = {\ 307 AUX_COMMON_REG_LIST(id), \ 308 .AUX_RESET_MASK = 0 \ 309 } 310 311 static const struct dce110_aux_registers aux_engine_regs[] = { 312 aux_engine_regs(0), 313 aux_engine_regs(1), 314 aux_engine_regs(2), 315 aux_engine_regs(3), 316 aux_engine_regs(4), 317 aux_engine_regs(5) 318 }; 319 320 #define audio_regs(id)\ 321 [id] = {\ 322 AUD_COMMON_REG_LIST(id)\ 323 } 324 325 static const struct dce_audio_registers audio_regs[] = { 326 audio_regs(0), 327 audio_regs(1), 328 audio_regs(2), 329 audio_regs(3), 330 audio_regs(4), 331 audio_regs(5) 332 }; 333 334 static const struct dce_audio_shift audio_shift = { 335 AUD_COMMON_MASK_SH_LIST(__SHIFT) 336 }; 337 338 static const struct dce_aduio_mask audio_mask = { 339 AUD_COMMON_MASK_SH_LIST(_MASK) 340 }; 341 342 #define clk_src_regs(index, id)\ 343 [index] = {\ 344 CS_COMMON_REG_LIST_DCE_112(id),\ 345 } 346 347 static const struct dce110_clk_src_regs clk_src_regs[] = { 348 clk_src_regs(0, A), 349 clk_src_regs(1, B), 350 clk_src_regs(2, C), 351 clk_src_regs(3, D), 352 clk_src_regs(4, E), 353 clk_src_regs(5, F) 354 }; 355 356 static const struct dce110_clk_src_shift cs_shift = { 357 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 358 }; 359 360 static const struct dce110_clk_src_mask cs_mask = { 361 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) 362 }; 363 364 static const struct bios_registers bios_regs = { 365 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 366 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 367 }; 368 369 static const struct resource_caps polaris_10_resource_cap = { 370 .num_timing_generator = 6, 371 .num_audio = 6, 372 .num_stream_encoder = 6, 373 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */ 374 .num_ddc = 6, 375 }; 376 377 static const struct resource_caps polaris_11_resource_cap = { 378 .num_timing_generator = 5, 379 .num_audio = 5, 380 .num_stream_encoder = 5, 381 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */ 382 .num_ddc = 5, 383 }; 384 385 static const struct dc_plane_cap plane_cap = { 386 .type = DC_PLANE_TYPE_DCE_RGB, 387 388 .pixel_format_support = { 389 .argb8888 = true, 390 .nv12 = false, 391 .fp16 = false 392 }, 393 394 .max_upscale_factor = { 395 .argb8888 = 16000, 396 .nv12 = 1, 397 .fp16 = 1 398 }, 399 400 .max_downscale_factor = { 401 .argb8888 = 250, 402 .nv12 = 1, 403 .fp16 = 1 404 } 405 }; 406 407 #define CTX ctx 408 #define REG(reg) mm ## reg 409 410 #ifndef mmCC_DC_HDMI_STRAPS 411 #define mmCC_DC_HDMI_STRAPS 0x4819 412 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 413 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 414 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 415 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 416 #endif 417 418 static void read_dce_straps( 419 struct dc_context *ctx, 420 struct resource_straps *straps) 421 { 422 REG_GET_2(CC_DC_HDMI_STRAPS, 423 HDMI_DISABLE, &straps->hdmi_disable, 424 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 425 426 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 427 } 428 429 static struct audio *create_audio( 430 struct dc_context *ctx, unsigned int inst) 431 { 432 return dce_audio_create(ctx, inst, 433 &audio_regs[inst], &audio_shift, &audio_mask); 434 } 435 436 437 static struct timing_generator *dce112_timing_generator_create( 438 struct dc_context *ctx, 439 uint32_t instance, 440 const struct dce110_timing_generator_offsets *offsets) 441 { 442 struct dce110_timing_generator *tg110 = 443 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 444 445 if (!tg110) 446 return NULL; 447 448 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 449 return &tg110->base; 450 } 451 452 static struct stream_encoder *dce112_stream_encoder_create( 453 enum engine_id eng_id, 454 struct dc_context *ctx) 455 { 456 struct dce110_stream_encoder *enc110 = 457 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 458 459 if (!enc110) 460 return NULL; 461 462 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 463 &stream_enc_regs[eng_id], 464 &se_shift, &se_mask); 465 return &enc110->base; 466 } 467 468 #define SRII(reg_name, block, id)\ 469 .reg_name[id] = mm ## block ## id ## _ ## reg_name 470 471 static const struct dce_hwseq_registers hwseq_reg = { 472 HWSEQ_DCE112_REG_LIST() 473 }; 474 475 static const struct dce_hwseq_shift hwseq_shift = { 476 HWSEQ_DCE112_MASK_SH_LIST(__SHIFT) 477 }; 478 479 static const struct dce_hwseq_mask hwseq_mask = { 480 HWSEQ_DCE112_MASK_SH_LIST(_MASK) 481 }; 482 483 static struct dce_hwseq *dce112_hwseq_create( 484 struct dc_context *ctx) 485 { 486 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 487 488 if (hws) { 489 hws->ctx = ctx; 490 hws->regs = &hwseq_reg; 491 hws->shifts = &hwseq_shift; 492 hws->masks = &hwseq_mask; 493 } 494 return hws; 495 } 496 497 static const struct resource_create_funcs res_create_funcs = { 498 .read_dce_straps = read_dce_straps, 499 .create_audio = create_audio, 500 .create_stream_encoder = dce112_stream_encoder_create, 501 .create_hwseq = dce112_hwseq_create, 502 }; 503 504 #define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) } 505 static const struct dce_mem_input_registers mi_regs[] = { 506 mi_inst_regs(0), 507 mi_inst_regs(1), 508 mi_inst_regs(2), 509 mi_inst_regs(3), 510 mi_inst_regs(4), 511 mi_inst_regs(5), 512 }; 513 514 static const struct dce_mem_input_shift mi_shifts = { 515 MI_DCE11_2_MASK_SH_LIST(__SHIFT) 516 }; 517 518 static const struct dce_mem_input_mask mi_masks = { 519 MI_DCE11_2_MASK_SH_LIST(_MASK) 520 }; 521 522 static struct mem_input *dce112_mem_input_create( 523 struct dc_context *ctx, 524 uint32_t inst) 525 { 526 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 527 GFP_KERNEL); 528 529 if (!dce_mi) { 530 BREAK_TO_DEBUGGER(); 531 return NULL; 532 } 533 534 dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 535 return &dce_mi->base; 536 } 537 538 static void dce112_transform_destroy(struct transform **xfm) 539 { 540 kfree(TO_DCE_TRANSFORM(*xfm)); 541 *xfm = NULL; 542 } 543 544 static struct transform *dce112_transform_create( 545 struct dc_context *ctx, 546 uint32_t inst) 547 { 548 struct dce_transform *transform = 549 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 550 551 if (!transform) 552 return NULL; 553 554 dce_transform_construct(transform, ctx, inst, 555 &xfm_regs[inst], &xfm_shift, &xfm_mask); 556 transform->lb_memory_size = 0x1404; /*5124*/ 557 return &transform->base; 558 } 559 560 static const struct encoder_feature_support link_enc_feature = { 561 .max_hdmi_deep_color = COLOR_DEPTH_121212, 562 .max_hdmi_pixel_clock = 600000, 563 .hdmi_ycbcr420_supported = true, 564 .dp_ycbcr420_supported = false, 565 .flags.bits.IS_HBR2_CAPABLE = true, 566 .flags.bits.IS_HBR3_CAPABLE = true, 567 .flags.bits.IS_TPS3_CAPABLE = true, 568 .flags.bits.IS_TPS4_CAPABLE = true 569 }; 570 571 struct link_encoder *dce112_link_encoder_create( 572 const struct encoder_init_data *enc_init_data) 573 { 574 struct dce110_link_encoder *enc110 = 575 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 576 577 if (!enc110) 578 return NULL; 579 580 dce110_link_encoder_construct(enc110, 581 enc_init_data, 582 &link_enc_feature, 583 &link_enc_regs[enc_init_data->transmitter], 584 &link_enc_aux_regs[enc_init_data->channel - 1], 585 &link_enc_hpd_regs[enc_init_data->hpd_source]); 586 return &enc110->base; 587 } 588 589 static struct input_pixel_processor *dce112_ipp_create( 590 struct dc_context *ctx, uint32_t inst) 591 { 592 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 593 594 if (!ipp) { 595 BREAK_TO_DEBUGGER(); 596 return NULL; 597 } 598 599 dce_ipp_construct(ipp, ctx, inst, 600 &ipp_regs[inst], &ipp_shift, &ipp_mask); 601 return &ipp->base; 602 } 603 604 struct output_pixel_processor *dce112_opp_create( 605 struct dc_context *ctx, 606 uint32_t inst) 607 { 608 struct dce110_opp *opp = 609 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 610 611 if (!opp) 612 return NULL; 613 614 dce110_opp_construct(opp, 615 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 616 return &opp->base; 617 } 618 619 struct dce_aux *dce112_aux_engine_create( 620 struct dc_context *ctx, 621 uint32_t inst) 622 { 623 struct aux_engine_dce110 *aux_engine = 624 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 625 626 if (!aux_engine) 627 return NULL; 628 629 dce110_aux_engine_construct(aux_engine, ctx, inst, 630 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 631 &aux_engine_regs[inst]); 632 633 return &aux_engine->base; 634 } 635 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 636 637 static const struct dce_i2c_registers i2c_hw_regs[] = { 638 i2c_inst_regs(1), 639 i2c_inst_regs(2), 640 i2c_inst_regs(3), 641 i2c_inst_regs(4), 642 i2c_inst_regs(5), 643 i2c_inst_regs(6), 644 }; 645 646 static const struct dce_i2c_shift i2c_shifts = { 647 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 648 }; 649 650 static const struct dce_i2c_mask i2c_masks = { 651 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 652 }; 653 654 struct dce_i2c_hw *dce112_i2c_hw_create( 655 struct dc_context *ctx, 656 uint32_t inst) 657 { 658 struct dce_i2c_hw *dce_i2c_hw = 659 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 660 661 if (!dce_i2c_hw) 662 return NULL; 663 664 dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst, 665 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 666 667 return dce_i2c_hw; 668 } 669 struct clock_source *dce112_clock_source_create( 670 struct dc_context *ctx, 671 struct dc_bios *bios, 672 enum clock_source_id id, 673 const struct dce110_clk_src_regs *regs, 674 bool dp_clk_src) 675 { 676 struct dce110_clk_src *clk_src = 677 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 678 679 if (!clk_src) 680 return NULL; 681 682 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 683 regs, &cs_shift, &cs_mask)) { 684 clk_src->base.dp_clk_src = dp_clk_src; 685 return &clk_src->base; 686 } 687 688 BREAK_TO_DEBUGGER(); 689 return NULL; 690 } 691 692 void dce112_clock_source_destroy(struct clock_source **clk_src) 693 { 694 kfree(TO_DCE110_CLK_SRC(*clk_src)); 695 *clk_src = NULL; 696 } 697 698 static void destruct(struct dce110_resource_pool *pool) 699 { 700 unsigned int i; 701 702 for (i = 0; i < pool->base.pipe_count; i++) { 703 if (pool->base.opps[i] != NULL) 704 dce110_opp_destroy(&pool->base.opps[i]); 705 706 if (pool->base.transforms[i] != NULL) 707 dce112_transform_destroy(&pool->base.transforms[i]); 708 709 if (pool->base.ipps[i] != NULL) 710 dce_ipp_destroy(&pool->base.ipps[i]); 711 712 if (pool->base.mis[i] != NULL) { 713 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 714 pool->base.mis[i] = NULL; 715 } 716 717 if (pool->base.timing_generators[i] != NULL) { 718 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 719 pool->base.timing_generators[i] = NULL; 720 } 721 } 722 723 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 724 if (pool->base.engines[i] != NULL) 725 dce110_engine_destroy(&pool->base.engines[i]); 726 if (pool->base.hw_i2cs[i] != NULL) { 727 kfree(pool->base.hw_i2cs[i]); 728 pool->base.hw_i2cs[i] = NULL; 729 } 730 if (pool->base.sw_i2cs[i] != NULL) { 731 kfree(pool->base.sw_i2cs[i]); 732 pool->base.sw_i2cs[i] = NULL; 733 } 734 } 735 736 for (i = 0; i < pool->base.stream_enc_count; i++) { 737 if (pool->base.stream_enc[i] != NULL) 738 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 739 } 740 741 for (i = 0; i < pool->base.clk_src_count; i++) { 742 if (pool->base.clock_sources[i] != NULL) { 743 dce112_clock_source_destroy(&pool->base.clock_sources[i]); 744 } 745 } 746 747 if (pool->base.dp_clock_source != NULL) 748 dce112_clock_source_destroy(&pool->base.dp_clock_source); 749 750 for (i = 0; i < pool->base.audio_count; i++) { 751 if (pool->base.audios[i] != NULL) { 752 dce_aud_destroy(&pool->base.audios[i]); 753 } 754 } 755 756 if (pool->base.abm != NULL) 757 dce_abm_destroy(&pool->base.abm); 758 759 if (pool->base.dmcu != NULL) 760 dce_dmcu_destroy(&pool->base.dmcu); 761 762 if (pool->base.irqs != NULL) { 763 dal_irq_service_destroy(&pool->base.irqs); 764 } 765 } 766 767 static struct clock_source *find_matching_pll( 768 struct resource_context *res_ctx, 769 const struct resource_pool *pool, 770 const struct dc_stream_state *const stream) 771 { 772 switch (stream->link->link_enc->transmitter) { 773 case TRANSMITTER_UNIPHY_A: 774 return pool->clock_sources[DCE112_CLK_SRC_PLL0]; 775 case TRANSMITTER_UNIPHY_B: 776 return pool->clock_sources[DCE112_CLK_SRC_PLL1]; 777 case TRANSMITTER_UNIPHY_C: 778 return pool->clock_sources[DCE112_CLK_SRC_PLL2]; 779 case TRANSMITTER_UNIPHY_D: 780 return pool->clock_sources[DCE112_CLK_SRC_PLL3]; 781 case TRANSMITTER_UNIPHY_E: 782 return pool->clock_sources[DCE112_CLK_SRC_PLL4]; 783 case TRANSMITTER_UNIPHY_F: 784 return pool->clock_sources[DCE112_CLK_SRC_PLL5]; 785 default: 786 return NULL; 787 }; 788 789 return 0; 790 } 791 792 static enum dc_status build_mapped_resource( 793 const struct dc *dc, 794 struct dc_state *context, 795 struct dc_stream_state *stream) 796 { 797 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 798 799 if (!pipe_ctx) 800 return DC_ERROR_UNEXPECTED; 801 802 dce110_resource_build_pipe_hw_param(pipe_ctx); 803 804 resource_build_info_frame(pipe_ctx); 805 806 return DC_OK; 807 } 808 809 bool dce112_validate_bandwidth( 810 struct dc *dc, 811 struct dc_state *context, 812 bool fast_validate) 813 { 814 bool result = false; 815 816 DC_LOG_BANDWIDTH_CALCS( 817 "%s: start", 818 __func__); 819 820 if (bw_calcs( 821 dc->ctx, 822 dc->bw_dceip, 823 dc->bw_vbios, 824 context->res_ctx.pipe_ctx, 825 dc->res_pool->pipe_count, 826 &context->bw_ctx.bw.dce)) 827 result = true; 828 829 if (!result) 830 DC_LOG_BANDWIDTH_VALIDATION( 831 "%s: Bandwidth validation failed!", 832 __func__); 833 834 if (memcmp(&dc->current_state->bw_ctx.bw.dce, 835 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { 836 837 DC_LOG_BANDWIDTH_CALCS( 838 "%s: finish,\n" 839 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 840 "stutMark_b: %d stutMark_a: %d\n" 841 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 842 "stutMark_b: %d stutMark_a: %d\n" 843 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 844 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n" 845 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" 846 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n" 847 , 848 __func__, 849 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark, 850 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark, 851 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, 852 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, 853 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark, 854 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark, 855 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark, 856 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark, 857 context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark, 858 context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark, 859 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark, 860 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark, 861 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark, 862 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark, 863 context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark, 864 context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark, 865 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark, 866 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark, 867 context->bw_ctx.bw.dce.stutter_mode_enable, 868 context->bw_ctx.bw.dce.cpuc_state_change_enable, 869 context->bw_ctx.bw.dce.cpup_state_change_enable, 870 context->bw_ctx.bw.dce.nbp_state_change_enable, 871 context->bw_ctx.bw.dce.all_displays_in_sync, 872 context->bw_ctx.bw.dce.dispclk_khz, 873 context->bw_ctx.bw.dce.sclk_khz, 874 context->bw_ctx.bw.dce.sclk_deep_sleep_khz, 875 context->bw_ctx.bw.dce.yclk_khz, 876 context->bw_ctx.bw.dce.blackout_recovery_time_us); 877 } 878 return result; 879 } 880 881 enum dc_status resource_map_phy_clock_resources( 882 const struct dc *dc, 883 struct dc_state *context, 884 struct dc_stream_state *stream) 885 { 886 887 /* acquire new resources */ 888 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( 889 &context->res_ctx, stream); 890 891 if (!pipe_ctx) 892 return DC_ERROR_UNEXPECTED; 893 894 if (dc_is_dp_signal(pipe_ctx->stream->signal) 895 || dc_is_virtual_signal(pipe_ctx->stream->signal)) 896 pipe_ctx->clock_source = 897 dc->res_pool->dp_clock_source; 898 else 899 pipe_ctx->clock_source = find_matching_pll( 900 &context->res_ctx, dc->res_pool, 901 stream); 902 903 if (pipe_ctx->clock_source == NULL) 904 return DC_NO_CLOCK_SOURCE_RESOURCE; 905 906 resource_reference_clock_source( 907 &context->res_ctx, 908 dc->res_pool, 909 pipe_ctx->clock_source); 910 911 return DC_OK; 912 } 913 914 static bool dce112_validate_surface_sets( 915 struct dc_state *context) 916 { 917 int i; 918 919 for (i = 0; i < context->stream_count; i++) { 920 if (context->stream_status[i].plane_count == 0) 921 continue; 922 923 if (context->stream_status[i].plane_count > 1) 924 return false; 925 926 if (context->stream_status[i].plane_states[0]->format 927 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 928 return false; 929 } 930 931 return true; 932 } 933 934 enum dc_status dce112_add_stream_to_ctx( 935 struct dc *dc, 936 struct dc_state *new_ctx, 937 struct dc_stream_state *dc_stream) 938 { 939 enum dc_status result = DC_ERROR_UNEXPECTED; 940 941 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 942 943 if (result == DC_OK) 944 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 945 946 947 if (result == DC_OK) 948 result = build_mapped_resource(dc, new_ctx, dc_stream); 949 950 return result; 951 } 952 953 enum dc_status dce112_validate_global( 954 struct dc *dc, 955 struct dc_state *context) 956 { 957 if (!dce112_validate_surface_sets(context)) 958 return DC_FAIL_SURFACE_VALIDATE; 959 960 return DC_OK; 961 } 962 963 static void dce112_destroy_resource_pool(struct resource_pool **pool) 964 { 965 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 966 967 destruct(dce110_pool); 968 kfree(dce110_pool); 969 *pool = NULL; 970 } 971 972 static const struct resource_funcs dce112_res_pool_funcs = { 973 .destroy = dce112_destroy_resource_pool, 974 .link_enc_create = dce112_link_encoder_create, 975 .validate_bandwidth = dce112_validate_bandwidth, 976 .validate_plane = dce100_validate_plane, 977 .add_stream_to_ctx = dce112_add_stream_to_ctx, 978 .validate_global = dce112_validate_global, 979 .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link 980 }; 981 982 static void bw_calcs_data_update_from_pplib(struct dc *dc) 983 { 984 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 985 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 986 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; 987 struct dm_pp_clock_levels clks = {0}; 988 989 /*do system clock TODO PPLIB: after PPLIB implement, 990 * then remove old way 991 */ 992 if (!dm_pp_get_clock_levels_by_type_with_latency( 993 dc->ctx, 994 DM_PP_CLOCK_TYPE_ENGINE_CLK, 995 &eng_clks)) { 996 997 /* This is only for temporary */ 998 dm_pp_get_clock_levels_by_type( 999 dc->ctx, 1000 DM_PP_CLOCK_TYPE_ENGINE_CLK, 1001 &clks); 1002 /* convert all the clock fro kHz to fix point mHz */ 1003 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 1004 clks.clocks_in_khz[clks.num_levels-1], 1000); 1005 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 1006 clks.clocks_in_khz[clks.num_levels/8], 1000); 1007 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 1008 clks.clocks_in_khz[clks.num_levels*2/8], 1000); 1009 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 1010 clks.clocks_in_khz[clks.num_levels*3/8], 1000); 1011 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 1012 clks.clocks_in_khz[clks.num_levels*4/8], 1000); 1013 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 1014 clks.clocks_in_khz[clks.num_levels*5/8], 1000); 1015 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1016 clks.clocks_in_khz[clks.num_levels*6/8], 1000); 1017 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1018 clks.clocks_in_khz[0], 1000); 1019 1020 /*do memory clock*/ 1021 dm_pp_get_clock_levels_by_type( 1022 dc->ctx, 1023 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1024 &clks); 1025 1026 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1027 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER_CZ, 1000); 1028 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1029 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ, 1030 1000); 1031 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1032 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER_CZ, 1033 1000); 1034 1035 return; 1036 } 1037 1038 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ 1039 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 1040 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); 1041 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 1042 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); 1043 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 1044 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); 1045 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 1046 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); 1047 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 1048 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); 1049 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 1050 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); 1051 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1052 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); 1053 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1054 eng_clks.data[0].clocks_in_khz, 1000); 1055 1056 /*do memory clock*/ 1057 dm_pp_get_clock_levels_by_type_with_latency( 1058 dc->ctx, 1059 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1060 &mem_clks); 1061 1062 /* we don't need to call PPLIB for validation clock since they 1063 * also give us the highest sclk and highest mclk (UMA clock). 1064 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): 1065 * YCLK = UMACLK*m_memoryTypeMultiplier 1066 */ 1067 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1068 mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 1000); 1069 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1070 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 1071 1000); 1072 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1073 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 1074 1000); 1075 1076 /* Now notify PPLib/SMU about which Watermarks sets they should select 1077 * depending on DPM state they are in. And update BW MGR GFX Engine and 1078 * Memory clock member variables for Watermarks calculations for each 1079 * Watermark Set 1080 */ 1081 clk_ranges.num_wm_sets = 4; 1082 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; 1083 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = 1084 eng_clks.data[0].clocks_in_khz; 1085 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = 1086 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 1087 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz = 1088 mem_clks.data[0].clocks_in_khz; 1089 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = 1090 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 1091 1092 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; 1093 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = 1094 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 1095 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 1096 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; 1097 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz = 1098 mem_clks.data[0].clocks_in_khz; 1099 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = 1100 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 1101 1102 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; 1103 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = 1104 eng_clks.data[0].clocks_in_khz; 1105 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = 1106 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 1107 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz = 1108 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 1109 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 1110 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; 1111 1112 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; 1113 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = 1114 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 1115 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 1116 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; 1117 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz = 1118 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 1119 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 1120 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; 1121 1122 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 1123 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); 1124 } 1125 1126 const struct resource_caps *dce112_resource_cap( 1127 struct hw_asic_id *asic_id) 1128 { 1129 if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) || 1130 ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev)) 1131 return &polaris_11_resource_cap; 1132 else 1133 return &polaris_10_resource_cap; 1134 } 1135 1136 static bool construct( 1137 uint8_t num_virtual_links, 1138 struct dc *dc, 1139 struct dce110_resource_pool *pool) 1140 { 1141 unsigned int i; 1142 struct dc_context *ctx = dc->ctx; 1143 1144 ctx->dc_bios->regs = &bios_regs; 1145 1146 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id); 1147 pool->base.funcs = &dce112_res_pool_funcs; 1148 1149 /************************************************* 1150 * Resource + asic cap harcoding * 1151 *************************************************/ 1152 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1153 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1154 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1155 dc->caps.max_downscale_ratio = 200; 1156 dc->caps.i2c_speed_in_khz = 100; 1157 dc->caps.max_cursor_size = 128; 1158 dc->caps.dual_link_dvi = true; 1159 1160 1161 /************************************************* 1162 * Create resources * 1163 *************************************************/ 1164 1165 pool->base.clock_sources[DCE112_CLK_SRC_PLL0] = 1166 dce112_clock_source_create( 1167 ctx, ctx->dc_bios, 1168 CLOCK_SOURCE_COMBO_PHY_PLL0, 1169 &clk_src_regs[0], false); 1170 pool->base.clock_sources[DCE112_CLK_SRC_PLL1] = 1171 dce112_clock_source_create( 1172 ctx, ctx->dc_bios, 1173 CLOCK_SOURCE_COMBO_PHY_PLL1, 1174 &clk_src_regs[1], false); 1175 pool->base.clock_sources[DCE112_CLK_SRC_PLL2] = 1176 dce112_clock_source_create( 1177 ctx, ctx->dc_bios, 1178 CLOCK_SOURCE_COMBO_PHY_PLL2, 1179 &clk_src_regs[2], false); 1180 pool->base.clock_sources[DCE112_CLK_SRC_PLL3] = 1181 dce112_clock_source_create( 1182 ctx, ctx->dc_bios, 1183 CLOCK_SOURCE_COMBO_PHY_PLL3, 1184 &clk_src_regs[3], false); 1185 pool->base.clock_sources[DCE112_CLK_SRC_PLL4] = 1186 dce112_clock_source_create( 1187 ctx, ctx->dc_bios, 1188 CLOCK_SOURCE_COMBO_PHY_PLL4, 1189 &clk_src_regs[4], false); 1190 pool->base.clock_sources[DCE112_CLK_SRC_PLL5] = 1191 dce112_clock_source_create( 1192 ctx, ctx->dc_bios, 1193 CLOCK_SOURCE_COMBO_PHY_PLL5, 1194 &clk_src_regs[5], false); 1195 pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL; 1196 1197 pool->base.dp_clock_source = dce112_clock_source_create( 1198 ctx, ctx->dc_bios, 1199 CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); 1200 1201 1202 for (i = 0; i < pool->base.clk_src_count; i++) { 1203 if (pool->base.clock_sources[i] == NULL) { 1204 dm_error("DC: failed to create clock sources!\n"); 1205 BREAK_TO_DEBUGGER(); 1206 goto res_create_fail; 1207 } 1208 } 1209 1210 pool->base.dmcu = dce_dmcu_create(ctx, 1211 &dmcu_regs, 1212 &dmcu_shift, 1213 &dmcu_mask); 1214 if (pool->base.dmcu == NULL) { 1215 dm_error("DC: failed to create dmcu!\n"); 1216 BREAK_TO_DEBUGGER(); 1217 goto res_create_fail; 1218 } 1219 1220 pool->base.abm = dce_abm_create(ctx, 1221 &abm_regs, 1222 &abm_shift, 1223 &abm_mask); 1224 if (pool->base.abm == NULL) { 1225 dm_error("DC: failed to create abm!\n"); 1226 BREAK_TO_DEBUGGER(); 1227 goto res_create_fail; 1228 } 1229 1230 { 1231 struct irq_service_init_data init_data; 1232 init_data.ctx = dc->ctx; 1233 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 1234 if (!pool->base.irqs) 1235 goto res_create_fail; 1236 } 1237 1238 for (i = 0; i < pool->base.pipe_count; i++) { 1239 pool->base.timing_generators[i] = 1240 dce112_timing_generator_create( 1241 ctx, 1242 i, 1243 &dce112_tg_offsets[i]); 1244 if (pool->base.timing_generators[i] == NULL) { 1245 BREAK_TO_DEBUGGER(); 1246 dm_error("DC: failed to create tg!\n"); 1247 goto res_create_fail; 1248 } 1249 1250 pool->base.mis[i] = dce112_mem_input_create(ctx, i); 1251 if (pool->base.mis[i] == NULL) { 1252 BREAK_TO_DEBUGGER(); 1253 dm_error( 1254 "DC: failed to create memory input!\n"); 1255 goto res_create_fail; 1256 } 1257 1258 pool->base.ipps[i] = dce112_ipp_create(ctx, i); 1259 if (pool->base.ipps[i] == NULL) { 1260 BREAK_TO_DEBUGGER(); 1261 dm_error( 1262 "DC:failed to create input pixel processor!\n"); 1263 goto res_create_fail; 1264 } 1265 1266 pool->base.transforms[i] = dce112_transform_create(ctx, i); 1267 if (pool->base.transforms[i] == NULL) { 1268 BREAK_TO_DEBUGGER(); 1269 dm_error( 1270 "DC: failed to create transform!\n"); 1271 goto res_create_fail; 1272 } 1273 1274 pool->base.opps[i] = dce112_opp_create( 1275 ctx, 1276 i); 1277 if (pool->base.opps[i] == NULL) { 1278 BREAK_TO_DEBUGGER(); 1279 dm_error( 1280 "DC:failed to create output pixel processor!\n"); 1281 goto res_create_fail; 1282 } 1283 } 1284 1285 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1286 pool->base.engines[i] = dce112_aux_engine_create(ctx, i); 1287 if (pool->base.engines[i] == NULL) { 1288 BREAK_TO_DEBUGGER(); 1289 dm_error( 1290 "DC:failed to create aux engine!!\n"); 1291 goto res_create_fail; 1292 } 1293 pool->base.hw_i2cs[i] = dce112_i2c_hw_create(ctx, i); 1294 if (pool->base.hw_i2cs[i] == NULL) { 1295 BREAK_TO_DEBUGGER(); 1296 dm_error( 1297 "DC:failed to create i2c engine!!\n"); 1298 goto res_create_fail; 1299 } 1300 pool->base.sw_i2cs[i] = NULL; 1301 } 1302 1303 if (!resource_construct(num_virtual_links, dc, &pool->base, 1304 &res_create_funcs)) 1305 goto res_create_fail; 1306 1307 dc->caps.max_planes = pool->base.pipe_count; 1308 1309 for (i = 0; i < dc->caps.max_planes; ++i) 1310 dc->caps.planes[i] = plane_cap; 1311 1312 /* Create hardware sequencer */ 1313 dce112_hw_sequencer_construct(dc); 1314 1315 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1316 1317 bw_calcs_data_update_from_pplib(dc); 1318 1319 return true; 1320 1321 res_create_fail: 1322 destruct(pool); 1323 return false; 1324 } 1325 1326 struct resource_pool *dce112_create_resource_pool( 1327 uint8_t num_virtual_links, 1328 struct dc *dc) 1329 { 1330 struct dce110_resource_pool *pool = 1331 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1332 1333 if (!pool) 1334 return NULL; 1335 1336 if (construct(num_virtual_links, dc, pool)) 1337 return &pool->base; 1338 1339 BREAK_TO_DEBUGGER(); 1340 return NULL; 1341 } 1342