1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dm_services.h"
27 
28 #include "link_encoder.h"
29 #include "stream_encoder.h"
30 
31 #include "resource.h"
32 #include "include/irq_service_interface.h"
33 #include "dce110/dce110_resource.h"
34 #include "dce110/dce110_timing_generator.h"
35 
36 #include "irq/dce110/irq_service_dce110.h"
37 
38 #include "dce/dce_clk_mgr.h"
39 #include "dce/dce_mem_input.h"
40 #include "dce/dce_transform.h"
41 #include "dce/dce_link_encoder.h"
42 #include "dce/dce_stream_encoder.h"
43 #include "dce/dce_audio.h"
44 #include "dce/dce_opp.h"
45 #include "dce/dce_ipp.h"
46 #include "dce/dce_clock_source.h"
47 
48 #include "dce/dce_hwseq.h"
49 #include "dce112/dce112_hw_sequencer.h"
50 #include "dce/dce_abm.h"
51 #include "dce/dce_dmcu.h"
52 #include "dce/dce_aux.h"
53 #include "dce/dce_i2c.h"
54 
55 #include "reg_helper.h"
56 
57 #include "dce/dce_11_2_d.h"
58 #include "dce/dce_11_2_sh_mask.h"
59 
60 #include "dce100/dce100_resource.h"
61 #define DC_LOGGER \
62 		dc->ctx->logger
63 
64 #ifndef mmDP_DPHY_INTERNAL_CTRL
65 	#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
66 	#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
67 	#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
68 	#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
69 	#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
70 	#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
71 	#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
72 	#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
73 	#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
74 	#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
75 #endif
76 
77 #ifndef mmBIOS_SCRATCH_2
78 	#define mmBIOS_SCRATCH_2 0x05CB
79 	#define mmBIOS_SCRATCH_3 0x05CC
80 	#define mmBIOS_SCRATCH_6 0x05CF
81 #endif
82 
83 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
84 	#define mmDP_DPHY_BS_SR_SWAP_CNTL                       0x4ADC
85 	#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                   0x4ADC
86 	#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                   0x4BDC
87 	#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                   0x4CDC
88 	#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                   0x4DDC
89 	#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                   0x4EDC
90 	#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL                   0x4FDC
91 	#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL                   0x54DC
92 #endif
93 
94 #ifndef mmDP_DPHY_FAST_TRAINING
95 	#define mmDP_DPHY_FAST_TRAINING                         0x4ABC
96 	#define mmDP0_DP_DPHY_FAST_TRAINING                     0x4ABC
97 	#define mmDP1_DP_DPHY_FAST_TRAINING                     0x4BBC
98 	#define mmDP2_DP_DPHY_FAST_TRAINING                     0x4CBC
99 	#define mmDP3_DP_DPHY_FAST_TRAINING                     0x4DBC
100 	#define mmDP4_DP_DPHY_FAST_TRAINING                     0x4EBC
101 	#define mmDP5_DP_DPHY_FAST_TRAINING                     0x4FBC
102 	#define mmDP6_DP_DPHY_FAST_TRAINING                     0x54BC
103 #endif
104 
105 enum dce112_clk_src_array_id {
106 	DCE112_CLK_SRC_PLL0,
107 	DCE112_CLK_SRC_PLL1,
108 	DCE112_CLK_SRC_PLL2,
109 	DCE112_CLK_SRC_PLL3,
110 	DCE112_CLK_SRC_PLL4,
111 	DCE112_CLK_SRC_PLL5,
112 
113 	DCE112_CLK_SRC_TOTAL
114 };
115 
116 static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = {
117 	{
118 		.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
119 		.dcp =  (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
120 	},
121 	{
122 		.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
123 		.dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
124 	},
125 	{
126 		.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
127 		.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
128 	},
129 	{
130 		.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
131 		.dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
132 	},
133 	{
134 		.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
135 		.dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
136 	},
137 	{
138 		.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
139 		.dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
140 	}
141 };
142 
143 /* set register offset */
144 #define SR(reg_name)\
145 	.reg_name = mm ## reg_name
146 
147 /* set register offset with instance */
148 #define SRI(reg_name, block, id)\
149 	.reg_name = mm ## block ## id ## _ ## reg_name
150 
151 
152 static const struct clk_mgr_registers disp_clk_regs = {
153 		CLK_COMMON_REG_LIST_DCE_BASE()
154 };
155 
156 static const struct clk_mgr_shift disp_clk_shift = {
157 		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
158 };
159 
160 static const struct clk_mgr_mask disp_clk_mask = {
161 		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
162 };
163 
164 static const struct dce_dmcu_registers dmcu_regs = {
165 		DMCU_DCE110_COMMON_REG_LIST()
166 };
167 
168 static const struct dce_dmcu_shift dmcu_shift = {
169 		DMCU_MASK_SH_LIST_DCE110(__SHIFT)
170 };
171 
172 static const struct dce_dmcu_mask dmcu_mask = {
173 		DMCU_MASK_SH_LIST_DCE110(_MASK)
174 };
175 
176 static const struct dce_abm_registers abm_regs = {
177 		ABM_DCE110_COMMON_REG_LIST()
178 };
179 
180 static const struct dce_abm_shift abm_shift = {
181 		ABM_MASK_SH_LIST_DCE110(__SHIFT)
182 };
183 
184 static const struct dce_abm_mask abm_mask = {
185 		ABM_MASK_SH_LIST_DCE110(_MASK)
186 };
187 
188 #define ipp_regs(id)\
189 [id] = {\
190 		IPP_DCE110_REG_LIST_DCE_BASE(id)\
191 }
192 
193 static const struct dce_ipp_registers ipp_regs[] = {
194 		ipp_regs(0),
195 		ipp_regs(1),
196 		ipp_regs(2),
197 		ipp_regs(3),
198 		ipp_regs(4),
199 		ipp_regs(5)
200 };
201 
202 static const struct dce_ipp_shift ipp_shift = {
203 		IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
204 };
205 
206 static const struct dce_ipp_mask ipp_mask = {
207 		IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
208 };
209 
210 #define transform_regs(id)\
211 [id] = {\
212 		XFM_COMMON_REG_LIST_DCE110(id)\
213 }
214 
215 static const struct dce_transform_registers xfm_regs[] = {
216 		transform_regs(0),
217 		transform_regs(1),
218 		transform_regs(2),
219 		transform_regs(3),
220 		transform_regs(4),
221 		transform_regs(5)
222 };
223 
224 static const struct dce_transform_shift xfm_shift = {
225 		XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
226 };
227 
228 static const struct dce_transform_mask xfm_mask = {
229 		XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
230 };
231 
232 #define aux_regs(id)\
233 [id] = {\
234 	AUX_REG_LIST(id)\
235 }
236 
237 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
238 		aux_regs(0),
239 		aux_regs(1),
240 		aux_regs(2),
241 		aux_regs(3),
242 		aux_regs(4),
243 		aux_regs(5)
244 };
245 
246 #define hpd_regs(id)\
247 [id] = {\
248 	HPD_REG_LIST(id)\
249 }
250 
251 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
252 		hpd_regs(0),
253 		hpd_regs(1),
254 		hpd_regs(2),
255 		hpd_regs(3),
256 		hpd_regs(4),
257 		hpd_regs(5)
258 };
259 
260 #define link_regs(id)\
261 [id] = {\
262 	LE_DCE110_REG_LIST(id)\
263 }
264 
265 static const struct dce110_link_enc_registers link_enc_regs[] = {
266 	link_regs(0),
267 	link_regs(1),
268 	link_regs(2),
269 	link_regs(3),
270 	link_regs(4),
271 	link_regs(5),
272 	link_regs(6),
273 };
274 
275 #define stream_enc_regs(id)\
276 [id] = {\
277 	SE_COMMON_REG_LIST(id),\
278 	.TMDS_CNTL = 0,\
279 }
280 
281 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
282 	stream_enc_regs(0),
283 	stream_enc_regs(1),
284 	stream_enc_regs(2),
285 	stream_enc_regs(3),
286 	stream_enc_regs(4),
287 	stream_enc_regs(5)
288 };
289 
290 static const struct dce_stream_encoder_shift se_shift = {
291 		SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT)
292 };
293 
294 static const struct dce_stream_encoder_mask se_mask = {
295 		SE_COMMON_MASK_SH_LIST_DCE112(_MASK)
296 };
297 
298 #define opp_regs(id)\
299 [id] = {\
300 	OPP_DCE_112_REG_LIST(id),\
301 }
302 
303 static const struct dce_opp_registers opp_regs[] = {
304 	opp_regs(0),
305 	opp_regs(1),
306 	opp_regs(2),
307 	opp_regs(3),
308 	opp_regs(4),
309 	opp_regs(5)
310 };
311 
312 static const struct dce_opp_shift opp_shift = {
313 	OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
314 };
315 
316 static const struct dce_opp_mask opp_mask = {
317 	OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK)
318 };
319 
320 #define aux_engine_regs(id)\
321 [id] = {\
322 	AUX_COMMON_REG_LIST(id), \
323 	.AUX_RESET_MASK = 0 \
324 }
325 
326 static const struct dce110_aux_registers aux_engine_regs[] = {
327 		aux_engine_regs(0),
328 		aux_engine_regs(1),
329 		aux_engine_regs(2),
330 		aux_engine_regs(3),
331 		aux_engine_regs(4),
332 		aux_engine_regs(5)
333 };
334 
335 #define audio_regs(id)\
336 [id] = {\
337 	AUD_COMMON_REG_LIST(id)\
338 }
339 
340 static const struct dce_audio_registers audio_regs[] = {
341 	audio_regs(0),
342 	audio_regs(1),
343 	audio_regs(2),
344 	audio_regs(3),
345 	audio_regs(4),
346 	audio_regs(5)
347 };
348 
349 static const struct dce_audio_shift audio_shift = {
350 		AUD_COMMON_MASK_SH_LIST(__SHIFT)
351 };
352 
353 static const struct dce_aduio_mask audio_mask = {
354 		AUD_COMMON_MASK_SH_LIST(_MASK)
355 };
356 
357 #define clk_src_regs(index, id)\
358 [index] = {\
359 	CS_COMMON_REG_LIST_DCE_112(id),\
360 }
361 
362 static const struct dce110_clk_src_regs clk_src_regs[] = {
363 	clk_src_regs(0, A),
364 	clk_src_regs(1, B),
365 	clk_src_regs(2, C),
366 	clk_src_regs(3, D),
367 	clk_src_regs(4, E),
368 	clk_src_regs(5, F)
369 };
370 
371 static const struct dce110_clk_src_shift cs_shift = {
372 		CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
373 };
374 
375 static const struct dce110_clk_src_mask cs_mask = {
376 		CS_COMMON_MASK_SH_LIST_DCE_112(_MASK)
377 };
378 
379 static const struct bios_registers bios_regs = {
380 	.BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
381 	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
382 };
383 
384 static const struct resource_caps polaris_10_resource_cap = {
385 		.num_timing_generator = 6,
386 		.num_audio = 6,
387 		.num_stream_encoder = 6,
388 		.num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
389 		.num_ddc = 6,
390 };
391 
392 static const struct resource_caps polaris_11_resource_cap = {
393 		.num_timing_generator = 5,
394 		.num_audio = 5,
395 		.num_stream_encoder = 5,
396 		.num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
397 		.num_ddc = 5,
398 };
399 
400 static const struct dc_plane_cap plane_cap = {
401 	.type = DC_PLANE_TYPE_DCE_RGB,
402 	.supports_argb8888 = true,
403 };
404 
405 #define CTX  ctx
406 #define REG(reg) mm ## reg
407 
408 #ifndef mmCC_DC_HDMI_STRAPS
409 #define mmCC_DC_HDMI_STRAPS 0x4819
410 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
411 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
412 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
413 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
414 #endif
415 
416 static void read_dce_straps(
417 	struct dc_context *ctx,
418 	struct resource_straps *straps)
419 {
420 	REG_GET_2(CC_DC_HDMI_STRAPS,
421 			HDMI_DISABLE, &straps->hdmi_disable,
422 			AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
423 
424 	REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
425 }
426 
427 static struct audio *create_audio(
428 		struct dc_context *ctx, unsigned int inst)
429 {
430 	return dce_audio_create(ctx, inst,
431 			&audio_regs[inst], &audio_shift, &audio_mask);
432 }
433 
434 
435 static struct timing_generator *dce112_timing_generator_create(
436 		struct dc_context *ctx,
437 		uint32_t instance,
438 		const struct dce110_timing_generator_offsets *offsets)
439 {
440 	struct dce110_timing_generator *tg110 =
441 		kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
442 
443 	if (!tg110)
444 		return NULL;
445 
446 	dce110_timing_generator_construct(tg110, ctx, instance, offsets);
447 	return &tg110->base;
448 }
449 
450 static struct stream_encoder *dce112_stream_encoder_create(
451 	enum engine_id eng_id,
452 	struct dc_context *ctx)
453 {
454 	struct dce110_stream_encoder *enc110 =
455 		kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
456 
457 	if (!enc110)
458 		return NULL;
459 
460 	dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
461 					&stream_enc_regs[eng_id],
462 					&se_shift, &se_mask);
463 	return &enc110->base;
464 }
465 
466 #define SRII(reg_name, block, id)\
467 	.reg_name[id] = mm ## block ## id ## _ ## reg_name
468 
469 static const struct dce_hwseq_registers hwseq_reg = {
470 		HWSEQ_DCE112_REG_LIST()
471 };
472 
473 static const struct dce_hwseq_shift hwseq_shift = {
474 		HWSEQ_DCE112_MASK_SH_LIST(__SHIFT)
475 };
476 
477 static const struct dce_hwseq_mask hwseq_mask = {
478 		HWSEQ_DCE112_MASK_SH_LIST(_MASK)
479 };
480 
481 static struct dce_hwseq *dce112_hwseq_create(
482 	struct dc_context *ctx)
483 {
484 	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
485 
486 	if (hws) {
487 		hws->ctx = ctx;
488 		hws->regs = &hwseq_reg;
489 		hws->shifts = &hwseq_shift;
490 		hws->masks = &hwseq_mask;
491 	}
492 	return hws;
493 }
494 
495 static const struct resource_create_funcs res_create_funcs = {
496 	.read_dce_straps = read_dce_straps,
497 	.create_audio = create_audio,
498 	.create_stream_encoder = dce112_stream_encoder_create,
499 	.create_hwseq = dce112_hwseq_create,
500 };
501 
502 #define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) }
503 static const struct dce_mem_input_registers mi_regs[] = {
504 		mi_inst_regs(0),
505 		mi_inst_regs(1),
506 		mi_inst_regs(2),
507 		mi_inst_regs(3),
508 		mi_inst_regs(4),
509 		mi_inst_regs(5),
510 };
511 
512 static const struct dce_mem_input_shift mi_shifts = {
513 		MI_DCE11_2_MASK_SH_LIST(__SHIFT)
514 };
515 
516 static const struct dce_mem_input_mask mi_masks = {
517 		MI_DCE11_2_MASK_SH_LIST(_MASK)
518 };
519 
520 static struct mem_input *dce112_mem_input_create(
521 	struct dc_context *ctx,
522 	uint32_t inst)
523 {
524 	struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
525 					       GFP_KERNEL);
526 
527 	if (!dce_mi) {
528 		BREAK_TO_DEBUGGER();
529 		return NULL;
530 	}
531 
532 	dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
533 	return &dce_mi->base;
534 }
535 
536 static void dce112_transform_destroy(struct transform **xfm)
537 {
538 	kfree(TO_DCE_TRANSFORM(*xfm));
539 	*xfm = NULL;
540 }
541 
542 static struct transform *dce112_transform_create(
543 	struct dc_context *ctx,
544 	uint32_t inst)
545 {
546 	struct dce_transform *transform =
547 		kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
548 
549 	if (!transform)
550 		return NULL;
551 
552 	dce_transform_construct(transform, ctx, inst,
553 				&xfm_regs[inst], &xfm_shift, &xfm_mask);
554 	transform->lb_memory_size = 0x1404; /*5124*/
555 	return &transform->base;
556 }
557 
558 static const struct encoder_feature_support link_enc_feature = {
559 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
560 		.max_hdmi_pixel_clock = 600000,
561 		.hdmi_ycbcr420_supported = true,
562 		.dp_ycbcr420_supported = false,
563 		.flags.bits.IS_HBR2_CAPABLE = true,
564 		.flags.bits.IS_HBR3_CAPABLE = true,
565 		.flags.bits.IS_TPS3_CAPABLE = true,
566 		.flags.bits.IS_TPS4_CAPABLE = true
567 };
568 
569 struct link_encoder *dce112_link_encoder_create(
570 	const struct encoder_init_data *enc_init_data)
571 {
572 	struct dce110_link_encoder *enc110 =
573 		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
574 
575 	if (!enc110)
576 		return NULL;
577 
578 	dce110_link_encoder_construct(enc110,
579 				      enc_init_data,
580 				      &link_enc_feature,
581 				      &link_enc_regs[enc_init_data->transmitter],
582 				      &link_enc_aux_regs[enc_init_data->channel - 1],
583 				      &link_enc_hpd_regs[enc_init_data->hpd_source]);
584 	return &enc110->base;
585 }
586 
587 static struct input_pixel_processor *dce112_ipp_create(
588 	struct dc_context *ctx, uint32_t inst)
589 {
590 	struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
591 
592 	if (!ipp) {
593 		BREAK_TO_DEBUGGER();
594 		return NULL;
595 	}
596 
597 	dce_ipp_construct(ipp, ctx, inst,
598 			&ipp_regs[inst], &ipp_shift, &ipp_mask);
599 	return &ipp->base;
600 }
601 
602 struct output_pixel_processor *dce112_opp_create(
603 	struct dc_context *ctx,
604 	uint32_t inst)
605 {
606 	struct dce110_opp *opp =
607 		kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
608 
609 	if (!opp)
610 		return NULL;
611 
612 	dce110_opp_construct(opp,
613 			     ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
614 	return &opp->base;
615 }
616 
617 struct dce_aux *dce112_aux_engine_create(
618 	struct dc_context *ctx,
619 	uint32_t inst)
620 {
621 	struct aux_engine_dce110 *aux_engine =
622 		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
623 
624 	if (!aux_engine)
625 		return NULL;
626 
627 	dce110_aux_engine_construct(aux_engine, ctx, inst,
628 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
629 				    &aux_engine_regs[inst]);
630 
631 	return &aux_engine->base;
632 }
633 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
634 
635 static const struct dce_i2c_registers i2c_hw_regs[] = {
636 		i2c_inst_regs(1),
637 		i2c_inst_regs(2),
638 		i2c_inst_regs(3),
639 		i2c_inst_regs(4),
640 		i2c_inst_regs(5),
641 		i2c_inst_regs(6),
642 };
643 
644 static const struct dce_i2c_shift i2c_shifts = {
645 		I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
646 };
647 
648 static const struct dce_i2c_mask i2c_masks = {
649 		I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
650 };
651 
652 struct dce_i2c_hw *dce112_i2c_hw_create(
653 	struct dc_context *ctx,
654 	uint32_t inst)
655 {
656 	struct dce_i2c_hw *dce_i2c_hw =
657 		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
658 
659 	if (!dce_i2c_hw)
660 		return NULL;
661 
662 	dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,
663 				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
664 
665 	return dce_i2c_hw;
666 }
667 struct clock_source *dce112_clock_source_create(
668 	struct dc_context *ctx,
669 	struct dc_bios *bios,
670 	enum clock_source_id id,
671 	const struct dce110_clk_src_regs *regs,
672 	bool dp_clk_src)
673 {
674 	struct dce110_clk_src *clk_src =
675 		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
676 
677 	if (!clk_src)
678 		return NULL;
679 
680 	if (dce112_clk_src_construct(clk_src, ctx, bios, id,
681 			regs, &cs_shift, &cs_mask)) {
682 		clk_src->base.dp_clk_src = dp_clk_src;
683 		return &clk_src->base;
684 	}
685 
686 	BREAK_TO_DEBUGGER();
687 	return NULL;
688 }
689 
690 void dce112_clock_source_destroy(struct clock_source **clk_src)
691 {
692 	kfree(TO_DCE110_CLK_SRC(*clk_src));
693 	*clk_src = NULL;
694 }
695 
696 static void destruct(struct dce110_resource_pool *pool)
697 {
698 	unsigned int i;
699 
700 	for (i = 0; i < pool->base.pipe_count; i++) {
701 		if (pool->base.opps[i] != NULL)
702 			dce110_opp_destroy(&pool->base.opps[i]);
703 
704 		if (pool->base.transforms[i] != NULL)
705 			dce112_transform_destroy(&pool->base.transforms[i]);
706 
707 		if (pool->base.ipps[i] != NULL)
708 			dce_ipp_destroy(&pool->base.ipps[i]);
709 
710 		if (pool->base.mis[i] != NULL) {
711 			kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
712 			pool->base.mis[i] = NULL;
713 		}
714 
715 		if (pool->base.timing_generators[i] != NULL) {
716 			kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
717 			pool->base.timing_generators[i] = NULL;
718 		}
719 	}
720 
721 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
722 		if (pool->base.engines[i] != NULL)
723 			dce110_engine_destroy(&pool->base.engines[i]);
724 		if (pool->base.hw_i2cs[i] != NULL) {
725 			kfree(pool->base.hw_i2cs[i]);
726 			pool->base.hw_i2cs[i] = NULL;
727 		}
728 		if (pool->base.sw_i2cs[i] != NULL) {
729 			kfree(pool->base.sw_i2cs[i]);
730 			pool->base.sw_i2cs[i] = NULL;
731 		}
732 	}
733 
734 	for (i = 0; i < pool->base.stream_enc_count; i++) {
735 		if (pool->base.stream_enc[i] != NULL)
736 			kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
737 	}
738 
739 	for (i = 0; i < pool->base.clk_src_count; i++) {
740 		if (pool->base.clock_sources[i] != NULL) {
741 			dce112_clock_source_destroy(&pool->base.clock_sources[i]);
742 		}
743 	}
744 
745 	if (pool->base.dp_clock_source != NULL)
746 		dce112_clock_source_destroy(&pool->base.dp_clock_source);
747 
748 	for (i = 0; i < pool->base.audio_count; i++)	{
749 		if (pool->base.audios[i] != NULL) {
750 			dce_aud_destroy(&pool->base.audios[i]);
751 		}
752 	}
753 
754 	if (pool->base.abm != NULL)
755 		dce_abm_destroy(&pool->base.abm);
756 
757 	if (pool->base.dmcu != NULL)
758 		dce_dmcu_destroy(&pool->base.dmcu);
759 
760 	if (pool->base.clk_mgr != NULL)
761 		dce_clk_mgr_destroy(&pool->base.clk_mgr);
762 
763 	if (pool->base.irqs != NULL) {
764 		dal_irq_service_destroy(&pool->base.irqs);
765 	}
766 }
767 
768 static struct clock_source *find_matching_pll(
769 		struct resource_context *res_ctx,
770 		const struct resource_pool *pool,
771 		const struct dc_stream_state *const stream)
772 {
773 	switch (stream->link->link_enc->transmitter) {
774 	case TRANSMITTER_UNIPHY_A:
775 		return pool->clock_sources[DCE112_CLK_SRC_PLL0];
776 	case TRANSMITTER_UNIPHY_B:
777 		return pool->clock_sources[DCE112_CLK_SRC_PLL1];
778 	case TRANSMITTER_UNIPHY_C:
779 		return pool->clock_sources[DCE112_CLK_SRC_PLL2];
780 	case TRANSMITTER_UNIPHY_D:
781 		return pool->clock_sources[DCE112_CLK_SRC_PLL3];
782 	case TRANSMITTER_UNIPHY_E:
783 		return pool->clock_sources[DCE112_CLK_SRC_PLL4];
784 	case TRANSMITTER_UNIPHY_F:
785 		return pool->clock_sources[DCE112_CLK_SRC_PLL5];
786 	default:
787 		return NULL;
788 	};
789 
790 	return 0;
791 }
792 
793 static enum dc_status build_mapped_resource(
794 		const struct dc *dc,
795 		struct dc_state *context,
796 		struct dc_stream_state *stream)
797 {
798 	struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
799 
800 	if (!pipe_ctx)
801 		return DC_ERROR_UNEXPECTED;
802 
803 	dce110_resource_build_pipe_hw_param(pipe_ctx);
804 
805 	resource_build_info_frame(pipe_ctx);
806 
807 	return DC_OK;
808 }
809 
810 bool dce112_validate_bandwidth(
811 	struct dc *dc,
812 	struct dc_state *context)
813 {
814 	bool result = false;
815 
816 	DC_LOG_BANDWIDTH_CALCS(
817 		"%s: start",
818 		__func__);
819 
820 	if (bw_calcs(
821 			dc->ctx,
822 			dc->bw_dceip,
823 			dc->bw_vbios,
824 			context->res_ctx.pipe_ctx,
825 			dc->res_pool->pipe_count,
826 			&context->bw.dce))
827 		result = true;
828 
829 	if (!result)
830 		DC_LOG_BANDWIDTH_VALIDATION(
831 			"%s: Bandwidth validation failed!",
832 			__func__);
833 
834 	if (memcmp(&dc->current_state->bw.dce,
835 			&context->bw.dce, sizeof(context->bw.dce))) {
836 
837 		DC_LOG_BANDWIDTH_CALCS(
838 			"%s: finish,\n"
839 			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
840 			"stutMark_b: %d stutMark_a: %d\n"
841 			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
842 			"stutMark_b: %d stutMark_a: %d\n"
843 			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
844 			"stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n"
845 			"cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
846 			"sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n"
847 			,
848 			__func__,
849 			context->bw.dce.nbp_state_change_wm_ns[0].b_mark,
850 			context->bw.dce.nbp_state_change_wm_ns[0].a_mark,
851 			context->bw.dce.urgent_wm_ns[0].b_mark,
852 			context->bw.dce.urgent_wm_ns[0].a_mark,
853 			context->bw.dce.stutter_exit_wm_ns[0].b_mark,
854 			context->bw.dce.stutter_exit_wm_ns[0].a_mark,
855 			context->bw.dce.nbp_state_change_wm_ns[1].b_mark,
856 			context->bw.dce.nbp_state_change_wm_ns[1].a_mark,
857 			context->bw.dce.urgent_wm_ns[1].b_mark,
858 			context->bw.dce.urgent_wm_ns[1].a_mark,
859 			context->bw.dce.stutter_exit_wm_ns[1].b_mark,
860 			context->bw.dce.stutter_exit_wm_ns[1].a_mark,
861 			context->bw.dce.nbp_state_change_wm_ns[2].b_mark,
862 			context->bw.dce.nbp_state_change_wm_ns[2].a_mark,
863 			context->bw.dce.urgent_wm_ns[2].b_mark,
864 			context->bw.dce.urgent_wm_ns[2].a_mark,
865 			context->bw.dce.stutter_exit_wm_ns[2].b_mark,
866 			context->bw.dce.stutter_exit_wm_ns[2].a_mark,
867 			context->bw.dce.stutter_mode_enable,
868 			context->bw.dce.cpuc_state_change_enable,
869 			context->bw.dce.cpup_state_change_enable,
870 			context->bw.dce.nbp_state_change_enable,
871 			context->bw.dce.all_displays_in_sync,
872 			context->bw.dce.dispclk_khz,
873 			context->bw.dce.sclk_khz,
874 			context->bw.dce.sclk_deep_sleep_khz,
875 			context->bw.dce.yclk_khz,
876 			context->bw.dce.blackout_recovery_time_us);
877 	}
878 	return result;
879 }
880 
881 enum dc_status resource_map_phy_clock_resources(
882 		const struct dc *dc,
883 		struct dc_state *context,
884 		struct dc_stream_state *stream)
885 {
886 
887 	/* acquire new resources */
888 	struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
889 			&context->res_ctx, stream);
890 
891 	if (!pipe_ctx)
892 		return DC_ERROR_UNEXPECTED;
893 
894 	if (dc_is_dp_signal(pipe_ctx->stream->signal)
895 		|| dc_is_virtual_signal(pipe_ctx->stream->signal))
896 		pipe_ctx->clock_source =
897 				dc->res_pool->dp_clock_source;
898 	else
899 		pipe_ctx->clock_source = find_matching_pll(
900 			&context->res_ctx, dc->res_pool,
901 			stream);
902 
903 	if (pipe_ctx->clock_source == NULL)
904 		return DC_NO_CLOCK_SOURCE_RESOURCE;
905 
906 	resource_reference_clock_source(
907 		&context->res_ctx,
908 		dc->res_pool,
909 		pipe_ctx->clock_source);
910 
911 	return DC_OK;
912 }
913 
914 static bool dce112_validate_surface_sets(
915 		struct dc_state *context)
916 {
917 	int i;
918 
919 	for (i = 0; i < context->stream_count; i++) {
920 		if (context->stream_status[i].plane_count == 0)
921 			continue;
922 
923 		if (context->stream_status[i].plane_count > 1)
924 			return false;
925 
926 		if (context->stream_status[i].plane_states[0]->format
927 				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
928 			return false;
929 	}
930 
931 	return true;
932 }
933 
934 enum dc_status dce112_add_stream_to_ctx(
935 		struct dc *dc,
936 		struct dc_state *new_ctx,
937 		struct dc_stream_state *dc_stream)
938 {
939 	enum dc_status result = DC_ERROR_UNEXPECTED;
940 
941 	result = resource_map_pool_resources(dc, new_ctx, dc_stream);
942 
943 	if (result == DC_OK)
944 		result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
945 
946 
947 	if (result == DC_OK)
948 		result = build_mapped_resource(dc, new_ctx, dc_stream);
949 
950 	return result;
951 }
952 
953 enum dc_status dce112_validate_global(
954 		struct dc *dc,
955 		struct dc_state *context)
956 {
957 	if (!dce112_validate_surface_sets(context))
958 		return DC_FAIL_SURFACE_VALIDATE;
959 
960 	return DC_OK;
961 }
962 
963 static void dce112_destroy_resource_pool(struct resource_pool **pool)
964 {
965 	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
966 
967 	destruct(dce110_pool);
968 	kfree(dce110_pool);
969 	*pool = NULL;
970 }
971 
972 static const struct resource_funcs dce112_res_pool_funcs = {
973 	.destroy = dce112_destroy_resource_pool,
974 	.link_enc_create = dce112_link_encoder_create,
975 	.validate_bandwidth = dce112_validate_bandwidth,
976 	.validate_plane = dce100_validate_plane,
977 	.add_stream_to_ctx = dce112_add_stream_to_ctx,
978 	.validate_global = dce112_validate_global
979 };
980 
981 static void bw_calcs_data_update_from_pplib(struct dc *dc)
982 {
983 	struct dm_pp_clock_levels_with_latency eng_clks = {0};
984 	struct dm_pp_clock_levels_with_latency mem_clks = {0};
985 	struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
986 	struct dm_pp_clock_levels clks = {0};
987 
988 	/*do system clock  TODO PPLIB: after PPLIB implement,
989 	 * then remove old way
990 	 */
991 	if (!dm_pp_get_clock_levels_by_type_with_latency(
992 			dc->ctx,
993 			DM_PP_CLOCK_TYPE_ENGINE_CLK,
994 			&eng_clks)) {
995 
996 		/* This is only for temporary */
997 		dm_pp_get_clock_levels_by_type(
998 				dc->ctx,
999 				DM_PP_CLOCK_TYPE_ENGINE_CLK,
1000 				&clks);
1001 		/* convert all the clock fro kHz to fix point mHz */
1002 		dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1003 				clks.clocks_in_khz[clks.num_levels-1], 1000);
1004 		dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
1005 				clks.clocks_in_khz[clks.num_levels/8], 1000);
1006 		dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
1007 				clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1008 		dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
1009 				clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1010 		dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
1011 				clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1012 		dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
1013 				clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1014 		dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
1015 				clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1016 		dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
1017 				clks.clocks_in_khz[0], 1000);
1018 
1019 		/*do memory clock*/
1020 		dm_pp_get_clock_levels_by_type(
1021 				dc->ctx,
1022 				DM_PP_CLOCK_TYPE_MEMORY_CLK,
1023 				&clks);
1024 
1025 		dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1026 			clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER_CZ, 1000);
1027 		dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1028 			clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ,
1029 			1000);
1030 		dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1031 			clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER_CZ,
1032 			1000);
1033 
1034 		return;
1035 	}
1036 
1037 	/* convert all the clock fro kHz to fix point mHz  TODO: wloop data */
1038 	dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1039 		eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
1040 	dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
1041 		eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
1042 	dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
1043 		eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
1044 	dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
1045 		eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
1046 	dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
1047 		eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
1048 	dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
1049 		eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
1050 	dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
1051 		eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
1052 	dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
1053 			eng_clks.data[0].clocks_in_khz, 1000);
1054 
1055 	/*do memory clock*/
1056 	dm_pp_get_clock_levels_by_type_with_latency(
1057 			dc->ctx,
1058 			DM_PP_CLOCK_TYPE_MEMORY_CLK,
1059 			&mem_clks);
1060 
1061 	/* we don't need to call PPLIB for validation clock since they
1062 	 * also give us the highest sclk and highest mclk (UMA clock).
1063 	 * ALSO always convert UMA clock (from PPLIB)  to YCLK (HW formula):
1064 	 * YCLK = UMACLK*m_memoryTypeMultiplier
1065 	 */
1066 	dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1067 		mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 1000);
1068 	dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1069 		mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ,
1070 		1000);
1071 	dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1072 		mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ,
1073 		1000);
1074 
1075 	/* Now notify PPLib/SMU about which Watermarks sets they should select
1076 	 * depending on DPM state they are in. And update BW MGR GFX Engine and
1077 	 * Memory clock member variables for Watermarks calculations for each
1078 	 * Watermark Set
1079 	 */
1080 	clk_ranges.num_wm_sets = 4;
1081 	clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
1082 	clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
1083 			eng_clks.data[0].clocks_in_khz;
1084 	clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
1085 			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1086 	clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz =
1087 			mem_clks.data[0].clocks_in_khz;
1088 	clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
1089 			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1090 
1091 	clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B;
1092 	clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz =
1093 			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1094 	/* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1095 	clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
1096 	clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz =
1097 			mem_clks.data[0].clocks_in_khz;
1098 	clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
1099 			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1100 
1101 	clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C;
1102 	clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz =
1103 			eng_clks.data[0].clocks_in_khz;
1104 	clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
1105 			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1106 	clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz =
1107 			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1108 	/* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1109 	clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
1110 
1111 	clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D;
1112 	clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz =
1113 			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1114 	/* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1115 	clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
1116 	clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz =
1117 			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1118 	/* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1119 	clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
1120 
1121 	/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1122 	dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
1123 }
1124 
1125 const struct resource_caps *dce112_resource_cap(
1126 	struct hw_asic_id *asic_id)
1127 {
1128 	if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) ||
1129 	    ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev))
1130 		return &polaris_11_resource_cap;
1131 	else
1132 		return &polaris_10_resource_cap;
1133 }
1134 
1135 static bool construct(
1136 	uint8_t num_virtual_links,
1137 	struct dc *dc,
1138 	struct dce110_resource_pool *pool)
1139 {
1140 	unsigned int i;
1141 	struct dc_context *ctx = dc->ctx;
1142 
1143 	ctx->dc_bios->regs = &bios_regs;
1144 
1145 	pool->base.res_cap = dce112_resource_cap(&ctx->asic_id);
1146 	pool->base.funcs = &dce112_res_pool_funcs;
1147 
1148 	/*************************************************
1149 	 *  Resource + asic cap harcoding                *
1150 	 *************************************************/
1151 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1152 	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1153 	pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1154 	dc->caps.max_downscale_ratio = 200;
1155 	dc->caps.i2c_speed_in_khz = 100;
1156 	dc->caps.max_cursor_size = 128;
1157 	dc->caps.dual_link_dvi = true;
1158 
1159 
1160 	/*************************************************
1161 	 *  Create resources                             *
1162 	 *************************************************/
1163 
1164 	pool->base.clock_sources[DCE112_CLK_SRC_PLL0] =
1165 			dce112_clock_source_create(
1166 				ctx, ctx->dc_bios,
1167 				CLOCK_SOURCE_COMBO_PHY_PLL0,
1168 				&clk_src_regs[0], false);
1169 	pool->base.clock_sources[DCE112_CLK_SRC_PLL1] =
1170 			dce112_clock_source_create(
1171 				ctx, ctx->dc_bios,
1172 				CLOCK_SOURCE_COMBO_PHY_PLL1,
1173 				&clk_src_regs[1], false);
1174 	pool->base.clock_sources[DCE112_CLK_SRC_PLL2] =
1175 			dce112_clock_source_create(
1176 				ctx, ctx->dc_bios,
1177 				CLOCK_SOURCE_COMBO_PHY_PLL2,
1178 				&clk_src_regs[2], false);
1179 	pool->base.clock_sources[DCE112_CLK_SRC_PLL3] =
1180 			dce112_clock_source_create(
1181 				ctx, ctx->dc_bios,
1182 				CLOCK_SOURCE_COMBO_PHY_PLL3,
1183 				&clk_src_regs[3], false);
1184 	pool->base.clock_sources[DCE112_CLK_SRC_PLL4] =
1185 			dce112_clock_source_create(
1186 				ctx, ctx->dc_bios,
1187 				CLOCK_SOURCE_COMBO_PHY_PLL4,
1188 				&clk_src_regs[4], false);
1189 	pool->base.clock_sources[DCE112_CLK_SRC_PLL5] =
1190 			dce112_clock_source_create(
1191 				ctx, ctx->dc_bios,
1192 				CLOCK_SOURCE_COMBO_PHY_PLL5,
1193 				&clk_src_regs[5], false);
1194 	pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL;
1195 
1196 	pool->base.dp_clock_source =  dce112_clock_source_create(
1197 		ctx, ctx->dc_bios,
1198 		CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true);
1199 
1200 
1201 	for (i = 0; i < pool->base.clk_src_count; i++) {
1202 		if (pool->base.clock_sources[i] == NULL) {
1203 			dm_error("DC: failed to create clock sources!\n");
1204 			BREAK_TO_DEBUGGER();
1205 			goto res_create_fail;
1206 		}
1207 	}
1208 
1209 	pool->base.clk_mgr = dce112_clk_mgr_create(ctx,
1210 			&disp_clk_regs,
1211 			&disp_clk_shift,
1212 			&disp_clk_mask);
1213 	if (pool->base.clk_mgr == NULL) {
1214 		dm_error("DC: failed to create display clock!\n");
1215 		BREAK_TO_DEBUGGER();
1216 		goto res_create_fail;
1217 	}
1218 
1219 	pool->base.dmcu = dce_dmcu_create(ctx,
1220 			&dmcu_regs,
1221 			&dmcu_shift,
1222 			&dmcu_mask);
1223 	if (pool->base.dmcu == NULL) {
1224 		dm_error("DC: failed to create dmcu!\n");
1225 		BREAK_TO_DEBUGGER();
1226 		goto res_create_fail;
1227 	}
1228 
1229 	pool->base.abm = dce_abm_create(ctx,
1230 			&abm_regs,
1231 			&abm_shift,
1232 			&abm_mask);
1233 	if (pool->base.abm == NULL) {
1234 		dm_error("DC: failed to create abm!\n");
1235 		BREAK_TO_DEBUGGER();
1236 		goto res_create_fail;
1237 	}
1238 
1239 	{
1240 		struct irq_service_init_data init_data;
1241 		init_data.ctx = dc->ctx;
1242 		pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1243 		if (!pool->base.irqs)
1244 			goto res_create_fail;
1245 	}
1246 
1247 	for (i = 0; i < pool->base.pipe_count; i++) {
1248 		pool->base.timing_generators[i] =
1249 				dce112_timing_generator_create(
1250 					ctx,
1251 					i,
1252 					&dce112_tg_offsets[i]);
1253 		if (pool->base.timing_generators[i] == NULL) {
1254 			BREAK_TO_DEBUGGER();
1255 			dm_error("DC: failed to create tg!\n");
1256 			goto res_create_fail;
1257 		}
1258 
1259 		pool->base.mis[i] = dce112_mem_input_create(ctx, i);
1260 		if (pool->base.mis[i] == NULL) {
1261 			BREAK_TO_DEBUGGER();
1262 			dm_error(
1263 				"DC: failed to create memory input!\n");
1264 			goto res_create_fail;
1265 		}
1266 
1267 		pool->base.ipps[i] = dce112_ipp_create(ctx, i);
1268 		if (pool->base.ipps[i] == NULL) {
1269 			BREAK_TO_DEBUGGER();
1270 			dm_error(
1271 				"DC:failed to create input pixel processor!\n");
1272 			goto res_create_fail;
1273 		}
1274 
1275 		pool->base.transforms[i] = dce112_transform_create(ctx, i);
1276 		if (pool->base.transforms[i] == NULL) {
1277 			BREAK_TO_DEBUGGER();
1278 			dm_error(
1279 				"DC: failed to create transform!\n");
1280 			goto res_create_fail;
1281 		}
1282 
1283 		pool->base.opps[i] = dce112_opp_create(
1284 			ctx,
1285 			i);
1286 		if (pool->base.opps[i] == NULL) {
1287 			BREAK_TO_DEBUGGER();
1288 			dm_error(
1289 				"DC:failed to create output pixel processor!\n");
1290 			goto res_create_fail;
1291 		}
1292 	}
1293 
1294 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1295 		pool->base.engines[i] = dce112_aux_engine_create(ctx, i);
1296 		if (pool->base.engines[i] == NULL) {
1297 			BREAK_TO_DEBUGGER();
1298 			dm_error(
1299 				"DC:failed to create aux engine!!\n");
1300 			goto res_create_fail;
1301 		}
1302 		pool->base.hw_i2cs[i] = dce112_i2c_hw_create(ctx, i);
1303 		if (pool->base.hw_i2cs[i] == NULL) {
1304 			BREAK_TO_DEBUGGER();
1305 			dm_error(
1306 				"DC:failed to create i2c engine!!\n");
1307 			goto res_create_fail;
1308 		}
1309 		pool->base.sw_i2cs[i] = NULL;
1310 	}
1311 
1312 	if (!resource_construct(num_virtual_links, dc, &pool->base,
1313 			  &res_create_funcs))
1314 		goto res_create_fail;
1315 
1316 	dc->caps.max_planes =  pool->base.pipe_count;
1317 
1318 	for (i = 0; i < dc->caps.max_planes; ++i)
1319 		dc->caps.planes[i] = plane_cap;
1320 
1321 	/* Create hardware sequencer */
1322 	dce112_hw_sequencer_construct(dc);
1323 
1324 	bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1325 
1326 	bw_calcs_data_update_from_pplib(dc);
1327 
1328 	return true;
1329 
1330 res_create_fail:
1331 	destruct(pool);
1332 	return false;
1333 }
1334 
1335 struct resource_pool *dce112_create_resource_pool(
1336 	uint8_t num_virtual_links,
1337 	struct dc *dc)
1338 {
1339 	struct dce110_resource_pool *pool =
1340 		kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1341 
1342 	if (!pool)
1343 		return NULL;
1344 
1345 	if (construct(num_virtual_links, dc, pool))
1346 		return &pool->base;
1347 
1348 	BREAK_TO_DEBUGGER();
1349 	return NULL;
1350 }
1351