1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "link_encoder.h" 29 #include "stream_encoder.h" 30 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dce110/dce110_resource.h" 34 #include "dce110/dce110_timing_generator.h" 35 36 #include "irq/dce110/irq_service_dce110.h" 37 38 #include "dce/dce_clk_mgr.h" 39 #include "dce/dce_mem_input.h" 40 #include "dce/dce_transform.h" 41 #include "dce/dce_link_encoder.h" 42 #include "dce/dce_stream_encoder.h" 43 #include "dce/dce_audio.h" 44 #include "dce/dce_opp.h" 45 #include "dce/dce_ipp.h" 46 #include "dce/dce_clock_source.h" 47 48 #include "dce/dce_hwseq.h" 49 #include "dce112/dce112_hw_sequencer.h" 50 #include "dce/dce_abm.h" 51 #include "dce/dce_dmcu.h" 52 #include "dce/dce_aux.h" 53 #include "dce/dce_i2c.h" 54 55 #include "reg_helper.h" 56 57 #include "dce/dce_11_2_d.h" 58 #include "dce/dce_11_2_sh_mask.h" 59 60 #include "dce100/dce100_resource.h" 61 #define DC_LOGGER \ 62 dc->ctx->logger 63 64 #ifndef mmDP_DPHY_INTERNAL_CTRL 65 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 66 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 67 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 68 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 69 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 70 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 71 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 72 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 73 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 74 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 75 #endif 76 77 #ifndef mmBIOS_SCRATCH_2 78 #define mmBIOS_SCRATCH_2 0x05CB 79 #define mmBIOS_SCRATCH_3 0x05CC 80 #define mmBIOS_SCRATCH_6 0x05CF 81 #endif 82 83 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 84 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 85 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 86 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 87 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 88 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 89 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 90 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 91 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 92 #endif 93 94 #ifndef mmDP_DPHY_FAST_TRAINING 95 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 96 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 97 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 98 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 99 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 100 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 101 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 102 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 103 #endif 104 105 enum dce112_clk_src_array_id { 106 DCE112_CLK_SRC_PLL0, 107 DCE112_CLK_SRC_PLL1, 108 DCE112_CLK_SRC_PLL2, 109 DCE112_CLK_SRC_PLL3, 110 DCE112_CLK_SRC_PLL4, 111 DCE112_CLK_SRC_PLL5, 112 113 DCE112_CLK_SRC_TOTAL 114 }; 115 116 static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = { 117 { 118 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 119 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 120 }, 121 { 122 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 123 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 124 }, 125 { 126 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 127 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 128 }, 129 { 130 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 131 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 132 }, 133 { 134 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 135 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 136 }, 137 { 138 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 139 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 140 } 141 }; 142 143 /* set register offset */ 144 #define SR(reg_name)\ 145 .reg_name = mm ## reg_name 146 147 /* set register offset with instance */ 148 #define SRI(reg_name, block, id)\ 149 .reg_name = mm ## block ## id ## _ ## reg_name 150 151 152 static const struct clk_mgr_registers disp_clk_regs = { 153 CLK_COMMON_REG_LIST_DCE_BASE() 154 }; 155 156 static const struct clk_mgr_shift disp_clk_shift = { 157 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 158 }; 159 160 static const struct clk_mgr_mask disp_clk_mask = { 161 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 162 }; 163 164 static const struct dce_dmcu_registers dmcu_regs = { 165 DMCU_DCE110_COMMON_REG_LIST() 166 }; 167 168 static const struct dce_dmcu_shift dmcu_shift = { 169 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 170 }; 171 172 static const struct dce_dmcu_mask dmcu_mask = { 173 DMCU_MASK_SH_LIST_DCE110(_MASK) 174 }; 175 176 static const struct dce_abm_registers abm_regs = { 177 ABM_DCE110_COMMON_REG_LIST() 178 }; 179 180 static const struct dce_abm_shift abm_shift = { 181 ABM_MASK_SH_LIST_DCE110(__SHIFT) 182 }; 183 184 static const struct dce_abm_mask abm_mask = { 185 ABM_MASK_SH_LIST_DCE110(_MASK) 186 }; 187 188 #define ipp_regs(id)\ 189 [id] = {\ 190 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 191 } 192 193 static const struct dce_ipp_registers ipp_regs[] = { 194 ipp_regs(0), 195 ipp_regs(1), 196 ipp_regs(2), 197 ipp_regs(3), 198 ipp_regs(4), 199 ipp_regs(5) 200 }; 201 202 static const struct dce_ipp_shift ipp_shift = { 203 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 204 }; 205 206 static const struct dce_ipp_mask ipp_mask = { 207 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 208 }; 209 210 #define transform_regs(id)\ 211 [id] = {\ 212 XFM_COMMON_REG_LIST_DCE110(id)\ 213 } 214 215 static const struct dce_transform_registers xfm_regs[] = { 216 transform_regs(0), 217 transform_regs(1), 218 transform_regs(2), 219 transform_regs(3), 220 transform_regs(4), 221 transform_regs(5) 222 }; 223 224 static const struct dce_transform_shift xfm_shift = { 225 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 226 }; 227 228 static const struct dce_transform_mask xfm_mask = { 229 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 230 }; 231 232 #define aux_regs(id)\ 233 [id] = {\ 234 AUX_REG_LIST(id)\ 235 } 236 237 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 238 aux_regs(0), 239 aux_regs(1), 240 aux_regs(2), 241 aux_regs(3), 242 aux_regs(4), 243 aux_regs(5) 244 }; 245 246 #define hpd_regs(id)\ 247 [id] = {\ 248 HPD_REG_LIST(id)\ 249 } 250 251 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 252 hpd_regs(0), 253 hpd_regs(1), 254 hpd_regs(2), 255 hpd_regs(3), 256 hpd_regs(4), 257 hpd_regs(5) 258 }; 259 260 #define link_regs(id)\ 261 [id] = {\ 262 LE_DCE110_REG_LIST(id)\ 263 } 264 265 static const struct dce110_link_enc_registers link_enc_regs[] = { 266 link_regs(0), 267 link_regs(1), 268 link_regs(2), 269 link_regs(3), 270 link_regs(4), 271 link_regs(5), 272 link_regs(6), 273 }; 274 275 #define stream_enc_regs(id)\ 276 [id] = {\ 277 SE_COMMON_REG_LIST(id),\ 278 .TMDS_CNTL = 0,\ 279 } 280 281 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 282 stream_enc_regs(0), 283 stream_enc_regs(1), 284 stream_enc_regs(2), 285 stream_enc_regs(3), 286 stream_enc_regs(4), 287 stream_enc_regs(5) 288 }; 289 290 static const struct dce_stream_encoder_shift se_shift = { 291 SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT) 292 }; 293 294 static const struct dce_stream_encoder_mask se_mask = { 295 SE_COMMON_MASK_SH_LIST_DCE112(_MASK) 296 }; 297 298 #define opp_regs(id)\ 299 [id] = {\ 300 OPP_DCE_112_REG_LIST(id),\ 301 } 302 303 static const struct dce_opp_registers opp_regs[] = { 304 opp_regs(0), 305 opp_regs(1), 306 opp_regs(2), 307 opp_regs(3), 308 opp_regs(4), 309 opp_regs(5) 310 }; 311 312 static const struct dce_opp_shift opp_shift = { 313 OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 314 }; 315 316 static const struct dce_opp_mask opp_mask = { 317 OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK) 318 }; 319 320 #define aux_engine_regs(id)\ 321 [id] = {\ 322 AUX_COMMON_REG_LIST(id), \ 323 .AUX_RESET_MASK = 0 \ 324 } 325 326 static const struct dce110_aux_registers aux_engine_regs[] = { 327 aux_engine_regs(0), 328 aux_engine_regs(1), 329 aux_engine_regs(2), 330 aux_engine_regs(3), 331 aux_engine_regs(4), 332 aux_engine_regs(5) 333 }; 334 335 #define audio_regs(id)\ 336 [id] = {\ 337 AUD_COMMON_REG_LIST(id)\ 338 } 339 340 static const struct dce_audio_registers audio_regs[] = { 341 audio_regs(0), 342 audio_regs(1), 343 audio_regs(2), 344 audio_regs(3), 345 audio_regs(4), 346 audio_regs(5) 347 }; 348 349 static const struct dce_audio_shift audio_shift = { 350 AUD_COMMON_MASK_SH_LIST(__SHIFT) 351 }; 352 353 static const struct dce_aduio_mask audio_mask = { 354 AUD_COMMON_MASK_SH_LIST(_MASK) 355 }; 356 357 #define clk_src_regs(index, id)\ 358 [index] = {\ 359 CS_COMMON_REG_LIST_DCE_112(id),\ 360 } 361 362 static const struct dce110_clk_src_regs clk_src_regs[] = { 363 clk_src_regs(0, A), 364 clk_src_regs(1, B), 365 clk_src_regs(2, C), 366 clk_src_regs(3, D), 367 clk_src_regs(4, E), 368 clk_src_regs(5, F) 369 }; 370 371 static const struct dce110_clk_src_shift cs_shift = { 372 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 373 }; 374 375 static const struct dce110_clk_src_mask cs_mask = { 376 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) 377 }; 378 379 static const struct bios_registers bios_regs = { 380 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 381 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 382 }; 383 384 static const struct resource_caps polaris_10_resource_cap = { 385 .num_timing_generator = 6, 386 .num_audio = 6, 387 .num_stream_encoder = 6, 388 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */ 389 .num_ddc = 6, 390 }; 391 392 static const struct resource_caps polaris_11_resource_cap = { 393 .num_timing_generator = 5, 394 .num_audio = 5, 395 .num_stream_encoder = 5, 396 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */ 397 .num_ddc = 5, 398 }; 399 400 static const struct dc_plane_cap plane_cap = { 401 .type = DC_PLANE_TYPE_DCE_RGB, 402 403 .pixel_format_support = { 404 .argb8888 = true, 405 .nv12 = false, 406 .fp16 = false 407 }, 408 409 .max_upscale_factor = { 410 .argb8888 = 16000, 411 .nv12 = 1, 412 .fp16 = 1 413 }, 414 415 .max_downscale_factor = { 416 .argb8888 = 250, 417 .nv12 = 1, 418 .fp16 = 1 419 } 420 }; 421 422 #define CTX ctx 423 #define REG(reg) mm ## reg 424 425 #ifndef mmCC_DC_HDMI_STRAPS 426 #define mmCC_DC_HDMI_STRAPS 0x4819 427 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 428 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 429 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 430 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 431 #endif 432 433 static void read_dce_straps( 434 struct dc_context *ctx, 435 struct resource_straps *straps) 436 { 437 REG_GET_2(CC_DC_HDMI_STRAPS, 438 HDMI_DISABLE, &straps->hdmi_disable, 439 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 440 441 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 442 } 443 444 static struct audio *create_audio( 445 struct dc_context *ctx, unsigned int inst) 446 { 447 return dce_audio_create(ctx, inst, 448 &audio_regs[inst], &audio_shift, &audio_mask); 449 } 450 451 452 static struct timing_generator *dce112_timing_generator_create( 453 struct dc_context *ctx, 454 uint32_t instance, 455 const struct dce110_timing_generator_offsets *offsets) 456 { 457 struct dce110_timing_generator *tg110 = 458 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 459 460 if (!tg110) 461 return NULL; 462 463 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 464 return &tg110->base; 465 } 466 467 static struct stream_encoder *dce112_stream_encoder_create( 468 enum engine_id eng_id, 469 struct dc_context *ctx) 470 { 471 struct dce110_stream_encoder *enc110 = 472 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 473 474 if (!enc110) 475 return NULL; 476 477 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 478 &stream_enc_regs[eng_id], 479 &se_shift, &se_mask); 480 return &enc110->base; 481 } 482 483 #define SRII(reg_name, block, id)\ 484 .reg_name[id] = mm ## block ## id ## _ ## reg_name 485 486 static const struct dce_hwseq_registers hwseq_reg = { 487 HWSEQ_DCE112_REG_LIST() 488 }; 489 490 static const struct dce_hwseq_shift hwseq_shift = { 491 HWSEQ_DCE112_MASK_SH_LIST(__SHIFT) 492 }; 493 494 static const struct dce_hwseq_mask hwseq_mask = { 495 HWSEQ_DCE112_MASK_SH_LIST(_MASK) 496 }; 497 498 static struct dce_hwseq *dce112_hwseq_create( 499 struct dc_context *ctx) 500 { 501 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 502 503 if (hws) { 504 hws->ctx = ctx; 505 hws->regs = &hwseq_reg; 506 hws->shifts = &hwseq_shift; 507 hws->masks = &hwseq_mask; 508 } 509 return hws; 510 } 511 512 static const struct resource_create_funcs res_create_funcs = { 513 .read_dce_straps = read_dce_straps, 514 .create_audio = create_audio, 515 .create_stream_encoder = dce112_stream_encoder_create, 516 .create_hwseq = dce112_hwseq_create, 517 }; 518 519 #define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) } 520 static const struct dce_mem_input_registers mi_regs[] = { 521 mi_inst_regs(0), 522 mi_inst_regs(1), 523 mi_inst_regs(2), 524 mi_inst_regs(3), 525 mi_inst_regs(4), 526 mi_inst_regs(5), 527 }; 528 529 static const struct dce_mem_input_shift mi_shifts = { 530 MI_DCE11_2_MASK_SH_LIST(__SHIFT) 531 }; 532 533 static const struct dce_mem_input_mask mi_masks = { 534 MI_DCE11_2_MASK_SH_LIST(_MASK) 535 }; 536 537 static struct mem_input *dce112_mem_input_create( 538 struct dc_context *ctx, 539 uint32_t inst) 540 { 541 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 542 GFP_KERNEL); 543 544 if (!dce_mi) { 545 BREAK_TO_DEBUGGER(); 546 return NULL; 547 } 548 549 dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 550 return &dce_mi->base; 551 } 552 553 static void dce112_transform_destroy(struct transform **xfm) 554 { 555 kfree(TO_DCE_TRANSFORM(*xfm)); 556 *xfm = NULL; 557 } 558 559 static struct transform *dce112_transform_create( 560 struct dc_context *ctx, 561 uint32_t inst) 562 { 563 struct dce_transform *transform = 564 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 565 566 if (!transform) 567 return NULL; 568 569 dce_transform_construct(transform, ctx, inst, 570 &xfm_regs[inst], &xfm_shift, &xfm_mask); 571 transform->lb_memory_size = 0x1404; /*5124*/ 572 return &transform->base; 573 } 574 575 static const struct encoder_feature_support link_enc_feature = { 576 .max_hdmi_deep_color = COLOR_DEPTH_121212, 577 .max_hdmi_pixel_clock = 600000, 578 .hdmi_ycbcr420_supported = true, 579 .dp_ycbcr420_supported = false, 580 .flags.bits.IS_HBR2_CAPABLE = true, 581 .flags.bits.IS_HBR3_CAPABLE = true, 582 .flags.bits.IS_TPS3_CAPABLE = true, 583 .flags.bits.IS_TPS4_CAPABLE = true 584 }; 585 586 struct link_encoder *dce112_link_encoder_create( 587 const struct encoder_init_data *enc_init_data) 588 { 589 struct dce110_link_encoder *enc110 = 590 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 591 592 if (!enc110) 593 return NULL; 594 595 dce110_link_encoder_construct(enc110, 596 enc_init_data, 597 &link_enc_feature, 598 &link_enc_regs[enc_init_data->transmitter], 599 &link_enc_aux_regs[enc_init_data->channel - 1], 600 &link_enc_hpd_regs[enc_init_data->hpd_source]); 601 return &enc110->base; 602 } 603 604 static struct input_pixel_processor *dce112_ipp_create( 605 struct dc_context *ctx, uint32_t inst) 606 { 607 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 608 609 if (!ipp) { 610 BREAK_TO_DEBUGGER(); 611 return NULL; 612 } 613 614 dce_ipp_construct(ipp, ctx, inst, 615 &ipp_regs[inst], &ipp_shift, &ipp_mask); 616 return &ipp->base; 617 } 618 619 struct output_pixel_processor *dce112_opp_create( 620 struct dc_context *ctx, 621 uint32_t inst) 622 { 623 struct dce110_opp *opp = 624 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 625 626 if (!opp) 627 return NULL; 628 629 dce110_opp_construct(opp, 630 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 631 return &opp->base; 632 } 633 634 struct dce_aux *dce112_aux_engine_create( 635 struct dc_context *ctx, 636 uint32_t inst) 637 { 638 struct aux_engine_dce110 *aux_engine = 639 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 640 641 if (!aux_engine) 642 return NULL; 643 644 dce110_aux_engine_construct(aux_engine, ctx, inst, 645 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 646 &aux_engine_regs[inst]); 647 648 return &aux_engine->base; 649 } 650 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 651 652 static const struct dce_i2c_registers i2c_hw_regs[] = { 653 i2c_inst_regs(1), 654 i2c_inst_regs(2), 655 i2c_inst_regs(3), 656 i2c_inst_regs(4), 657 i2c_inst_regs(5), 658 i2c_inst_regs(6), 659 }; 660 661 static const struct dce_i2c_shift i2c_shifts = { 662 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 663 }; 664 665 static const struct dce_i2c_mask i2c_masks = { 666 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 667 }; 668 669 struct dce_i2c_hw *dce112_i2c_hw_create( 670 struct dc_context *ctx, 671 uint32_t inst) 672 { 673 struct dce_i2c_hw *dce_i2c_hw = 674 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 675 676 if (!dce_i2c_hw) 677 return NULL; 678 679 dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst, 680 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 681 682 return dce_i2c_hw; 683 } 684 struct clock_source *dce112_clock_source_create( 685 struct dc_context *ctx, 686 struct dc_bios *bios, 687 enum clock_source_id id, 688 const struct dce110_clk_src_regs *regs, 689 bool dp_clk_src) 690 { 691 struct dce110_clk_src *clk_src = 692 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 693 694 if (!clk_src) 695 return NULL; 696 697 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 698 regs, &cs_shift, &cs_mask)) { 699 clk_src->base.dp_clk_src = dp_clk_src; 700 return &clk_src->base; 701 } 702 703 BREAK_TO_DEBUGGER(); 704 return NULL; 705 } 706 707 void dce112_clock_source_destroy(struct clock_source **clk_src) 708 { 709 kfree(TO_DCE110_CLK_SRC(*clk_src)); 710 *clk_src = NULL; 711 } 712 713 static void destruct(struct dce110_resource_pool *pool) 714 { 715 unsigned int i; 716 717 for (i = 0; i < pool->base.pipe_count; i++) { 718 if (pool->base.opps[i] != NULL) 719 dce110_opp_destroy(&pool->base.opps[i]); 720 721 if (pool->base.transforms[i] != NULL) 722 dce112_transform_destroy(&pool->base.transforms[i]); 723 724 if (pool->base.ipps[i] != NULL) 725 dce_ipp_destroy(&pool->base.ipps[i]); 726 727 if (pool->base.mis[i] != NULL) { 728 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 729 pool->base.mis[i] = NULL; 730 } 731 732 if (pool->base.timing_generators[i] != NULL) { 733 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 734 pool->base.timing_generators[i] = NULL; 735 } 736 } 737 738 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 739 if (pool->base.engines[i] != NULL) 740 dce110_engine_destroy(&pool->base.engines[i]); 741 if (pool->base.hw_i2cs[i] != NULL) { 742 kfree(pool->base.hw_i2cs[i]); 743 pool->base.hw_i2cs[i] = NULL; 744 } 745 if (pool->base.sw_i2cs[i] != NULL) { 746 kfree(pool->base.sw_i2cs[i]); 747 pool->base.sw_i2cs[i] = NULL; 748 } 749 } 750 751 for (i = 0; i < pool->base.stream_enc_count; i++) { 752 if (pool->base.stream_enc[i] != NULL) 753 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 754 } 755 756 for (i = 0; i < pool->base.clk_src_count; i++) { 757 if (pool->base.clock_sources[i] != NULL) { 758 dce112_clock_source_destroy(&pool->base.clock_sources[i]); 759 } 760 } 761 762 if (pool->base.dp_clock_source != NULL) 763 dce112_clock_source_destroy(&pool->base.dp_clock_source); 764 765 for (i = 0; i < pool->base.audio_count; i++) { 766 if (pool->base.audios[i] != NULL) { 767 dce_aud_destroy(&pool->base.audios[i]); 768 } 769 } 770 771 if (pool->base.abm != NULL) 772 dce_abm_destroy(&pool->base.abm); 773 774 if (pool->base.dmcu != NULL) 775 dce_dmcu_destroy(&pool->base.dmcu); 776 777 if (pool->base.clk_mgr != NULL) 778 dce_clk_mgr_destroy(&pool->base.clk_mgr); 779 780 if (pool->base.irqs != NULL) { 781 dal_irq_service_destroy(&pool->base.irqs); 782 } 783 } 784 785 static struct clock_source *find_matching_pll( 786 struct resource_context *res_ctx, 787 const struct resource_pool *pool, 788 const struct dc_stream_state *const stream) 789 { 790 switch (stream->link->link_enc->transmitter) { 791 case TRANSMITTER_UNIPHY_A: 792 return pool->clock_sources[DCE112_CLK_SRC_PLL0]; 793 case TRANSMITTER_UNIPHY_B: 794 return pool->clock_sources[DCE112_CLK_SRC_PLL1]; 795 case TRANSMITTER_UNIPHY_C: 796 return pool->clock_sources[DCE112_CLK_SRC_PLL2]; 797 case TRANSMITTER_UNIPHY_D: 798 return pool->clock_sources[DCE112_CLK_SRC_PLL3]; 799 case TRANSMITTER_UNIPHY_E: 800 return pool->clock_sources[DCE112_CLK_SRC_PLL4]; 801 case TRANSMITTER_UNIPHY_F: 802 return pool->clock_sources[DCE112_CLK_SRC_PLL5]; 803 default: 804 return NULL; 805 }; 806 807 return 0; 808 } 809 810 static enum dc_status build_mapped_resource( 811 const struct dc *dc, 812 struct dc_state *context, 813 struct dc_stream_state *stream) 814 { 815 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 816 817 if (!pipe_ctx) 818 return DC_ERROR_UNEXPECTED; 819 820 dce110_resource_build_pipe_hw_param(pipe_ctx); 821 822 resource_build_info_frame(pipe_ctx); 823 824 return DC_OK; 825 } 826 827 bool dce112_validate_bandwidth( 828 struct dc *dc, 829 struct dc_state *context, 830 bool fast_validate) 831 { 832 bool result = false; 833 834 DC_LOG_BANDWIDTH_CALCS( 835 "%s: start", 836 __func__); 837 838 if (bw_calcs( 839 dc->ctx, 840 dc->bw_dceip, 841 dc->bw_vbios, 842 context->res_ctx.pipe_ctx, 843 dc->res_pool->pipe_count, 844 &context->bw_ctx.bw.dce)) 845 result = true; 846 847 if (!result) 848 DC_LOG_BANDWIDTH_VALIDATION( 849 "%s: Bandwidth validation failed!", 850 __func__); 851 852 if (memcmp(&dc->current_state->bw_ctx.bw.dce, 853 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { 854 855 DC_LOG_BANDWIDTH_CALCS( 856 "%s: finish,\n" 857 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 858 "stutMark_b: %d stutMark_a: %d\n" 859 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 860 "stutMark_b: %d stutMark_a: %d\n" 861 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 862 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n" 863 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" 864 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n" 865 , 866 __func__, 867 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark, 868 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark, 869 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, 870 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, 871 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark, 872 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark, 873 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark, 874 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark, 875 context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark, 876 context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark, 877 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark, 878 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark, 879 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark, 880 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark, 881 context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark, 882 context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark, 883 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark, 884 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark, 885 context->bw_ctx.bw.dce.stutter_mode_enable, 886 context->bw_ctx.bw.dce.cpuc_state_change_enable, 887 context->bw_ctx.bw.dce.cpup_state_change_enable, 888 context->bw_ctx.bw.dce.nbp_state_change_enable, 889 context->bw_ctx.bw.dce.all_displays_in_sync, 890 context->bw_ctx.bw.dce.dispclk_khz, 891 context->bw_ctx.bw.dce.sclk_khz, 892 context->bw_ctx.bw.dce.sclk_deep_sleep_khz, 893 context->bw_ctx.bw.dce.yclk_khz, 894 context->bw_ctx.bw.dce.blackout_recovery_time_us); 895 } 896 return result; 897 } 898 899 enum dc_status resource_map_phy_clock_resources( 900 const struct dc *dc, 901 struct dc_state *context, 902 struct dc_stream_state *stream) 903 { 904 905 /* acquire new resources */ 906 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( 907 &context->res_ctx, stream); 908 909 if (!pipe_ctx) 910 return DC_ERROR_UNEXPECTED; 911 912 if (dc_is_dp_signal(pipe_ctx->stream->signal) 913 || dc_is_virtual_signal(pipe_ctx->stream->signal)) 914 pipe_ctx->clock_source = 915 dc->res_pool->dp_clock_source; 916 else 917 pipe_ctx->clock_source = find_matching_pll( 918 &context->res_ctx, dc->res_pool, 919 stream); 920 921 if (pipe_ctx->clock_source == NULL) 922 return DC_NO_CLOCK_SOURCE_RESOURCE; 923 924 resource_reference_clock_source( 925 &context->res_ctx, 926 dc->res_pool, 927 pipe_ctx->clock_source); 928 929 return DC_OK; 930 } 931 932 static bool dce112_validate_surface_sets( 933 struct dc_state *context) 934 { 935 int i; 936 937 for (i = 0; i < context->stream_count; i++) { 938 if (context->stream_status[i].plane_count == 0) 939 continue; 940 941 if (context->stream_status[i].plane_count > 1) 942 return false; 943 944 if (context->stream_status[i].plane_states[0]->format 945 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 946 return false; 947 } 948 949 return true; 950 } 951 952 enum dc_status dce112_add_stream_to_ctx( 953 struct dc *dc, 954 struct dc_state *new_ctx, 955 struct dc_stream_state *dc_stream) 956 { 957 enum dc_status result = DC_ERROR_UNEXPECTED; 958 959 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 960 961 if (result == DC_OK) 962 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 963 964 965 if (result == DC_OK) 966 result = build_mapped_resource(dc, new_ctx, dc_stream); 967 968 return result; 969 } 970 971 enum dc_status dce112_validate_global( 972 struct dc *dc, 973 struct dc_state *context) 974 { 975 if (!dce112_validate_surface_sets(context)) 976 return DC_FAIL_SURFACE_VALIDATE; 977 978 return DC_OK; 979 } 980 981 static void dce112_destroy_resource_pool(struct resource_pool **pool) 982 { 983 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 984 985 destruct(dce110_pool); 986 kfree(dce110_pool); 987 *pool = NULL; 988 } 989 990 static const struct resource_funcs dce112_res_pool_funcs = { 991 .destroy = dce112_destroy_resource_pool, 992 .link_enc_create = dce112_link_encoder_create, 993 .validate_bandwidth = dce112_validate_bandwidth, 994 .validate_plane = dce100_validate_plane, 995 .add_stream_to_ctx = dce112_add_stream_to_ctx, 996 .validate_global = dce112_validate_global 997 }; 998 999 static void bw_calcs_data_update_from_pplib(struct dc *dc) 1000 { 1001 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 1002 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 1003 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; 1004 struct dm_pp_clock_levels clks = {0}; 1005 1006 /*do system clock TODO PPLIB: after PPLIB implement, 1007 * then remove old way 1008 */ 1009 if (!dm_pp_get_clock_levels_by_type_with_latency( 1010 dc->ctx, 1011 DM_PP_CLOCK_TYPE_ENGINE_CLK, 1012 &eng_clks)) { 1013 1014 /* This is only for temporary */ 1015 dm_pp_get_clock_levels_by_type( 1016 dc->ctx, 1017 DM_PP_CLOCK_TYPE_ENGINE_CLK, 1018 &clks); 1019 /* convert all the clock fro kHz to fix point mHz */ 1020 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 1021 clks.clocks_in_khz[clks.num_levels-1], 1000); 1022 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 1023 clks.clocks_in_khz[clks.num_levels/8], 1000); 1024 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 1025 clks.clocks_in_khz[clks.num_levels*2/8], 1000); 1026 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 1027 clks.clocks_in_khz[clks.num_levels*3/8], 1000); 1028 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 1029 clks.clocks_in_khz[clks.num_levels*4/8], 1000); 1030 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 1031 clks.clocks_in_khz[clks.num_levels*5/8], 1000); 1032 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1033 clks.clocks_in_khz[clks.num_levels*6/8], 1000); 1034 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1035 clks.clocks_in_khz[0], 1000); 1036 1037 /*do memory clock*/ 1038 dm_pp_get_clock_levels_by_type( 1039 dc->ctx, 1040 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1041 &clks); 1042 1043 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1044 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER_CZ, 1000); 1045 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1046 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ, 1047 1000); 1048 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1049 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER_CZ, 1050 1000); 1051 1052 return; 1053 } 1054 1055 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ 1056 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 1057 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); 1058 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 1059 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); 1060 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 1061 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); 1062 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 1063 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); 1064 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 1065 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); 1066 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 1067 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); 1068 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1069 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); 1070 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1071 eng_clks.data[0].clocks_in_khz, 1000); 1072 1073 /*do memory clock*/ 1074 dm_pp_get_clock_levels_by_type_with_latency( 1075 dc->ctx, 1076 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1077 &mem_clks); 1078 1079 /* we don't need to call PPLIB for validation clock since they 1080 * also give us the highest sclk and highest mclk (UMA clock). 1081 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): 1082 * YCLK = UMACLK*m_memoryTypeMultiplier 1083 */ 1084 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1085 mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 1000); 1086 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1087 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 1088 1000); 1089 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1090 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 1091 1000); 1092 1093 /* Now notify PPLib/SMU about which Watermarks sets they should select 1094 * depending on DPM state they are in. And update BW MGR GFX Engine and 1095 * Memory clock member variables for Watermarks calculations for each 1096 * Watermark Set 1097 */ 1098 clk_ranges.num_wm_sets = 4; 1099 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; 1100 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = 1101 eng_clks.data[0].clocks_in_khz; 1102 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = 1103 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 1104 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz = 1105 mem_clks.data[0].clocks_in_khz; 1106 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = 1107 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 1108 1109 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; 1110 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = 1111 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 1112 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 1113 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; 1114 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz = 1115 mem_clks.data[0].clocks_in_khz; 1116 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = 1117 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 1118 1119 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; 1120 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = 1121 eng_clks.data[0].clocks_in_khz; 1122 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = 1123 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 1124 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz = 1125 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 1126 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 1127 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; 1128 1129 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; 1130 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = 1131 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 1132 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 1133 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; 1134 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz = 1135 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 1136 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 1137 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; 1138 1139 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 1140 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); 1141 } 1142 1143 const struct resource_caps *dce112_resource_cap( 1144 struct hw_asic_id *asic_id) 1145 { 1146 if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) || 1147 ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev)) 1148 return &polaris_11_resource_cap; 1149 else 1150 return &polaris_10_resource_cap; 1151 } 1152 1153 static bool construct( 1154 uint8_t num_virtual_links, 1155 struct dc *dc, 1156 struct dce110_resource_pool *pool) 1157 { 1158 unsigned int i; 1159 struct dc_context *ctx = dc->ctx; 1160 1161 ctx->dc_bios->regs = &bios_regs; 1162 1163 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id); 1164 pool->base.funcs = &dce112_res_pool_funcs; 1165 1166 /************************************************* 1167 * Resource + asic cap harcoding * 1168 *************************************************/ 1169 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1170 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1171 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1172 dc->caps.max_downscale_ratio = 200; 1173 dc->caps.i2c_speed_in_khz = 100; 1174 dc->caps.max_cursor_size = 128; 1175 dc->caps.dual_link_dvi = true; 1176 1177 1178 /************************************************* 1179 * Create resources * 1180 *************************************************/ 1181 1182 pool->base.clock_sources[DCE112_CLK_SRC_PLL0] = 1183 dce112_clock_source_create( 1184 ctx, ctx->dc_bios, 1185 CLOCK_SOURCE_COMBO_PHY_PLL0, 1186 &clk_src_regs[0], false); 1187 pool->base.clock_sources[DCE112_CLK_SRC_PLL1] = 1188 dce112_clock_source_create( 1189 ctx, ctx->dc_bios, 1190 CLOCK_SOURCE_COMBO_PHY_PLL1, 1191 &clk_src_regs[1], false); 1192 pool->base.clock_sources[DCE112_CLK_SRC_PLL2] = 1193 dce112_clock_source_create( 1194 ctx, ctx->dc_bios, 1195 CLOCK_SOURCE_COMBO_PHY_PLL2, 1196 &clk_src_regs[2], false); 1197 pool->base.clock_sources[DCE112_CLK_SRC_PLL3] = 1198 dce112_clock_source_create( 1199 ctx, ctx->dc_bios, 1200 CLOCK_SOURCE_COMBO_PHY_PLL3, 1201 &clk_src_regs[3], false); 1202 pool->base.clock_sources[DCE112_CLK_SRC_PLL4] = 1203 dce112_clock_source_create( 1204 ctx, ctx->dc_bios, 1205 CLOCK_SOURCE_COMBO_PHY_PLL4, 1206 &clk_src_regs[4], false); 1207 pool->base.clock_sources[DCE112_CLK_SRC_PLL5] = 1208 dce112_clock_source_create( 1209 ctx, ctx->dc_bios, 1210 CLOCK_SOURCE_COMBO_PHY_PLL5, 1211 &clk_src_regs[5], false); 1212 pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL; 1213 1214 pool->base.dp_clock_source = dce112_clock_source_create( 1215 ctx, ctx->dc_bios, 1216 CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); 1217 1218 1219 for (i = 0; i < pool->base.clk_src_count; i++) { 1220 if (pool->base.clock_sources[i] == NULL) { 1221 dm_error("DC: failed to create clock sources!\n"); 1222 BREAK_TO_DEBUGGER(); 1223 goto res_create_fail; 1224 } 1225 } 1226 1227 pool->base.clk_mgr = dce112_clk_mgr_create(ctx, 1228 &disp_clk_regs, 1229 &disp_clk_shift, 1230 &disp_clk_mask); 1231 if (pool->base.clk_mgr == NULL) { 1232 dm_error("DC: failed to create display clock!\n"); 1233 BREAK_TO_DEBUGGER(); 1234 goto res_create_fail; 1235 } 1236 1237 pool->base.dmcu = dce_dmcu_create(ctx, 1238 &dmcu_regs, 1239 &dmcu_shift, 1240 &dmcu_mask); 1241 if (pool->base.dmcu == NULL) { 1242 dm_error("DC: failed to create dmcu!\n"); 1243 BREAK_TO_DEBUGGER(); 1244 goto res_create_fail; 1245 } 1246 1247 pool->base.abm = dce_abm_create(ctx, 1248 &abm_regs, 1249 &abm_shift, 1250 &abm_mask); 1251 if (pool->base.abm == NULL) { 1252 dm_error("DC: failed to create abm!\n"); 1253 BREAK_TO_DEBUGGER(); 1254 goto res_create_fail; 1255 } 1256 1257 { 1258 struct irq_service_init_data init_data; 1259 init_data.ctx = dc->ctx; 1260 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 1261 if (!pool->base.irqs) 1262 goto res_create_fail; 1263 } 1264 1265 for (i = 0; i < pool->base.pipe_count; i++) { 1266 pool->base.timing_generators[i] = 1267 dce112_timing_generator_create( 1268 ctx, 1269 i, 1270 &dce112_tg_offsets[i]); 1271 if (pool->base.timing_generators[i] == NULL) { 1272 BREAK_TO_DEBUGGER(); 1273 dm_error("DC: failed to create tg!\n"); 1274 goto res_create_fail; 1275 } 1276 1277 pool->base.mis[i] = dce112_mem_input_create(ctx, i); 1278 if (pool->base.mis[i] == NULL) { 1279 BREAK_TO_DEBUGGER(); 1280 dm_error( 1281 "DC: failed to create memory input!\n"); 1282 goto res_create_fail; 1283 } 1284 1285 pool->base.ipps[i] = dce112_ipp_create(ctx, i); 1286 if (pool->base.ipps[i] == NULL) { 1287 BREAK_TO_DEBUGGER(); 1288 dm_error( 1289 "DC:failed to create input pixel processor!\n"); 1290 goto res_create_fail; 1291 } 1292 1293 pool->base.transforms[i] = dce112_transform_create(ctx, i); 1294 if (pool->base.transforms[i] == NULL) { 1295 BREAK_TO_DEBUGGER(); 1296 dm_error( 1297 "DC: failed to create transform!\n"); 1298 goto res_create_fail; 1299 } 1300 1301 pool->base.opps[i] = dce112_opp_create( 1302 ctx, 1303 i); 1304 if (pool->base.opps[i] == NULL) { 1305 BREAK_TO_DEBUGGER(); 1306 dm_error( 1307 "DC:failed to create output pixel processor!\n"); 1308 goto res_create_fail; 1309 } 1310 } 1311 1312 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1313 pool->base.engines[i] = dce112_aux_engine_create(ctx, i); 1314 if (pool->base.engines[i] == NULL) { 1315 BREAK_TO_DEBUGGER(); 1316 dm_error( 1317 "DC:failed to create aux engine!!\n"); 1318 goto res_create_fail; 1319 } 1320 pool->base.hw_i2cs[i] = dce112_i2c_hw_create(ctx, i); 1321 if (pool->base.hw_i2cs[i] == NULL) { 1322 BREAK_TO_DEBUGGER(); 1323 dm_error( 1324 "DC:failed to create i2c engine!!\n"); 1325 goto res_create_fail; 1326 } 1327 pool->base.sw_i2cs[i] = NULL; 1328 } 1329 1330 if (!resource_construct(num_virtual_links, dc, &pool->base, 1331 &res_create_funcs)) 1332 goto res_create_fail; 1333 1334 dc->caps.max_planes = pool->base.pipe_count; 1335 1336 for (i = 0; i < dc->caps.max_planes; ++i) 1337 dc->caps.planes[i] = plane_cap; 1338 1339 /* Create hardware sequencer */ 1340 dce112_hw_sequencer_construct(dc); 1341 1342 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1343 1344 bw_calcs_data_update_from_pplib(dc); 1345 1346 return true; 1347 1348 res_create_fail: 1349 destruct(pool); 1350 return false; 1351 } 1352 1353 struct resource_pool *dce112_create_resource_pool( 1354 uint8_t num_virtual_links, 1355 struct dc *dc) 1356 { 1357 struct dce110_resource_pool *pool = 1358 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1359 1360 if (!pool) 1361 return NULL; 1362 1363 if (construct(num_virtual_links, dc, pool)) 1364 return &pool->base; 1365 1366 BREAK_TO_DEBUGGER(); 1367 return NULL; 1368 } 1369