1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include <linux/slab.h>
27 
28 #include "dm_services.h"
29 
30 #include "link_encoder.h"
31 #include "stream_encoder.h"
32 
33 #include "resource.h"
34 #include "include/irq_service_interface.h"
35 #include "dce110/dce110_resource.h"
36 #include "dce110/dce110_timing_generator.h"
37 
38 #include "irq/dce110/irq_service_dce110.h"
39 #include "dce/dce_mem_input.h"
40 #include "dce/dce_transform.h"
41 #include "dce/dce_link_encoder.h"
42 #include "dce/dce_stream_encoder.h"
43 #include "dce/dce_audio.h"
44 #include "dce/dce_opp.h"
45 #include "dce/dce_ipp.h"
46 #include "dce/dce_clock_source.h"
47 
48 #include "dce/dce_hwseq.h"
49 #include "dce112/dce112_hw_sequencer.h"
50 #include "dce/dce_abm.h"
51 #include "dce/dce_dmcu.h"
52 #include "dce/dce_aux.h"
53 #include "dce/dce_i2c.h"
54 #include "dce/dce_panel_cntl.h"
55 
56 #include "reg_helper.h"
57 
58 #include "dce/dce_11_2_d.h"
59 #include "dce/dce_11_2_sh_mask.h"
60 
61 #include "dce100/dce100_resource.h"
62 #define DC_LOGGER \
63 		dc->ctx->logger
64 
65 #ifndef mmDP_DPHY_INTERNAL_CTRL
66 	#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
67 	#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
68 	#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
69 	#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
70 	#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
71 	#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
72 	#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
73 	#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
74 	#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
75 	#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
76 #endif
77 
78 #ifndef mmBIOS_SCRATCH_2
79 	#define mmBIOS_SCRATCH_2 0x05CB
80 	#define mmBIOS_SCRATCH_3 0x05CC
81 	#define mmBIOS_SCRATCH_6 0x05CF
82 #endif
83 
84 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
85 	#define mmDP_DPHY_BS_SR_SWAP_CNTL                       0x4ADC
86 	#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                   0x4ADC
87 	#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                   0x4BDC
88 	#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                   0x4CDC
89 	#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                   0x4DDC
90 	#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                   0x4EDC
91 	#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL                   0x4FDC
92 	#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL                   0x54DC
93 #endif
94 
95 #ifndef mmDP_DPHY_FAST_TRAINING
96 	#define mmDP_DPHY_FAST_TRAINING                         0x4ABC
97 	#define mmDP0_DP_DPHY_FAST_TRAINING                     0x4ABC
98 	#define mmDP1_DP_DPHY_FAST_TRAINING                     0x4BBC
99 	#define mmDP2_DP_DPHY_FAST_TRAINING                     0x4CBC
100 	#define mmDP3_DP_DPHY_FAST_TRAINING                     0x4DBC
101 	#define mmDP4_DP_DPHY_FAST_TRAINING                     0x4EBC
102 	#define mmDP5_DP_DPHY_FAST_TRAINING                     0x4FBC
103 	#define mmDP6_DP_DPHY_FAST_TRAINING                     0x54BC
104 #endif
105 
106 enum dce112_clk_src_array_id {
107 	DCE112_CLK_SRC_PLL0,
108 	DCE112_CLK_SRC_PLL1,
109 	DCE112_CLK_SRC_PLL2,
110 	DCE112_CLK_SRC_PLL3,
111 	DCE112_CLK_SRC_PLL4,
112 	DCE112_CLK_SRC_PLL5,
113 
114 	DCE112_CLK_SRC_TOTAL
115 };
116 
117 static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = {
118 	{
119 		.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
120 		.dcp =  (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
121 	},
122 	{
123 		.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
124 		.dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
125 	},
126 	{
127 		.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
128 		.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
129 	},
130 	{
131 		.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
132 		.dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
133 	},
134 	{
135 		.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
136 		.dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
137 	},
138 	{
139 		.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
140 		.dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
141 	}
142 };
143 
144 /* set register offset */
145 #define SR(reg_name)\
146 	.reg_name = mm ## reg_name
147 
148 /* set register offset with instance */
149 #define SRI(reg_name, block, id)\
150 	.reg_name = mm ## block ## id ## _ ## reg_name
151 
152 static const struct dce_dmcu_registers dmcu_regs = {
153 		DMCU_DCE110_COMMON_REG_LIST()
154 };
155 
156 static const struct dce_dmcu_shift dmcu_shift = {
157 		DMCU_MASK_SH_LIST_DCE110(__SHIFT)
158 };
159 
160 static const struct dce_dmcu_mask dmcu_mask = {
161 		DMCU_MASK_SH_LIST_DCE110(_MASK)
162 };
163 
164 static const struct dce_abm_registers abm_regs = {
165 		ABM_DCE110_COMMON_REG_LIST()
166 };
167 
168 static const struct dce_abm_shift abm_shift = {
169 		ABM_MASK_SH_LIST_DCE110(__SHIFT)
170 };
171 
172 static const struct dce_abm_mask abm_mask = {
173 		ABM_MASK_SH_LIST_DCE110(_MASK)
174 };
175 
176 static const struct dce110_aux_registers_shift aux_shift = {
177 	DCE_AUX_MASK_SH_LIST(__SHIFT)
178 };
179 
180 static const struct dce110_aux_registers_mask aux_mask = {
181 	DCE_AUX_MASK_SH_LIST(_MASK)
182 };
183 
184 #define ipp_regs(id)\
185 [id] = {\
186 		IPP_DCE110_REG_LIST_DCE_BASE(id)\
187 }
188 
189 static const struct dce_ipp_registers ipp_regs[] = {
190 		ipp_regs(0),
191 		ipp_regs(1),
192 		ipp_regs(2),
193 		ipp_regs(3),
194 		ipp_regs(4),
195 		ipp_regs(5)
196 };
197 
198 static const struct dce_ipp_shift ipp_shift = {
199 		IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
200 };
201 
202 static const struct dce_ipp_mask ipp_mask = {
203 		IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
204 };
205 
206 #define transform_regs(id)\
207 [id] = {\
208 		XFM_COMMON_REG_LIST_DCE110(id)\
209 }
210 
211 static const struct dce_transform_registers xfm_regs[] = {
212 		transform_regs(0),
213 		transform_regs(1),
214 		transform_regs(2),
215 		transform_regs(3),
216 		transform_regs(4),
217 		transform_regs(5)
218 };
219 
220 static const struct dce_transform_shift xfm_shift = {
221 		XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
222 };
223 
224 static const struct dce_transform_mask xfm_mask = {
225 		XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
226 };
227 
228 #define aux_regs(id)\
229 [id] = {\
230 	AUX_REG_LIST(id)\
231 }
232 
233 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
234 		aux_regs(0),
235 		aux_regs(1),
236 		aux_regs(2),
237 		aux_regs(3),
238 		aux_regs(4),
239 		aux_regs(5)
240 };
241 
242 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
243 	{ DCE_PANEL_CNTL_REG_LIST() }
244 };
245 
246 static const struct dce_panel_cntl_shift panel_cntl_shift = {
247 	DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
248 };
249 
250 static const struct dce_panel_cntl_mask panel_cntl_mask = {
251 	DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
252 };
253 
254 #define hpd_regs(id)\
255 [id] = {\
256 	HPD_REG_LIST(id)\
257 }
258 
259 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
260 		hpd_regs(0),
261 		hpd_regs(1),
262 		hpd_regs(2),
263 		hpd_regs(3),
264 		hpd_regs(4),
265 		hpd_regs(5)
266 };
267 
268 #define link_regs(id)\
269 [id] = {\
270 	LE_DCE110_REG_LIST(id)\
271 }
272 
273 static const struct dce110_link_enc_registers link_enc_regs[] = {
274 	link_regs(0),
275 	link_regs(1),
276 	link_regs(2),
277 	link_regs(3),
278 	link_regs(4),
279 	link_regs(5),
280 	link_regs(6),
281 };
282 
283 #define stream_enc_regs(id)\
284 [id] = {\
285 	SE_COMMON_REG_LIST(id),\
286 	.TMDS_CNTL = 0,\
287 }
288 
289 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
290 	stream_enc_regs(0),
291 	stream_enc_regs(1),
292 	stream_enc_regs(2),
293 	stream_enc_regs(3),
294 	stream_enc_regs(4),
295 	stream_enc_regs(5)
296 };
297 
298 static const struct dce_stream_encoder_shift se_shift = {
299 		SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT)
300 };
301 
302 static const struct dce_stream_encoder_mask se_mask = {
303 		SE_COMMON_MASK_SH_LIST_DCE112(_MASK)
304 };
305 
306 #define opp_regs(id)\
307 [id] = {\
308 	OPP_DCE_112_REG_LIST(id),\
309 }
310 
311 static const struct dce_opp_registers opp_regs[] = {
312 	opp_regs(0),
313 	opp_regs(1),
314 	opp_regs(2),
315 	opp_regs(3),
316 	opp_regs(4),
317 	opp_regs(5)
318 };
319 
320 static const struct dce_opp_shift opp_shift = {
321 	OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
322 };
323 
324 static const struct dce_opp_mask opp_mask = {
325 	OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK)
326 };
327 
328 #define aux_engine_regs(id)\
329 [id] = {\
330 	AUX_COMMON_REG_LIST(id), \
331 	.AUX_RESET_MASK = 0 \
332 }
333 
334 static const struct dce110_aux_registers aux_engine_regs[] = {
335 		aux_engine_regs(0),
336 		aux_engine_regs(1),
337 		aux_engine_regs(2),
338 		aux_engine_regs(3),
339 		aux_engine_regs(4),
340 		aux_engine_regs(5)
341 };
342 
343 #define audio_regs(id)\
344 [id] = {\
345 	AUD_COMMON_REG_LIST(id)\
346 }
347 
348 static const struct dce_audio_registers audio_regs[] = {
349 	audio_regs(0),
350 	audio_regs(1),
351 	audio_regs(2),
352 	audio_regs(3),
353 	audio_regs(4),
354 	audio_regs(5)
355 };
356 
357 static const struct dce_audio_shift audio_shift = {
358 		AUD_COMMON_MASK_SH_LIST(__SHIFT)
359 };
360 
361 static const struct dce_audio_mask audio_mask = {
362 		AUD_COMMON_MASK_SH_LIST(_MASK)
363 };
364 
365 #define clk_src_regs(index, id)\
366 [index] = {\
367 	CS_COMMON_REG_LIST_DCE_112(id),\
368 }
369 
370 static const struct dce110_clk_src_regs clk_src_regs[] = {
371 	clk_src_regs(0, A),
372 	clk_src_regs(1, B),
373 	clk_src_regs(2, C),
374 	clk_src_regs(3, D),
375 	clk_src_regs(4, E),
376 	clk_src_regs(5, F)
377 };
378 
379 static const struct dce110_clk_src_shift cs_shift = {
380 		CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
381 };
382 
383 static const struct dce110_clk_src_mask cs_mask = {
384 		CS_COMMON_MASK_SH_LIST_DCE_112(_MASK)
385 };
386 
387 static const struct bios_registers bios_regs = {
388 	.BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
389 	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
390 };
391 
392 static const struct resource_caps polaris_10_resource_cap = {
393 		.num_timing_generator = 6,
394 		.num_audio = 6,
395 		.num_stream_encoder = 6,
396 		.num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
397 		.num_ddc = 6,
398 };
399 
400 static const struct resource_caps polaris_11_resource_cap = {
401 		.num_timing_generator = 5,
402 		.num_audio = 5,
403 		.num_stream_encoder = 5,
404 		.num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
405 		.num_ddc = 5,
406 };
407 
408 static const struct dc_plane_cap plane_cap = {
409 	.type = DC_PLANE_TYPE_DCE_RGB,
410 
411 	.pixel_format_support = {
412 			.argb8888 = true,
413 			.nv12 = false,
414 			.fp16 = true
415 	},
416 
417 	.max_upscale_factor = {
418 			.argb8888 = 16000,
419 			.nv12 = 1,
420 			.fp16 = 1
421 	},
422 
423 	.max_downscale_factor = {
424 			.argb8888 = 250,
425 			.nv12 = 1,
426 			.fp16 = 1
427 	},
428 	64,
429 	64
430 };
431 
432 #define CTX  ctx
433 #define REG(reg) mm ## reg
434 
435 #ifndef mmCC_DC_HDMI_STRAPS
436 #define mmCC_DC_HDMI_STRAPS 0x4819
437 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
438 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
439 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
440 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
441 #endif
442 
443 static int map_transmitter_id_to_phy_instance(
444 	enum transmitter transmitter)
445 {
446 	switch (transmitter) {
447 	case TRANSMITTER_UNIPHY_A:
448 		return 0;
449 	case TRANSMITTER_UNIPHY_B:
450 		return 1;
451 	case TRANSMITTER_UNIPHY_C:
452 		return 2;
453 	case TRANSMITTER_UNIPHY_D:
454 		return 3;
455 	case TRANSMITTER_UNIPHY_E:
456 		return 4;
457 	case TRANSMITTER_UNIPHY_F:
458 		return 5;
459 	case TRANSMITTER_UNIPHY_G:
460 		return 6;
461 	default:
462 		ASSERT(0);
463 		return 0;
464 	}
465 }
466 
467 static void read_dce_straps(
468 	struct dc_context *ctx,
469 	struct resource_straps *straps)
470 {
471 	REG_GET_2(CC_DC_HDMI_STRAPS,
472 			HDMI_DISABLE, &straps->hdmi_disable,
473 			AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
474 
475 	REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
476 }
477 
478 static struct audio *create_audio(
479 		struct dc_context *ctx, unsigned int inst)
480 {
481 	return dce_audio_create(ctx, inst,
482 			&audio_regs[inst], &audio_shift, &audio_mask);
483 }
484 
485 
486 static struct timing_generator *dce112_timing_generator_create(
487 		struct dc_context *ctx,
488 		uint32_t instance,
489 		const struct dce110_timing_generator_offsets *offsets)
490 {
491 	struct dce110_timing_generator *tg110 =
492 		kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
493 
494 	if (!tg110)
495 		return NULL;
496 
497 	dce110_timing_generator_construct(tg110, ctx, instance, offsets);
498 	return &tg110->base;
499 }
500 
501 static struct stream_encoder *dce112_stream_encoder_create(
502 	enum engine_id eng_id,
503 	struct dc_context *ctx)
504 {
505 	struct dce110_stream_encoder *enc110 =
506 		kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
507 
508 	if (!enc110)
509 		return NULL;
510 
511 	dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
512 					&stream_enc_regs[eng_id],
513 					&se_shift, &se_mask);
514 	return &enc110->base;
515 }
516 
517 #define SRII(reg_name, block, id)\
518 	.reg_name[id] = mm ## block ## id ## _ ## reg_name
519 
520 static const struct dce_hwseq_registers hwseq_reg = {
521 		HWSEQ_DCE112_REG_LIST()
522 };
523 
524 static const struct dce_hwseq_shift hwseq_shift = {
525 		HWSEQ_DCE112_MASK_SH_LIST(__SHIFT)
526 };
527 
528 static const struct dce_hwseq_mask hwseq_mask = {
529 		HWSEQ_DCE112_MASK_SH_LIST(_MASK)
530 };
531 
532 static struct dce_hwseq *dce112_hwseq_create(
533 	struct dc_context *ctx)
534 {
535 	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
536 
537 	if (hws) {
538 		hws->ctx = ctx;
539 		hws->regs = &hwseq_reg;
540 		hws->shifts = &hwseq_shift;
541 		hws->masks = &hwseq_mask;
542 	}
543 	return hws;
544 }
545 
546 static const struct resource_create_funcs res_create_funcs = {
547 	.read_dce_straps = read_dce_straps,
548 	.create_audio = create_audio,
549 	.create_stream_encoder = dce112_stream_encoder_create,
550 	.create_hwseq = dce112_hwseq_create,
551 };
552 
553 #define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) }
554 static const struct dce_mem_input_registers mi_regs[] = {
555 		mi_inst_regs(0),
556 		mi_inst_regs(1),
557 		mi_inst_regs(2),
558 		mi_inst_regs(3),
559 		mi_inst_regs(4),
560 		mi_inst_regs(5),
561 };
562 
563 static const struct dce_mem_input_shift mi_shifts = {
564 		MI_DCE11_2_MASK_SH_LIST(__SHIFT)
565 };
566 
567 static const struct dce_mem_input_mask mi_masks = {
568 		MI_DCE11_2_MASK_SH_LIST(_MASK)
569 };
570 
571 static struct mem_input *dce112_mem_input_create(
572 	struct dc_context *ctx,
573 	uint32_t inst)
574 {
575 	struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
576 					       GFP_KERNEL);
577 
578 	if (!dce_mi) {
579 		BREAK_TO_DEBUGGER();
580 		return NULL;
581 	}
582 
583 	dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
584 	return &dce_mi->base;
585 }
586 
587 static void dce112_transform_destroy(struct transform **xfm)
588 {
589 	kfree(TO_DCE_TRANSFORM(*xfm));
590 	*xfm = NULL;
591 }
592 
593 static struct transform *dce112_transform_create(
594 	struct dc_context *ctx,
595 	uint32_t inst)
596 {
597 	struct dce_transform *transform =
598 		kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
599 
600 	if (!transform)
601 		return NULL;
602 
603 	dce_transform_construct(transform, ctx, inst,
604 				&xfm_regs[inst], &xfm_shift, &xfm_mask);
605 	transform->lb_memory_size = 0x1404; /*5124*/
606 	return &transform->base;
607 }
608 
609 static const struct encoder_feature_support link_enc_feature = {
610 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
611 		.max_hdmi_pixel_clock = 600000,
612 		.hdmi_ycbcr420_supported = true,
613 		.dp_ycbcr420_supported = false,
614 		.flags.bits.IS_HBR2_CAPABLE = true,
615 		.flags.bits.IS_HBR3_CAPABLE = true,
616 		.flags.bits.IS_TPS3_CAPABLE = true,
617 		.flags.bits.IS_TPS4_CAPABLE = true
618 };
619 
620 struct link_encoder *dce112_link_encoder_create(
621 	const struct encoder_init_data *enc_init_data)
622 {
623 	struct dce110_link_encoder *enc110 =
624 		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
625 	int link_regs_id;
626 
627 	if (!enc110)
628 		return NULL;
629 
630 	link_regs_id =
631 		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
632 
633 	dce110_link_encoder_construct(enc110,
634 				      enc_init_data,
635 				      &link_enc_feature,
636 				      &link_enc_regs[link_regs_id],
637 				      &link_enc_aux_regs[enc_init_data->channel - 1],
638 				      &link_enc_hpd_regs[enc_init_data->hpd_source]);
639 	return &enc110->base;
640 }
641 
642 static struct panel_cntl *dce112_panel_cntl_create(const struct panel_cntl_init_data *init_data)
643 {
644 	struct dce_panel_cntl *panel_cntl =
645 		kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
646 
647 	if (!panel_cntl)
648 		return NULL;
649 
650 	dce_panel_cntl_construct(panel_cntl,
651 			init_data,
652 			&panel_cntl_regs[init_data->inst],
653 			&panel_cntl_shift,
654 			&panel_cntl_mask);
655 
656 	return &panel_cntl->base;
657 }
658 
659 static struct input_pixel_processor *dce112_ipp_create(
660 	struct dc_context *ctx, uint32_t inst)
661 {
662 	struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
663 
664 	if (!ipp) {
665 		BREAK_TO_DEBUGGER();
666 		return NULL;
667 	}
668 
669 	dce_ipp_construct(ipp, ctx, inst,
670 			&ipp_regs[inst], &ipp_shift, &ipp_mask);
671 	return &ipp->base;
672 }
673 
674 struct output_pixel_processor *dce112_opp_create(
675 	struct dc_context *ctx,
676 	uint32_t inst)
677 {
678 	struct dce110_opp *opp =
679 		kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
680 
681 	if (!opp)
682 		return NULL;
683 
684 	dce110_opp_construct(opp,
685 			     ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
686 	return &opp->base;
687 }
688 
689 struct dce_aux *dce112_aux_engine_create(
690 	struct dc_context *ctx,
691 	uint32_t inst)
692 {
693 	struct aux_engine_dce110 *aux_engine =
694 		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
695 
696 	if (!aux_engine)
697 		return NULL;
698 
699 	dce110_aux_engine_construct(aux_engine, ctx, inst,
700 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
701 				    &aux_engine_regs[inst],
702 					&aux_mask,
703 					&aux_shift,
704 					ctx->dc->caps.extended_aux_timeout_support);
705 
706 	return &aux_engine->base;
707 }
708 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
709 
710 static const struct dce_i2c_registers i2c_hw_regs[] = {
711 		i2c_inst_regs(1),
712 		i2c_inst_regs(2),
713 		i2c_inst_regs(3),
714 		i2c_inst_regs(4),
715 		i2c_inst_regs(5),
716 		i2c_inst_regs(6),
717 };
718 
719 static const struct dce_i2c_shift i2c_shifts = {
720 		I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
721 };
722 
723 static const struct dce_i2c_mask i2c_masks = {
724 		I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
725 };
726 
727 struct dce_i2c_hw *dce112_i2c_hw_create(
728 	struct dc_context *ctx,
729 	uint32_t inst)
730 {
731 	struct dce_i2c_hw *dce_i2c_hw =
732 		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
733 
734 	if (!dce_i2c_hw)
735 		return NULL;
736 
737 	dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,
738 				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
739 
740 	return dce_i2c_hw;
741 }
742 struct clock_source *dce112_clock_source_create(
743 	struct dc_context *ctx,
744 	struct dc_bios *bios,
745 	enum clock_source_id id,
746 	const struct dce110_clk_src_regs *regs,
747 	bool dp_clk_src)
748 {
749 	struct dce110_clk_src *clk_src =
750 		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
751 
752 	if (!clk_src)
753 		return NULL;
754 
755 	if (dce112_clk_src_construct(clk_src, ctx, bios, id,
756 			regs, &cs_shift, &cs_mask)) {
757 		clk_src->base.dp_clk_src = dp_clk_src;
758 		return &clk_src->base;
759 	}
760 
761 	kfree(clk_src);
762 	BREAK_TO_DEBUGGER();
763 	return NULL;
764 }
765 
766 void dce112_clock_source_destroy(struct clock_source **clk_src)
767 {
768 	kfree(TO_DCE110_CLK_SRC(*clk_src));
769 	*clk_src = NULL;
770 }
771 
772 static void dce112_resource_destruct(struct dce110_resource_pool *pool)
773 {
774 	unsigned int i;
775 
776 	for (i = 0; i < pool->base.pipe_count; i++) {
777 		if (pool->base.opps[i] != NULL)
778 			dce110_opp_destroy(&pool->base.opps[i]);
779 
780 		if (pool->base.transforms[i] != NULL)
781 			dce112_transform_destroy(&pool->base.transforms[i]);
782 
783 		if (pool->base.ipps[i] != NULL)
784 			dce_ipp_destroy(&pool->base.ipps[i]);
785 
786 		if (pool->base.mis[i] != NULL) {
787 			kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
788 			pool->base.mis[i] = NULL;
789 		}
790 
791 		if (pool->base.timing_generators[i] != NULL) {
792 			kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
793 			pool->base.timing_generators[i] = NULL;
794 		}
795 	}
796 
797 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
798 		if (pool->base.engines[i] != NULL)
799 			dce110_engine_destroy(&pool->base.engines[i]);
800 		if (pool->base.hw_i2cs[i] != NULL) {
801 			kfree(pool->base.hw_i2cs[i]);
802 			pool->base.hw_i2cs[i] = NULL;
803 		}
804 		if (pool->base.sw_i2cs[i] != NULL) {
805 			kfree(pool->base.sw_i2cs[i]);
806 			pool->base.sw_i2cs[i] = NULL;
807 		}
808 	}
809 
810 	for (i = 0; i < pool->base.stream_enc_count; i++) {
811 		if (pool->base.stream_enc[i] != NULL)
812 			kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
813 	}
814 
815 	for (i = 0; i < pool->base.clk_src_count; i++) {
816 		if (pool->base.clock_sources[i] != NULL) {
817 			dce112_clock_source_destroy(&pool->base.clock_sources[i]);
818 		}
819 	}
820 
821 	if (pool->base.dp_clock_source != NULL)
822 		dce112_clock_source_destroy(&pool->base.dp_clock_source);
823 
824 	for (i = 0; i < pool->base.audio_count; i++)	{
825 		if (pool->base.audios[i] != NULL) {
826 			dce_aud_destroy(&pool->base.audios[i]);
827 		}
828 	}
829 
830 	if (pool->base.abm != NULL)
831 		dce_abm_destroy(&pool->base.abm);
832 
833 	if (pool->base.dmcu != NULL)
834 		dce_dmcu_destroy(&pool->base.dmcu);
835 
836 	if (pool->base.irqs != NULL) {
837 		dal_irq_service_destroy(&pool->base.irqs);
838 	}
839 }
840 
841 static struct clock_source *find_matching_pll(
842 		struct resource_context *res_ctx,
843 		const struct resource_pool *pool,
844 		const struct dc_stream_state *const stream)
845 {
846 	switch (stream->link->link_enc->transmitter) {
847 	case TRANSMITTER_UNIPHY_A:
848 		return pool->clock_sources[DCE112_CLK_SRC_PLL0];
849 	case TRANSMITTER_UNIPHY_B:
850 		return pool->clock_sources[DCE112_CLK_SRC_PLL1];
851 	case TRANSMITTER_UNIPHY_C:
852 		return pool->clock_sources[DCE112_CLK_SRC_PLL2];
853 	case TRANSMITTER_UNIPHY_D:
854 		return pool->clock_sources[DCE112_CLK_SRC_PLL3];
855 	case TRANSMITTER_UNIPHY_E:
856 		return pool->clock_sources[DCE112_CLK_SRC_PLL4];
857 	case TRANSMITTER_UNIPHY_F:
858 		return pool->clock_sources[DCE112_CLK_SRC_PLL5];
859 	default:
860 		return NULL;
861 	};
862 
863 	return 0;
864 }
865 
866 static enum dc_status build_mapped_resource(
867 		const struct dc *dc,
868 		struct dc_state *context,
869 		struct dc_stream_state *stream)
870 {
871 	struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
872 
873 	if (!pipe_ctx)
874 		return DC_ERROR_UNEXPECTED;
875 
876 	dce110_resource_build_pipe_hw_param(pipe_ctx);
877 
878 	resource_build_info_frame(pipe_ctx);
879 
880 	return DC_OK;
881 }
882 
883 bool dce112_validate_bandwidth(
884 	struct dc *dc,
885 	struct dc_state *context,
886 	bool fast_validate)
887 {
888 	bool result = false;
889 
890 	DC_LOG_BANDWIDTH_CALCS(
891 		"%s: start",
892 		__func__);
893 
894 	if (bw_calcs(
895 			dc->ctx,
896 			dc->bw_dceip,
897 			dc->bw_vbios,
898 			context->res_ctx.pipe_ctx,
899 			dc->res_pool->pipe_count,
900 			&context->bw_ctx.bw.dce))
901 		result = true;
902 
903 	if (!result)
904 		DC_LOG_BANDWIDTH_VALIDATION(
905 			"%s: Bandwidth validation failed!",
906 			__func__);
907 
908 	if (memcmp(&dc->current_state->bw_ctx.bw.dce,
909 			&context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) {
910 
911 		DC_LOG_BANDWIDTH_CALCS(
912 			"%s: finish,\n"
913 			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
914 			"stutMark_b: %d stutMark_a: %d\n"
915 			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
916 			"stutMark_b: %d stutMark_a: %d\n"
917 			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
918 			"stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n"
919 			"cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
920 			"sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n"
921 			,
922 			__func__,
923 			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark,
924 			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark,
925 			context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark,
926 			context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark,
927 			context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark,
928 			context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark,
929 			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark,
930 			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark,
931 			context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark,
932 			context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark,
933 			context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark,
934 			context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark,
935 			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark,
936 			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark,
937 			context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark,
938 			context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark,
939 			context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark,
940 			context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark,
941 			context->bw_ctx.bw.dce.stutter_mode_enable,
942 			context->bw_ctx.bw.dce.cpuc_state_change_enable,
943 			context->bw_ctx.bw.dce.cpup_state_change_enable,
944 			context->bw_ctx.bw.dce.nbp_state_change_enable,
945 			context->bw_ctx.bw.dce.all_displays_in_sync,
946 			context->bw_ctx.bw.dce.dispclk_khz,
947 			context->bw_ctx.bw.dce.sclk_khz,
948 			context->bw_ctx.bw.dce.sclk_deep_sleep_khz,
949 			context->bw_ctx.bw.dce.yclk_khz,
950 			context->bw_ctx.bw.dce.blackout_recovery_time_us);
951 	}
952 	return result;
953 }
954 
955 enum dc_status resource_map_phy_clock_resources(
956 		const struct dc *dc,
957 		struct dc_state *context,
958 		struct dc_stream_state *stream)
959 {
960 
961 	/* acquire new resources */
962 	struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
963 			&context->res_ctx, stream);
964 
965 	if (!pipe_ctx)
966 		return DC_ERROR_UNEXPECTED;
967 
968 	if (dc_is_dp_signal(pipe_ctx->stream->signal)
969 		|| dc_is_virtual_signal(pipe_ctx->stream->signal))
970 		pipe_ctx->clock_source =
971 				dc->res_pool->dp_clock_source;
972 	else
973 		pipe_ctx->clock_source = find_matching_pll(
974 			&context->res_ctx, dc->res_pool,
975 			stream);
976 
977 	if (pipe_ctx->clock_source == NULL)
978 		return DC_NO_CLOCK_SOURCE_RESOURCE;
979 
980 	resource_reference_clock_source(
981 		&context->res_ctx,
982 		dc->res_pool,
983 		pipe_ctx->clock_source);
984 
985 	return DC_OK;
986 }
987 
988 static bool dce112_validate_surface_sets(
989 		struct dc_state *context)
990 {
991 	int i;
992 
993 	for (i = 0; i < context->stream_count; i++) {
994 		if (context->stream_status[i].plane_count == 0)
995 			continue;
996 
997 		if (context->stream_status[i].plane_count > 1)
998 			return false;
999 
1000 		if (context->stream_status[i].plane_states[0]->format
1001 				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
1002 			return false;
1003 	}
1004 
1005 	return true;
1006 }
1007 
1008 enum dc_status dce112_add_stream_to_ctx(
1009 		struct dc *dc,
1010 		struct dc_state *new_ctx,
1011 		struct dc_stream_state *dc_stream)
1012 {
1013 	enum dc_status result;
1014 
1015 	result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1016 
1017 	if (result == DC_OK)
1018 		result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1019 
1020 
1021 	if (result == DC_OK)
1022 		result = build_mapped_resource(dc, new_ctx, dc_stream);
1023 
1024 	return result;
1025 }
1026 
1027 enum dc_status dce112_validate_global(
1028 		struct dc *dc,
1029 		struct dc_state *context)
1030 {
1031 	if (!dce112_validate_surface_sets(context))
1032 		return DC_FAIL_SURFACE_VALIDATE;
1033 
1034 	return DC_OK;
1035 }
1036 
1037 static void dce112_destroy_resource_pool(struct resource_pool **pool)
1038 {
1039 	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
1040 
1041 	dce112_resource_destruct(dce110_pool);
1042 	kfree(dce110_pool);
1043 	*pool = NULL;
1044 }
1045 
1046 static const struct resource_funcs dce112_res_pool_funcs = {
1047 	.destroy = dce112_destroy_resource_pool,
1048 	.link_enc_create = dce112_link_encoder_create,
1049 	.panel_cntl_create = dce112_panel_cntl_create,
1050 	.validate_bandwidth = dce112_validate_bandwidth,
1051 	.validate_plane = dce100_validate_plane,
1052 	.add_stream_to_ctx = dce112_add_stream_to_ctx,
1053 	.validate_global = dce112_validate_global,
1054 	.find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link
1055 };
1056 
1057 static void bw_calcs_data_update_from_pplib(struct dc *dc)
1058 {
1059 	struct dm_pp_clock_levels_with_latency eng_clks = {0};
1060 	struct dm_pp_clock_levels_with_latency mem_clks = {0};
1061 	struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
1062 	struct dm_pp_clock_levels clks = {0};
1063 	int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ;
1064 
1065 	if (dc->bw_vbios && dc->bw_vbios->memory_type == bw_def_hbm)
1066 		memory_type_multiplier = MEMORY_TYPE_HBM;
1067 
1068 	/*do system clock  TODO PPLIB: after PPLIB implement,
1069 	 * then remove old way
1070 	 */
1071 	if (!dm_pp_get_clock_levels_by_type_with_latency(
1072 			dc->ctx,
1073 			DM_PP_CLOCK_TYPE_ENGINE_CLK,
1074 			&eng_clks)) {
1075 
1076 		/* This is only for temporary */
1077 		dm_pp_get_clock_levels_by_type(
1078 				dc->ctx,
1079 				DM_PP_CLOCK_TYPE_ENGINE_CLK,
1080 				&clks);
1081 		/* convert all the clock fro kHz to fix point mHz */
1082 		dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1083 				clks.clocks_in_khz[clks.num_levels-1], 1000);
1084 		dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
1085 				clks.clocks_in_khz[clks.num_levels/8], 1000);
1086 		dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
1087 				clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1088 		dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
1089 				clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1090 		dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
1091 				clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1092 		dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
1093 				clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1094 		dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
1095 				clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1096 		dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
1097 				clks.clocks_in_khz[0], 1000);
1098 
1099 		/*do memory clock*/
1100 		dm_pp_get_clock_levels_by_type(
1101 				dc->ctx,
1102 				DM_PP_CLOCK_TYPE_MEMORY_CLK,
1103 				&clks);
1104 
1105 		dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1106 			clks.clocks_in_khz[0] * memory_type_multiplier, 1000);
1107 		dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1108 			clks.clocks_in_khz[clks.num_levels>>1] * memory_type_multiplier,
1109 			1000);
1110 		dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1111 			clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier,
1112 			1000);
1113 
1114 		return;
1115 	}
1116 
1117 	/* convert all the clock fro kHz to fix point mHz  TODO: wloop data */
1118 	dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1119 		eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
1120 	dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
1121 		eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
1122 	dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
1123 		eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
1124 	dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
1125 		eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
1126 	dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
1127 		eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
1128 	dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
1129 		eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
1130 	dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
1131 		eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
1132 	dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
1133 			eng_clks.data[0].clocks_in_khz, 1000);
1134 
1135 	/*do memory clock*/
1136 	dm_pp_get_clock_levels_by_type_with_latency(
1137 			dc->ctx,
1138 			DM_PP_CLOCK_TYPE_MEMORY_CLK,
1139 			&mem_clks);
1140 
1141 	/* we don't need to call PPLIB for validation clock since they
1142 	 * also give us the highest sclk and highest mclk (UMA clock).
1143 	 * ALSO always convert UMA clock (from PPLIB)  to YCLK (HW formula):
1144 	 * YCLK = UMACLK*m_memoryTypeMultiplier
1145 	 */
1146 	dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1147 		mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000);
1148 	dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1149 		mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier,
1150 		1000);
1151 	dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1152 		mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier,
1153 		1000);
1154 
1155 	/* Now notify PPLib/SMU about which Watermarks sets they should select
1156 	 * depending on DPM state they are in. And update BW MGR GFX Engine and
1157 	 * Memory clock member variables for Watermarks calculations for each
1158 	 * Watermark Set
1159 	 */
1160 	clk_ranges.num_wm_sets = 4;
1161 	clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
1162 	clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
1163 			eng_clks.data[0].clocks_in_khz;
1164 	clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
1165 			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1166 	clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz =
1167 			mem_clks.data[0].clocks_in_khz;
1168 	clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
1169 			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1170 
1171 	clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B;
1172 	clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz =
1173 			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1174 	/* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1175 	clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
1176 	clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz =
1177 			mem_clks.data[0].clocks_in_khz;
1178 	clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
1179 			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1180 
1181 	clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C;
1182 	clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz =
1183 			eng_clks.data[0].clocks_in_khz;
1184 	clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
1185 			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1186 	clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz =
1187 			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1188 	/* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1189 	clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
1190 
1191 	clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D;
1192 	clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz =
1193 			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1194 	/* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1195 	clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
1196 	clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz =
1197 			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1198 	/* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1199 	clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
1200 
1201 	/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1202 	dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
1203 }
1204 
1205 const struct resource_caps *dce112_resource_cap(
1206 	struct hw_asic_id *asic_id)
1207 {
1208 	if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) ||
1209 	    ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev))
1210 		return &polaris_11_resource_cap;
1211 	else
1212 		return &polaris_10_resource_cap;
1213 }
1214 
1215 static bool dce112_resource_construct(
1216 	uint8_t num_virtual_links,
1217 	struct dc *dc,
1218 	struct dce110_resource_pool *pool)
1219 {
1220 	unsigned int i;
1221 	struct dc_context *ctx = dc->ctx;
1222 
1223 	ctx->dc_bios->regs = &bios_regs;
1224 
1225 	pool->base.res_cap = dce112_resource_cap(&ctx->asic_id);
1226 	pool->base.funcs = &dce112_res_pool_funcs;
1227 
1228 	/*************************************************
1229 	 *  Resource + asic cap harcoding                *
1230 	 *************************************************/
1231 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1232 	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1233 	pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1234 	dc->caps.max_downscale_ratio = 200;
1235 	dc->caps.i2c_speed_in_khz = 100;
1236 	dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
1237 	dc->caps.max_cursor_size = 128;
1238 	dc->caps.min_horizontal_blanking_period = 80;
1239 	dc->caps.dual_link_dvi = true;
1240 	dc->caps.extended_aux_timeout_support = false;
1241 
1242 	/*************************************************
1243 	 *  Create resources                             *
1244 	 *************************************************/
1245 
1246 	pool->base.clock_sources[DCE112_CLK_SRC_PLL0] =
1247 			dce112_clock_source_create(
1248 				ctx, ctx->dc_bios,
1249 				CLOCK_SOURCE_COMBO_PHY_PLL0,
1250 				&clk_src_regs[0], false);
1251 	pool->base.clock_sources[DCE112_CLK_SRC_PLL1] =
1252 			dce112_clock_source_create(
1253 				ctx, ctx->dc_bios,
1254 				CLOCK_SOURCE_COMBO_PHY_PLL1,
1255 				&clk_src_regs[1], false);
1256 	pool->base.clock_sources[DCE112_CLK_SRC_PLL2] =
1257 			dce112_clock_source_create(
1258 				ctx, ctx->dc_bios,
1259 				CLOCK_SOURCE_COMBO_PHY_PLL2,
1260 				&clk_src_regs[2], false);
1261 	pool->base.clock_sources[DCE112_CLK_SRC_PLL3] =
1262 			dce112_clock_source_create(
1263 				ctx, ctx->dc_bios,
1264 				CLOCK_SOURCE_COMBO_PHY_PLL3,
1265 				&clk_src_regs[3], false);
1266 	pool->base.clock_sources[DCE112_CLK_SRC_PLL4] =
1267 			dce112_clock_source_create(
1268 				ctx, ctx->dc_bios,
1269 				CLOCK_SOURCE_COMBO_PHY_PLL4,
1270 				&clk_src_regs[4], false);
1271 	pool->base.clock_sources[DCE112_CLK_SRC_PLL5] =
1272 			dce112_clock_source_create(
1273 				ctx, ctx->dc_bios,
1274 				CLOCK_SOURCE_COMBO_PHY_PLL5,
1275 				&clk_src_regs[5], false);
1276 	pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL;
1277 
1278 	pool->base.dp_clock_source =  dce112_clock_source_create(
1279 		ctx, ctx->dc_bios,
1280 		CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true);
1281 
1282 
1283 	for (i = 0; i < pool->base.clk_src_count; i++) {
1284 		if (pool->base.clock_sources[i] == NULL) {
1285 			dm_error("DC: failed to create clock sources!\n");
1286 			BREAK_TO_DEBUGGER();
1287 			goto res_create_fail;
1288 		}
1289 	}
1290 
1291 	pool->base.dmcu = dce_dmcu_create(ctx,
1292 			&dmcu_regs,
1293 			&dmcu_shift,
1294 			&dmcu_mask);
1295 	if (pool->base.dmcu == NULL) {
1296 		dm_error("DC: failed to create dmcu!\n");
1297 		BREAK_TO_DEBUGGER();
1298 		goto res_create_fail;
1299 	}
1300 
1301 	pool->base.abm = dce_abm_create(ctx,
1302 			&abm_regs,
1303 			&abm_shift,
1304 			&abm_mask);
1305 	if (pool->base.abm == NULL) {
1306 		dm_error("DC: failed to create abm!\n");
1307 		BREAK_TO_DEBUGGER();
1308 		goto res_create_fail;
1309 	}
1310 
1311 	{
1312 		struct irq_service_init_data init_data;
1313 		init_data.ctx = dc->ctx;
1314 		pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1315 		if (!pool->base.irqs)
1316 			goto res_create_fail;
1317 	}
1318 
1319 	for (i = 0; i < pool->base.pipe_count; i++) {
1320 		pool->base.timing_generators[i] =
1321 				dce112_timing_generator_create(
1322 					ctx,
1323 					i,
1324 					&dce112_tg_offsets[i]);
1325 		if (pool->base.timing_generators[i] == NULL) {
1326 			BREAK_TO_DEBUGGER();
1327 			dm_error("DC: failed to create tg!\n");
1328 			goto res_create_fail;
1329 		}
1330 
1331 		pool->base.mis[i] = dce112_mem_input_create(ctx, i);
1332 		if (pool->base.mis[i] == NULL) {
1333 			BREAK_TO_DEBUGGER();
1334 			dm_error(
1335 				"DC: failed to create memory input!\n");
1336 			goto res_create_fail;
1337 		}
1338 
1339 		pool->base.ipps[i] = dce112_ipp_create(ctx, i);
1340 		if (pool->base.ipps[i] == NULL) {
1341 			BREAK_TO_DEBUGGER();
1342 			dm_error(
1343 				"DC:failed to create input pixel processor!\n");
1344 			goto res_create_fail;
1345 		}
1346 
1347 		pool->base.transforms[i] = dce112_transform_create(ctx, i);
1348 		if (pool->base.transforms[i] == NULL) {
1349 			BREAK_TO_DEBUGGER();
1350 			dm_error(
1351 				"DC: failed to create transform!\n");
1352 			goto res_create_fail;
1353 		}
1354 
1355 		pool->base.opps[i] = dce112_opp_create(
1356 			ctx,
1357 			i);
1358 		if (pool->base.opps[i] == NULL) {
1359 			BREAK_TO_DEBUGGER();
1360 			dm_error(
1361 				"DC:failed to create output pixel processor!\n");
1362 			goto res_create_fail;
1363 		}
1364 	}
1365 
1366 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1367 		pool->base.engines[i] = dce112_aux_engine_create(ctx, i);
1368 		if (pool->base.engines[i] == NULL) {
1369 			BREAK_TO_DEBUGGER();
1370 			dm_error(
1371 				"DC:failed to create aux engine!!\n");
1372 			goto res_create_fail;
1373 		}
1374 		pool->base.hw_i2cs[i] = dce112_i2c_hw_create(ctx, i);
1375 		if (pool->base.hw_i2cs[i] == NULL) {
1376 			BREAK_TO_DEBUGGER();
1377 			dm_error(
1378 				"DC:failed to create i2c engine!!\n");
1379 			goto res_create_fail;
1380 		}
1381 		pool->base.sw_i2cs[i] = NULL;
1382 	}
1383 
1384 	if (!resource_construct(num_virtual_links, dc, &pool->base,
1385 			  &res_create_funcs))
1386 		goto res_create_fail;
1387 
1388 	dc->caps.max_planes =  pool->base.pipe_count;
1389 
1390 	for (i = 0; i < dc->caps.max_planes; ++i)
1391 		dc->caps.planes[i] = plane_cap;
1392 
1393 	/* Create hardware sequencer */
1394 	dce112_hw_sequencer_construct(dc);
1395 
1396 	bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1397 
1398 	bw_calcs_data_update_from_pplib(dc);
1399 
1400 	return true;
1401 
1402 res_create_fail:
1403 	dce112_resource_destruct(pool);
1404 	return false;
1405 }
1406 
1407 struct resource_pool *dce112_create_resource_pool(
1408 	uint8_t num_virtual_links,
1409 	struct dc *dc)
1410 {
1411 	struct dce110_resource_pool *pool =
1412 		kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1413 
1414 	if (!pool)
1415 		return NULL;
1416 
1417 	if (dce112_resource_construct(num_virtual_links, dc, pool))
1418 		return &pool->base;
1419 
1420 	kfree(pool);
1421 	BREAK_TO_DEBUGGER();
1422 	return NULL;
1423 }
1424