1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "link_encoder.h" 29 #include "stream_encoder.h" 30 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dce110/dce110_resource.h" 34 #include "dce110/dce110_timing_generator.h" 35 36 #include "irq/dce110/irq_service_dce110.h" 37 38 #include "dce/dce_mem_input.h" 39 #include "dce/dce_transform.h" 40 #include "dce/dce_link_encoder.h" 41 #include "dce/dce_stream_encoder.h" 42 #include "dce/dce_audio.h" 43 #include "dce/dce_opp.h" 44 #include "dce/dce_ipp.h" 45 #include "dce/dce_clocks.h" 46 #include "dce/dce_clock_source.h" 47 48 #include "dce/dce_hwseq.h" 49 #include "dce112/dce112_hw_sequencer.h" 50 #include "dce/dce_abm.h" 51 #include "dce/dce_dmcu.h" 52 #include "dce/dce_aux.h" 53 54 #include "reg_helper.h" 55 56 #include "dce/dce_11_2_d.h" 57 #include "dce/dce_11_2_sh_mask.h" 58 59 #include "dce100/dce100_resource.h" 60 #define DC_LOGGER \ 61 dc->ctx->logger 62 63 #ifndef mmDP_DPHY_INTERNAL_CTRL 64 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 65 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 66 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 67 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 68 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 69 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 70 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 71 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 72 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 73 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 74 #endif 75 76 #ifndef mmBIOS_SCRATCH_2 77 #define mmBIOS_SCRATCH_2 0x05CB 78 #define mmBIOS_SCRATCH_6 0x05CF 79 #endif 80 81 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 82 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 83 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 84 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 85 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 86 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 87 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 88 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 89 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 90 #endif 91 92 #ifndef mmDP_DPHY_FAST_TRAINING 93 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 94 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 95 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 96 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 97 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 98 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 99 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 100 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 101 #endif 102 103 enum dce112_clk_src_array_id { 104 DCE112_CLK_SRC_PLL0, 105 DCE112_CLK_SRC_PLL1, 106 DCE112_CLK_SRC_PLL2, 107 DCE112_CLK_SRC_PLL3, 108 DCE112_CLK_SRC_PLL4, 109 DCE112_CLK_SRC_PLL5, 110 111 DCE112_CLK_SRC_TOTAL 112 }; 113 114 static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = { 115 { 116 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 117 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 118 }, 119 { 120 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 121 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 122 }, 123 { 124 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 125 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 126 }, 127 { 128 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 129 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 130 }, 131 { 132 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 133 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 134 }, 135 { 136 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 137 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 138 } 139 }; 140 141 /* set register offset */ 142 #define SR(reg_name)\ 143 .reg_name = mm ## reg_name 144 145 /* set register offset with instance */ 146 #define SRI(reg_name, block, id)\ 147 .reg_name = mm ## block ## id ## _ ## reg_name 148 149 150 static const struct dccg_registers disp_clk_regs = { 151 CLK_COMMON_REG_LIST_DCE_BASE() 152 }; 153 154 static const struct dccg_shift disp_clk_shift = { 155 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 156 }; 157 158 static const struct dccg_mask disp_clk_mask = { 159 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 160 }; 161 162 static const struct dce_dmcu_registers dmcu_regs = { 163 DMCU_DCE110_COMMON_REG_LIST() 164 }; 165 166 static const struct dce_dmcu_shift dmcu_shift = { 167 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 168 }; 169 170 static const struct dce_dmcu_mask dmcu_mask = { 171 DMCU_MASK_SH_LIST_DCE110(_MASK) 172 }; 173 174 static const struct dce_abm_registers abm_regs = { 175 ABM_DCE110_COMMON_REG_LIST() 176 }; 177 178 static const struct dce_abm_shift abm_shift = { 179 ABM_MASK_SH_LIST_DCE110(__SHIFT) 180 }; 181 182 static const struct dce_abm_mask abm_mask = { 183 ABM_MASK_SH_LIST_DCE110(_MASK) 184 }; 185 186 #define ipp_regs(id)\ 187 [id] = {\ 188 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 189 } 190 191 static const struct dce_ipp_registers ipp_regs[] = { 192 ipp_regs(0), 193 ipp_regs(1), 194 ipp_regs(2), 195 ipp_regs(3), 196 ipp_regs(4), 197 ipp_regs(5) 198 }; 199 200 static const struct dce_ipp_shift ipp_shift = { 201 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 202 }; 203 204 static const struct dce_ipp_mask ipp_mask = { 205 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 206 }; 207 208 #define transform_regs(id)\ 209 [id] = {\ 210 XFM_COMMON_REG_LIST_DCE110(id)\ 211 } 212 213 static const struct dce_transform_registers xfm_regs[] = { 214 transform_regs(0), 215 transform_regs(1), 216 transform_regs(2), 217 transform_regs(3), 218 transform_regs(4), 219 transform_regs(5) 220 }; 221 222 static const struct dce_transform_shift xfm_shift = { 223 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 224 }; 225 226 static const struct dce_transform_mask xfm_mask = { 227 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 228 }; 229 230 #define aux_regs(id)\ 231 [id] = {\ 232 AUX_REG_LIST(id)\ 233 } 234 235 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 236 aux_regs(0), 237 aux_regs(1), 238 aux_regs(2), 239 aux_regs(3), 240 aux_regs(4), 241 aux_regs(5) 242 }; 243 244 #define hpd_regs(id)\ 245 [id] = {\ 246 HPD_REG_LIST(id)\ 247 } 248 249 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 250 hpd_regs(0), 251 hpd_regs(1), 252 hpd_regs(2), 253 hpd_regs(3), 254 hpd_regs(4), 255 hpd_regs(5) 256 }; 257 258 #define link_regs(id)\ 259 [id] = {\ 260 LE_DCE110_REG_LIST(id)\ 261 } 262 263 static const struct dce110_link_enc_registers link_enc_regs[] = { 264 link_regs(0), 265 link_regs(1), 266 link_regs(2), 267 link_regs(3), 268 link_regs(4), 269 link_regs(5), 270 link_regs(6), 271 }; 272 273 #define stream_enc_regs(id)\ 274 [id] = {\ 275 SE_COMMON_REG_LIST(id),\ 276 .TMDS_CNTL = 0,\ 277 } 278 279 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 280 stream_enc_regs(0), 281 stream_enc_regs(1), 282 stream_enc_regs(2), 283 stream_enc_regs(3), 284 stream_enc_regs(4), 285 stream_enc_regs(5) 286 }; 287 288 static const struct dce_stream_encoder_shift se_shift = { 289 SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT) 290 }; 291 292 static const struct dce_stream_encoder_mask se_mask = { 293 SE_COMMON_MASK_SH_LIST_DCE112(_MASK) 294 }; 295 296 #define opp_regs(id)\ 297 [id] = {\ 298 OPP_DCE_112_REG_LIST(id),\ 299 } 300 301 static const struct dce_opp_registers opp_regs[] = { 302 opp_regs(0), 303 opp_regs(1), 304 opp_regs(2), 305 opp_regs(3), 306 opp_regs(4), 307 opp_regs(5) 308 }; 309 310 static const struct dce_opp_shift opp_shift = { 311 OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 312 }; 313 314 static const struct dce_opp_mask opp_mask = { 315 OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK) 316 }; 317 318 #define aux_engine_regs(id)\ 319 [id] = {\ 320 AUX_COMMON_REG_LIST(id), \ 321 .AUX_RESET_MASK = 0 \ 322 } 323 324 static const struct dce110_aux_registers aux_engine_regs[] = { 325 aux_engine_regs(0), 326 aux_engine_regs(1), 327 aux_engine_regs(2), 328 aux_engine_regs(3), 329 aux_engine_regs(4), 330 aux_engine_regs(5) 331 }; 332 333 #define audio_regs(id)\ 334 [id] = {\ 335 AUD_COMMON_REG_LIST(id)\ 336 } 337 338 static const struct dce_audio_registers audio_regs[] = { 339 audio_regs(0), 340 audio_regs(1), 341 audio_regs(2), 342 audio_regs(3), 343 audio_regs(4), 344 audio_regs(5) 345 }; 346 347 static const struct dce_audio_shift audio_shift = { 348 AUD_COMMON_MASK_SH_LIST(__SHIFT) 349 }; 350 351 static const struct dce_aduio_mask audio_mask = { 352 AUD_COMMON_MASK_SH_LIST(_MASK) 353 }; 354 355 #define clk_src_regs(index, id)\ 356 [index] = {\ 357 CS_COMMON_REG_LIST_DCE_112(id),\ 358 } 359 360 static const struct dce110_clk_src_regs clk_src_regs[] = { 361 clk_src_regs(0, A), 362 clk_src_regs(1, B), 363 clk_src_regs(2, C), 364 clk_src_regs(3, D), 365 clk_src_regs(4, E), 366 clk_src_regs(5, F) 367 }; 368 369 static const struct dce110_clk_src_shift cs_shift = { 370 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 371 }; 372 373 static const struct dce110_clk_src_mask cs_mask = { 374 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) 375 }; 376 377 static const struct bios_registers bios_regs = { 378 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 379 }; 380 381 static const struct resource_caps polaris_10_resource_cap = { 382 .num_timing_generator = 6, 383 .num_audio = 6, 384 .num_stream_encoder = 6, 385 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */ 386 }; 387 388 static const struct resource_caps polaris_11_resource_cap = { 389 .num_timing_generator = 5, 390 .num_audio = 5, 391 .num_stream_encoder = 5, 392 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */ 393 }; 394 395 #define CTX ctx 396 #define REG(reg) mm ## reg 397 398 #ifndef mmCC_DC_HDMI_STRAPS 399 #define mmCC_DC_HDMI_STRAPS 0x4819 400 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 401 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 402 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 403 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 404 #endif 405 406 static void read_dce_straps( 407 struct dc_context *ctx, 408 struct resource_straps *straps) 409 { 410 REG_GET_2(CC_DC_HDMI_STRAPS, 411 HDMI_DISABLE, &straps->hdmi_disable, 412 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 413 414 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 415 } 416 417 static struct audio *create_audio( 418 struct dc_context *ctx, unsigned int inst) 419 { 420 return dce_audio_create(ctx, inst, 421 &audio_regs[inst], &audio_shift, &audio_mask); 422 } 423 424 425 static struct timing_generator *dce112_timing_generator_create( 426 struct dc_context *ctx, 427 uint32_t instance, 428 const struct dce110_timing_generator_offsets *offsets) 429 { 430 struct dce110_timing_generator *tg110 = 431 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 432 433 if (!tg110) 434 return NULL; 435 436 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 437 return &tg110->base; 438 } 439 440 static struct stream_encoder *dce112_stream_encoder_create( 441 enum engine_id eng_id, 442 struct dc_context *ctx) 443 { 444 struct dce110_stream_encoder *enc110 = 445 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 446 447 if (!enc110) 448 return NULL; 449 450 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 451 &stream_enc_regs[eng_id], 452 &se_shift, &se_mask); 453 return &enc110->base; 454 } 455 456 #define SRII(reg_name, block, id)\ 457 .reg_name[id] = mm ## block ## id ## _ ## reg_name 458 459 static const struct dce_hwseq_registers hwseq_reg = { 460 HWSEQ_DCE112_REG_LIST() 461 }; 462 463 static const struct dce_hwseq_shift hwseq_shift = { 464 HWSEQ_DCE112_MASK_SH_LIST(__SHIFT) 465 }; 466 467 static const struct dce_hwseq_mask hwseq_mask = { 468 HWSEQ_DCE112_MASK_SH_LIST(_MASK) 469 }; 470 471 static struct dce_hwseq *dce112_hwseq_create( 472 struct dc_context *ctx) 473 { 474 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 475 476 if (hws) { 477 hws->ctx = ctx; 478 hws->regs = &hwseq_reg; 479 hws->shifts = &hwseq_shift; 480 hws->masks = &hwseq_mask; 481 } 482 return hws; 483 } 484 485 static const struct resource_create_funcs res_create_funcs = { 486 .read_dce_straps = read_dce_straps, 487 .create_audio = create_audio, 488 .create_stream_encoder = dce112_stream_encoder_create, 489 .create_hwseq = dce112_hwseq_create, 490 }; 491 492 #define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) } 493 static const struct dce_mem_input_registers mi_regs[] = { 494 mi_inst_regs(0), 495 mi_inst_regs(1), 496 mi_inst_regs(2), 497 mi_inst_regs(3), 498 mi_inst_regs(4), 499 mi_inst_regs(5), 500 }; 501 502 static const struct dce_mem_input_shift mi_shifts = { 503 MI_DCE11_2_MASK_SH_LIST(__SHIFT) 504 }; 505 506 static const struct dce_mem_input_mask mi_masks = { 507 MI_DCE11_2_MASK_SH_LIST(_MASK) 508 }; 509 510 static struct mem_input *dce112_mem_input_create( 511 struct dc_context *ctx, 512 uint32_t inst) 513 { 514 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 515 GFP_KERNEL); 516 517 if (!dce_mi) { 518 BREAK_TO_DEBUGGER(); 519 return NULL; 520 } 521 522 dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 523 return &dce_mi->base; 524 } 525 526 static void dce112_transform_destroy(struct transform **xfm) 527 { 528 kfree(TO_DCE_TRANSFORM(*xfm)); 529 *xfm = NULL; 530 } 531 532 static struct transform *dce112_transform_create( 533 struct dc_context *ctx, 534 uint32_t inst) 535 { 536 struct dce_transform *transform = 537 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 538 539 if (!transform) 540 return NULL; 541 542 dce_transform_construct(transform, ctx, inst, 543 &xfm_regs[inst], &xfm_shift, &xfm_mask); 544 transform->lb_memory_size = 0x1404; /*5124*/ 545 return &transform->base; 546 } 547 548 static const struct encoder_feature_support link_enc_feature = { 549 .max_hdmi_deep_color = COLOR_DEPTH_121212, 550 .max_hdmi_pixel_clock = 600000, 551 .ycbcr420_supported = true, 552 .flags.bits.IS_HBR2_CAPABLE = true, 553 .flags.bits.IS_HBR3_CAPABLE = true, 554 .flags.bits.IS_TPS3_CAPABLE = true, 555 .flags.bits.IS_TPS4_CAPABLE = true, 556 .flags.bits.IS_YCBCR_CAPABLE = true 557 }; 558 559 struct link_encoder *dce112_link_encoder_create( 560 const struct encoder_init_data *enc_init_data) 561 { 562 struct dce110_link_encoder *enc110 = 563 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 564 565 if (!enc110) 566 return NULL; 567 568 dce110_link_encoder_construct(enc110, 569 enc_init_data, 570 &link_enc_feature, 571 &link_enc_regs[enc_init_data->transmitter], 572 &link_enc_aux_regs[enc_init_data->channel - 1], 573 &link_enc_hpd_regs[enc_init_data->hpd_source]); 574 return &enc110->base; 575 } 576 577 static struct input_pixel_processor *dce112_ipp_create( 578 struct dc_context *ctx, uint32_t inst) 579 { 580 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 581 582 if (!ipp) { 583 BREAK_TO_DEBUGGER(); 584 return NULL; 585 } 586 587 dce_ipp_construct(ipp, ctx, inst, 588 &ipp_regs[inst], &ipp_shift, &ipp_mask); 589 return &ipp->base; 590 } 591 592 struct output_pixel_processor *dce112_opp_create( 593 struct dc_context *ctx, 594 uint32_t inst) 595 { 596 struct dce110_opp *opp = 597 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 598 599 if (!opp) 600 return NULL; 601 602 dce110_opp_construct(opp, 603 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 604 return &opp->base; 605 } 606 607 struct aux_engine *dce112_aux_engine_create( 608 struct dc_context *ctx, 609 uint32_t inst) 610 { 611 struct aux_engine_dce110 *aux_engine = 612 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 613 614 if (!aux_engine) 615 return NULL; 616 617 dce110_aux_engine_construct(aux_engine, ctx, inst, 618 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 619 &aux_engine_regs[inst]); 620 621 return &aux_engine->base; 622 } 623 624 struct clock_source *dce112_clock_source_create( 625 struct dc_context *ctx, 626 struct dc_bios *bios, 627 enum clock_source_id id, 628 const struct dce110_clk_src_regs *regs, 629 bool dp_clk_src) 630 { 631 struct dce110_clk_src *clk_src = 632 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 633 634 if (!clk_src) 635 return NULL; 636 637 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 638 regs, &cs_shift, &cs_mask)) { 639 clk_src->base.dp_clk_src = dp_clk_src; 640 return &clk_src->base; 641 } 642 643 BREAK_TO_DEBUGGER(); 644 return NULL; 645 } 646 647 void dce112_clock_source_destroy(struct clock_source **clk_src) 648 { 649 kfree(TO_DCE110_CLK_SRC(*clk_src)); 650 *clk_src = NULL; 651 } 652 653 static void destruct(struct dce110_resource_pool *pool) 654 { 655 unsigned int i; 656 657 for (i = 0; i < pool->base.pipe_count; i++) { 658 if (pool->base.opps[i] != NULL) 659 dce110_opp_destroy(&pool->base.opps[i]); 660 661 if (pool->base.engines[i] != NULL) 662 dce110_engine_destroy(&pool->base.engines[i]); 663 664 if (pool->base.transforms[i] != NULL) 665 dce112_transform_destroy(&pool->base.transforms[i]); 666 667 if (pool->base.ipps[i] != NULL) 668 dce_ipp_destroy(&pool->base.ipps[i]); 669 670 if (pool->base.mis[i] != NULL) { 671 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 672 pool->base.mis[i] = NULL; 673 } 674 675 if (pool->base.timing_generators[i] != NULL) { 676 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 677 pool->base.timing_generators[i] = NULL; 678 } 679 680 } 681 682 for (i = 0; i < pool->base.stream_enc_count; i++) { 683 if (pool->base.stream_enc[i] != NULL) 684 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 685 } 686 687 for (i = 0; i < pool->base.clk_src_count; i++) { 688 if (pool->base.clock_sources[i] != NULL) { 689 dce112_clock_source_destroy(&pool->base.clock_sources[i]); 690 } 691 } 692 693 if (pool->base.dp_clock_source != NULL) 694 dce112_clock_source_destroy(&pool->base.dp_clock_source); 695 696 for (i = 0; i < pool->base.audio_count; i++) { 697 if (pool->base.audios[i] != NULL) { 698 dce_aud_destroy(&pool->base.audios[i]); 699 } 700 } 701 702 if (pool->base.abm != NULL) 703 dce_abm_destroy(&pool->base.abm); 704 705 if (pool->base.dmcu != NULL) 706 dce_dmcu_destroy(&pool->base.dmcu); 707 708 if (pool->base.dccg != NULL) 709 dce_dccg_destroy(&pool->base.dccg); 710 711 if (pool->base.irqs != NULL) { 712 dal_irq_service_destroy(&pool->base.irqs); 713 } 714 } 715 716 static struct clock_source *find_matching_pll( 717 struct resource_context *res_ctx, 718 const struct resource_pool *pool, 719 const struct dc_stream_state *const stream) 720 { 721 switch (stream->sink->link->link_enc->transmitter) { 722 case TRANSMITTER_UNIPHY_A: 723 return pool->clock_sources[DCE112_CLK_SRC_PLL0]; 724 case TRANSMITTER_UNIPHY_B: 725 return pool->clock_sources[DCE112_CLK_SRC_PLL1]; 726 case TRANSMITTER_UNIPHY_C: 727 return pool->clock_sources[DCE112_CLK_SRC_PLL2]; 728 case TRANSMITTER_UNIPHY_D: 729 return pool->clock_sources[DCE112_CLK_SRC_PLL3]; 730 case TRANSMITTER_UNIPHY_E: 731 return pool->clock_sources[DCE112_CLK_SRC_PLL4]; 732 case TRANSMITTER_UNIPHY_F: 733 return pool->clock_sources[DCE112_CLK_SRC_PLL5]; 734 default: 735 return NULL; 736 }; 737 738 return 0; 739 } 740 741 static enum dc_status build_mapped_resource( 742 const struct dc *dc, 743 struct dc_state *context, 744 struct dc_stream_state *stream) 745 { 746 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 747 748 if (!pipe_ctx) 749 return DC_ERROR_UNEXPECTED; 750 751 dce110_resource_build_pipe_hw_param(pipe_ctx); 752 753 resource_build_info_frame(pipe_ctx); 754 755 return DC_OK; 756 } 757 758 bool dce112_validate_bandwidth( 759 struct dc *dc, 760 struct dc_state *context) 761 { 762 bool result = false; 763 764 DC_LOG_BANDWIDTH_CALCS( 765 "%s: start", 766 __func__); 767 768 if (bw_calcs( 769 dc->ctx, 770 dc->bw_dceip, 771 dc->bw_vbios, 772 context->res_ctx.pipe_ctx, 773 dc->res_pool->pipe_count, 774 &context->bw.dce)) 775 result = true; 776 777 if (!result) 778 DC_LOG_BANDWIDTH_VALIDATION( 779 "%s: Bandwidth validation failed!", 780 __func__); 781 782 if (memcmp(&dc->current_state->bw.dce, 783 &context->bw.dce, sizeof(context->bw.dce))) { 784 785 DC_LOG_BANDWIDTH_CALCS( 786 "%s: finish,\n" 787 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 788 "stutMark_b: %d stutMark_a: %d\n" 789 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 790 "stutMark_b: %d stutMark_a: %d\n" 791 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 792 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n" 793 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" 794 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n" 795 , 796 __func__, 797 context->bw.dce.nbp_state_change_wm_ns[0].b_mark, 798 context->bw.dce.nbp_state_change_wm_ns[0].a_mark, 799 context->bw.dce.urgent_wm_ns[0].b_mark, 800 context->bw.dce.urgent_wm_ns[0].a_mark, 801 context->bw.dce.stutter_exit_wm_ns[0].b_mark, 802 context->bw.dce.stutter_exit_wm_ns[0].a_mark, 803 context->bw.dce.nbp_state_change_wm_ns[1].b_mark, 804 context->bw.dce.nbp_state_change_wm_ns[1].a_mark, 805 context->bw.dce.urgent_wm_ns[1].b_mark, 806 context->bw.dce.urgent_wm_ns[1].a_mark, 807 context->bw.dce.stutter_exit_wm_ns[1].b_mark, 808 context->bw.dce.stutter_exit_wm_ns[1].a_mark, 809 context->bw.dce.nbp_state_change_wm_ns[2].b_mark, 810 context->bw.dce.nbp_state_change_wm_ns[2].a_mark, 811 context->bw.dce.urgent_wm_ns[2].b_mark, 812 context->bw.dce.urgent_wm_ns[2].a_mark, 813 context->bw.dce.stutter_exit_wm_ns[2].b_mark, 814 context->bw.dce.stutter_exit_wm_ns[2].a_mark, 815 context->bw.dce.stutter_mode_enable, 816 context->bw.dce.cpuc_state_change_enable, 817 context->bw.dce.cpup_state_change_enable, 818 context->bw.dce.nbp_state_change_enable, 819 context->bw.dce.all_displays_in_sync, 820 context->bw.dce.dispclk_khz, 821 context->bw.dce.sclk_khz, 822 context->bw.dce.sclk_deep_sleep_khz, 823 context->bw.dce.yclk_khz, 824 context->bw.dce.blackout_recovery_time_us); 825 } 826 return result; 827 } 828 829 enum dc_status resource_map_phy_clock_resources( 830 const struct dc *dc, 831 struct dc_state *context, 832 struct dc_stream_state *stream) 833 { 834 835 /* acquire new resources */ 836 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( 837 &context->res_ctx, stream); 838 839 if (!pipe_ctx) 840 return DC_ERROR_UNEXPECTED; 841 842 if (dc_is_dp_signal(pipe_ctx->stream->signal) 843 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) 844 pipe_ctx->clock_source = 845 dc->res_pool->dp_clock_source; 846 else 847 pipe_ctx->clock_source = find_matching_pll( 848 &context->res_ctx, dc->res_pool, 849 stream); 850 851 if (pipe_ctx->clock_source == NULL) 852 return DC_NO_CLOCK_SOURCE_RESOURCE; 853 854 resource_reference_clock_source( 855 &context->res_ctx, 856 dc->res_pool, 857 pipe_ctx->clock_source); 858 859 return DC_OK; 860 } 861 862 static bool dce112_validate_surface_sets( 863 struct dc_state *context) 864 { 865 int i; 866 867 for (i = 0; i < context->stream_count; i++) { 868 if (context->stream_status[i].plane_count == 0) 869 continue; 870 871 if (context->stream_status[i].plane_count > 1) 872 return false; 873 874 if (context->stream_status[i].plane_states[0]->format 875 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 876 return false; 877 } 878 879 return true; 880 } 881 882 enum dc_status dce112_add_stream_to_ctx( 883 struct dc *dc, 884 struct dc_state *new_ctx, 885 struct dc_stream_state *dc_stream) 886 { 887 enum dc_status result = DC_ERROR_UNEXPECTED; 888 889 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 890 891 if (result == DC_OK) 892 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 893 894 895 if (result == DC_OK) 896 result = build_mapped_resource(dc, new_ctx, dc_stream); 897 898 return result; 899 } 900 901 enum dc_status dce112_validate_global( 902 struct dc *dc, 903 struct dc_state *context) 904 { 905 if (!dce112_validate_surface_sets(context)) 906 return DC_FAIL_SURFACE_VALIDATE; 907 908 return DC_OK; 909 } 910 911 static void dce112_destroy_resource_pool(struct resource_pool **pool) 912 { 913 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 914 915 destruct(dce110_pool); 916 kfree(dce110_pool); 917 *pool = NULL; 918 } 919 920 static const struct resource_funcs dce112_res_pool_funcs = { 921 .destroy = dce112_destroy_resource_pool, 922 .link_enc_create = dce112_link_encoder_create, 923 .validate_bandwidth = dce112_validate_bandwidth, 924 .validate_plane = dce100_validate_plane, 925 .add_stream_to_ctx = dce112_add_stream_to_ctx, 926 .validate_global = dce112_validate_global 927 }; 928 929 static void bw_calcs_data_update_from_pplib(struct dc *dc) 930 { 931 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 932 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 933 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; 934 struct dm_pp_clock_levels clks = {0}; 935 936 /*do system clock TODO PPLIB: after PPLIB implement, 937 * then remove old way 938 */ 939 if (!dm_pp_get_clock_levels_by_type_with_latency( 940 dc->ctx, 941 DM_PP_CLOCK_TYPE_ENGINE_CLK, 942 &eng_clks)) { 943 944 /* This is only for temporary */ 945 dm_pp_get_clock_levels_by_type( 946 dc->ctx, 947 DM_PP_CLOCK_TYPE_ENGINE_CLK, 948 &clks); 949 /* convert all the clock fro kHz to fix point mHz */ 950 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 951 clks.clocks_in_khz[clks.num_levels-1], 1000); 952 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 953 clks.clocks_in_khz[clks.num_levels/8], 1000); 954 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 955 clks.clocks_in_khz[clks.num_levels*2/8], 1000); 956 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 957 clks.clocks_in_khz[clks.num_levels*3/8], 1000); 958 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 959 clks.clocks_in_khz[clks.num_levels*4/8], 1000); 960 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 961 clks.clocks_in_khz[clks.num_levels*5/8], 1000); 962 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 963 clks.clocks_in_khz[clks.num_levels*6/8], 1000); 964 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 965 clks.clocks_in_khz[0], 1000); 966 967 /*do memory clock*/ 968 dm_pp_get_clock_levels_by_type( 969 dc->ctx, 970 DM_PP_CLOCK_TYPE_MEMORY_CLK, 971 &clks); 972 973 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 974 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000); 975 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 976 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER, 977 1000); 978 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 979 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER, 980 1000); 981 982 return; 983 } 984 985 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ 986 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 987 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); 988 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 989 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); 990 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 991 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); 992 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 993 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); 994 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 995 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); 996 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 997 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); 998 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 999 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); 1000 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1001 eng_clks.data[0].clocks_in_khz, 1000); 1002 1003 /*do memory clock*/ 1004 dm_pp_get_clock_levels_by_type_with_latency( 1005 dc->ctx, 1006 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1007 &mem_clks); 1008 1009 /* we don't need to call PPLIB for validation clock since they 1010 * also give us the highest sclk and highest mclk (UMA clock). 1011 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): 1012 * YCLK = UMACLK*m_memoryTypeMultiplier 1013 */ 1014 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1015 mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000); 1016 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1017 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1018 1000); 1019 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1020 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1021 1000); 1022 1023 /* Now notify PPLib/SMU about which Watermarks sets they should select 1024 * depending on DPM state they are in. And update BW MGR GFX Engine and 1025 * Memory clock member variables for Watermarks calculations for each 1026 * Watermark Set 1027 */ 1028 clk_ranges.num_wm_sets = 4; 1029 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; 1030 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = 1031 eng_clks.data[0].clocks_in_khz; 1032 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = 1033 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 1034 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz = 1035 mem_clks.data[0].clocks_in_khz; 1036 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = 1037 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 1038 1039 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; 1040 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = 1041 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 1042 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 1043 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; 1044 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz = 1045 mem_clks.data[0].clocks_in_khz; 1046 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = 1047 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 1048 1049 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; 1050 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = 1051 eng_clks.data[0].clocks_in_khz; 1052 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = 1053 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 1054 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz = 1055 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 1056 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 1057 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; 1058 1059 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; 1060 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = 1061 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 1062 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 1063 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; 1064 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz = 1065 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 1066 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 1067 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; 1068 1069 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 1070 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); 1071 } 1072 1073 const struct resource_caps *dce112_resource_cap( 1074 struct hw_asic_id *asic_id) 1075 { 1076 if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) || 1077 ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev)) 1078 return &polaris_11_resource_cap; 1079 else 1080 return &polaris_10_resource_cap; 1081 } 1082 1083 static bool construct( 1084 uint8_t num_virtual_links, 1085 struct dc *dc, 1086 struct dce110_resource_pool *pool) 1087 { 1088 unsigned int i; 1089 struct dc_context *ctx = dc->ctx; 1090 struct dm_pp_static_clock_info static_clk_info = {0}; 1091 1092 ctx->dc_bios->regs = &bios_regs; 1093 1094 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id); 1095 pool->base.funcs = &dce112_res_pool_funcs; 1096 1097 /************************************************* 1098 * Resource + asic cap harcoding * 1099 *************************************************/ 1100 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1101 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1102 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1103 dc->caps.max_downscale_ratio = 200; 1104 dc->caps.i2c_speed_in_khz = 100; 1105 dc->caps.max_cursor_size = 128; 1106 dc->caps.dual_link_dvi = true; 1107 1108 1109 /************************************************* 1110 * Create resources * 1111 *************************************************/ 1112 1113 pool->base.clock_sources[DCE112_CLK_SRC_PLL0] = 1114 dce112_clock_source_create( 1115 ctx, ctx->dc_bios, 1116 CLOCK_SOURCE_COMBO_PHY_PLL0, 1117 &clk_src_regs[0], false); 1118 pool->base.clock_sources[DCE112_CLK_SRC_PLL1] = 1119 dce112_clock_source_create( 1120 ctx, ctx->dc_bios, 1121 CLOCK_SOURCE_COMBO_PHY_PLL1, 1122 &clk_src_regs[1], false); 1123 pool->base.clock_sources[DCE112_CLK_SRC_PLL2] = 1124 dce112_clock_source_create( 1125 ctx, ctx->dc_bios, 1126 CLOCK_SOURCE_COMBO_PHY_PLL2, 1127 &clk_src_regs[2], false); 1128 pool->base.clock_sources[DCE112_CLK_SRC_PLL3] = 1129 dce112_clock_source_create( 1130 ctx, ctx->dc_bios, 1131 CLOCK_SOURCE_COMBO_PHY_PLL3, 1132 &clk_src_regs[3], false); 1133 pool->base.clock_sources[DCE112_CLK_SRC_PLL4] = 1134 dce112_clock_source_create( 1135 ctx, ctx->dc_bios, 1136 CLOCK_SOURCE_COMBO_PHY_PLL4, 1137 &clk_src_regs[4], false); 1138 pool->base.clock_sources[DCE112_CLK_SRC_PLL5] = 1139 dce112_clock_source_create( 1140 ctx, ctx->dc_bios, 1141 CLOCK_SOURCE_COMBO_PHY_PLL5, 1142 &clk_src_regs[5], false); 1143 pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL; 1144 1145 pool->base.dp_clock_source = dce112_clock_source_create( 1146 ctx, ctx->dc_bios, 1147 CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); 1148 1149 1150 for (i = 0; i < pool->base.clk_src_count; i++) { 1151 if (pool->base.clock_sources[i] == NULL) { 1152 dm_error("DC: failed to create clock sources!\n"); 1153 BREAK_TO_DEBUGGER(); 1154 goto res_create_fail; 1155 } 1156 } 1157 1158 pool->base.dccg = dce112_dccg_create(ctx, 1159 &disp_clk_regs, 1160 &disp_clk_shift, 1161 &disp_clk_mask); 1162 if (pool->base.dccg == NULL) { 1163 dm_error("DC: failed to create display clock!\n"); 1164 BREAK_TO_DEBUGGER(); 1165 goto res_create_fail; 1166 } 1167 1168 pool->base.dmcu = dce_dmcu_create(ctx, 1169 &dmcu_regs, 1170 &dmcu_shift, 1171 &dmcu_mask); 1172 if (pool->base.dmcu == NULL) { 1173 dm_error("DC: failed to create dmcu!\n"); 1174 BREAK_TO_DEBUGGER(); 1175 goto res_create_fail; 1176 } 1177 1178 pool->base.abm = dce_abm_create(ctx, 1179 &abm_regs, 1180 &abm_shift, 1181 &abm_mask); 1182 if (pool->base.abm == NULL) { 1183 dm_error("DC: failed to create abm!\n"); 1184 BREAK_TO_DEBUGGER(); 1185 goto res_create_fail; 1186 } 1187 1188 /* get static clock information for PPLIB or firmware, save 1189 * max_clock_state 1190 */ 1191 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 1192 pool->base.dccg->max_clks_state = 1193 static_clk_info.max_clocks_state; 1194 1195 { 1196 struct irq_service_init_data init_data; 1197 init_data.ctx = dc->ctx; 1198 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 1199 if (!pool->base.irqs) 1200 goto res_create_fail; 1201 } 1202 1203 for (i = 0; i < pool->base.pipe_count; i++) { 1204 pool->base.timing_generators[i] = 1205 dce112_timing_generator_create( 1206 ctx, 1207 i, 1208 &dce112_tg_offsets[i]); 1209 if (pool->base.timing_generators[i] == NULL) { 1210 BREAK_TO_DEBUGGER(); 1211 dm_error("DC: failed to create tg!\n"); 1212 goto res_create_fail; 1213 } 1214 1215 pool->base.mis[i] = dce112_mem_input_create(ctx, i); 1216 if (pool->base.mis[i] == NULL) { 1217 BREAK_TO_DEBUGGER(); 1218 dm_error( 1219 "DC: failed to create memory input!\n"); 1220 goto res_create_fail; 1221 } 1222 1223 pool->base.ipps[i] = dce112_ipp_create(ctx, i); 1224 if (pool->base.ipps[i] == NULL) { 1225 BREAK_TO_DEBUGGER(); 1226 dm_error( 1227 "DC:failed to create input pixel processor!\n"); 1228 goto res_create_fail; 1229 } 1230 1231 pool->base.transforms[i] = dce112_transform_create(ctx, i); 1232 if (pool->base.transforms[i] == NULL) { 1233 BREAK_TO_DEBUGGER(); 1234 dm_error( 1235 "DC: failed to create transform!\n"); 1236 goto res_create_fail; 1237 } 1238 1239 pool->base.opps[i] = dce112_opp_create( 1240 ctx, 1241 i); 1242 if (pool->base.opps[i] == NULL) { 1243 BREAK_TO_DEBUGGER(); 1244 dm_error( 1245 "DC:failed to create output pixel processor!\n"); 1246 goto res_create_fail; 1247 } 1248 pool->base.engines[i] = dce112_aux_engine_create(ctx, i); 1249 if (pool->base.engines[i] == NULL) { 1250 BREAK_TO_DEBUGGER(); 1251 dm_error( 1252 "DC:failed to create aux engine!!\n"); 1253 goto res_create_fail; 1254 } 1255 } 1256 1257 if (!resource_construct(num_virtual_links, dc, &pool->base, 1258 &res_create_funcs)) 1259 goto res_create_fail; 1260 1261 dc->caps.max_planes = pool->base.pipe_count; 1262 1263 /* Create hardware sequencer */ 1264 dce112_hw_sequencer_construct(dc); 1265 1266 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1267 1268 bw_calcs_data_update_from_pplib(dc); 1269 1270 return true; 1271 1272 res_create_fail: 1273 destruct(pool); 1274 return false; 1275 } 1276 1277 struct resource_pool *dce112_create_resource_pool( 1278 uint8_t num_virtual_links, 1279 struct dc *dc) 1280 { 1281 struct dce110_resource_pool *pool = 1282 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1283 1284 if (!pool) 1285 return NULL; 1286 1287 if (construct(num_virtual_links, dc, pool)) 1288 return &pool->base; 1289 1290 BREAK_TO_DEBUGGER(); 1291 return NULL; 1292 } 1293