1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "link_encoder.h" 29 #include "stream_encoder.h" 30 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dce110/dce110_resource.h" 34 #include "dce110/dce110_timing_generator.h" 35 36 #include "irq/dce110/irq_service_dce110.h" 37 38 #include "dce/dce_clk_mgr.h" 39 #include "dce/dce_mem_input.h" 40 #include "dce/dce_transform.h" 41 #include "dce/dce_link_encoder.h" 42 #include "dce/dce_stream_encoder.h" 43 #include "dce/dce_audio.h" 44 #include "dce/dce_opp.h" 45 #include "dce/dce_ipp.h" 46 #include "dce/dce_clock_source.h" 47 48 #include "dce/dce_hwseq.h" 49 #include "dce112/dce112_hw_sequencer.h" 50 #include "dce/dce_abm.h" 51 #include "dce/dce_dmcu.h" 52 #include "dce/dce_aux.h" 53 #include "dce/dce_i2c.h" 54 55 #include "reg_helper.h" 56 57 #include "dce/dce_11_2_d.h" 58 #include "dce/dce_11_2_sh_mask.h" 59 60 #include "dce100/dce100_resource.h" 61 #define DC_LOGGER \ 62 dc->ctx->logger 63 64 #ifndef mmDP_DPHY_INTERNAL_CTRL 65 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 66 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 67 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 68 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 69 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 70 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 71 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 72 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 73 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 74 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 75 #endif 76 77 #ifndef mmBIOS_SCRATCH_2 78 #define mmBIOS_SCRATCH_2 0x05CB 79 #define mmBIOS_SCRATCH_3 0x05CC 80 #define mmBIOS_SCRATCH_6 0x05CF 81 #endif 82 83 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 84 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 85 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 86 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 87 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 88 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 89 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 90 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 91 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 92 #endif 93 94 #ifndef mmDP_DPHY_FAST_TRAINING 95 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 96 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 97 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 98 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 99 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 100 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 101 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 102 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 103 #endif 104 105 enum dce112_clk_src_array_id { 106 DCE112_CLK_SRC_PLL0, 107 DCE112_CLK_SRC_PLL1, 108 DCE112_CLK_SRC_PLL2, 109 DCE112_CLK_SRC_PLL3, 110 DCE112_CLK_SRC_PLL4, 111 DCE112_CLK_SRC_PLL5, 112 113 DCE112_CLK_SRC_TOTAL 114 }; 115 116 static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = { 117 { 118 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 119 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 120 }, 121 { 122 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 123 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 124 }, 125 { 126 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 127 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 128 }, 129 { 130 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 131 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 132 }, 133 { 134 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 135 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 136 }, 137 { 138 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 139 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 140 } 141 }; 142 143 /* set register offset */ 144 #define SR(reg_name)\ 145 .reg_name = mm ## reg_name 146 147 /* set register offset with instance */ 148 #define SRI(reg_name, block, id)\ 149 .reg_name = mm ## block ## id ## _ ## reg_name 150 151 152 static const struct clk_mgr_registers disp_clk_regs = { 153 CLK_COMMON_REG_LIST_DCE_BASE() 154 }; 155 156 static const struct clk_mgr_shift disp_clk_shift = { 157 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 158 }; 159 160 static const struct clk_mgr_mask disp_clk_mask = { 161 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 162 }; 163 164 static const struct dce_dmcu_registers dmcu_regs = { 165 DMCU_DCE110_COMMON_REG_LIST() 166 }; 167 168 static const struct dce_dmcu_shift dmcu_shift = { 169 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 170 }; 171 172 static const struct dce_dmcu_mask dmcu_mask = { 173 DMCU_MASK_SH_LIST_DCE110(_MASK) 174 }; 175 176 static const struct dce_abm_registers abm_regs = { 177 ABM_DCE110_COMMON_REG_LIST() 178 }; 179 180 static const struct dce_abm_shift abm_shift = { 181 ABM_MASK_SH_LIST_DCE110(__SHIFT) 182 }; 183 184 static const struct dce_abm_mask abm_mask = { 185 ABM_MASK_SH_LIST_DCE110(_MASK) 186 }; 187 188 #define ipp_regs(id)\ 189 [id] = {\ 190 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 191 } 192 193 static const struct dce_ipp_registers ipp_regs[] = { 194 ipp_regs(0), 195 ipp_regs(1), 196 ipp_regs(2), 197 ipp_regs(3), 198 ipp_regs(4), 199 ipp_regs(5) 200 }; 201 202 static const struct dce_ipp_shift ipp_shift = { 203 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 204 }; 205 206 static const struct dce_ipp_mask ipp_mask = { 207 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 208 }; 209 210 #define transform_regs(id)\ 211 [id] = {\ 212 XFM_COMMON_REG_LIST_DCE110(id)\ 213 } 214 215 static const struct dce_transform_registers xfm_regs[] = { 216 transform_regs(0), 217 transform_regs(1), 218 transform_regs(2), 219 transform_regs(3), 220 transform_regs(4), 221 transform_regs(5) 222 }; 223 224 static const struct dce_transform_shift xfm_shift = { 225 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 226 }; 227 228 static const struct dce_transform_mask xfm_mask = { 229 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 230 }; 231 232 #define aux_regs(id)\ 233 [id] = {\ 234 AUX_REG_LIST(id)\ 235 } 236 237 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 238 aux_regs(0), 239 aux_regs(1), 240 aux_regs(2), 241 aux_regs(3), 242 aux_regs(4), 243 aux_regs(5) 244 }; 245 246 #define hpd_regs(id)\ 247 [id] = {\ 248 HPD_REG_LIST(id)\ 249 } 250 251 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 252 hpd_regs(0), 253 hpd_regs(1), 254 hpd_regs(2), 255 hpd_regs(3), 256 hpd_regs(4), 257 hpd_regs(5) 258 }; 259 260 #define link_regs(id)\ 261 [id] = {\ 262 LE_DCE110_REG_LIST(id)\ 263 } 264 265 static const struct dce110_link_enc_registers link_enc_regs[] = { 266 link_regs(0), 267 link_regs(1), 268 link_regs(2), 269 link_regs(3), 270 link_regs(4), 271 link_regs(5), 272 link_regs(6), 273 }; 274 275 #define stream_enc_regs(id)\ 276 [id] = {\ 277 SE_COMMON_REG_LIST(id),\ 278 .TMDS_CNTL = 0,\ 279 } 280 281 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 282 stream_enc_regs(0), 283 stream_enc_regs(1), 284 stream_enc_regs(2), 285 stream_enc_regs(3), 286 stream_enc_regs(4), 287 stream_enc_regs(5) 288 }; 289 290 static const struct dce_stream_encoder_shift se_shift = { 291 SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT) 292 }; 293 294 static const struct dce_stream_encoder_mask se_mask = { 295 SE_COMMON_MASK_SH_LIST_DCE112(_MASK) 296 }; 297 298 #define opp_regs(id)\ 299 [id] = {\ 300 OPP_DCE_112_REG_LIST(id),\ 301 } 302 303 static const struct dce_opp_registers opp_regs[] = { 304 opp_regs(0), 305 opp_regs(1), 306 opp_regs(2), 307 opp_regs(3), 308 opp_regs(4), 309 opp_regs(5) 310 }; 311 312 static const struct dce_opp_shift opp_shift = { 313 OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 314 }; 315 316 static const struct dce_opp_mask opp_mask = { 317 OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK) 318 }; 319 320 #define aux_engine_regs(id)\ 321 [id] = {\ 322 AUX_COMMON_REG_LIST(id), \ 323 .AUX_RESET_MASK = 0 \ 324 } 325 326 static const struct dce110_aux_registers aux_engine_regs[] = { 327 aux_engine_regs(0), 328 aux_engine_regs(1), 329 aux_engine_regs(2), 330 aux_engine_regs(3), 331 aux_engine_regs(4), 332 aux_engine_regs(5) 333 }; 334 335 #define audio_regs(id)\ 336 [id] = {\ 337 AUD_COMMON_REG_LIST(id)\ 338 } 339 340 static const struct dce_audio_registers audio_regs[] = { 341 audio_regs(0), 342 audio_regs(1), 343 audio_regs(2), 344 audio_regs(3), 345 audio_regs(4), 346 audio_regs(5) 347 }; 348 349 static const struct dce_audio_shift audio_shift = { 350 AUD_COMMON_MASK_SH_LIST(__SHIFT) 351 }; 352 353 static const struct dce_aduio_mask audio_mask = { 354 AUD_COMMON_MASK_SH_LIST(_MASK) 355 }; 356 357 #define clk_src_regs(index, id)\ 358 [index] = {\ 359 CS_COMMON_REG_LIST_DCE_112(id),\ 360 } 361 362 static const struct dce110_clk_src_regs clk_src_regs[] = { 363 clk_src_regs(0, A), 364 clk_src_regs(1, B), 365 clk_src_regs(2, C), 366 clk_src_regs(3, D), 367 clk_src_regs(4, E), 368 clk_src_regs(5, F) 369 }; 370 371 static const struct dce110_clk_src_shift cs_shift = { 372 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 373 }; 374 375 static const struct dce110_clk_src_mask cs_mask = { 376 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) 377 }; 378 379 static const struct bios_registers bios_regs = { 380 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 381 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 382 }; 383 384 static const struct resource_caps polaris_10_resource_cap = { 385 .num_timing_generator = 6, 386 .num_audio = 6, 387 .num_stream_encoder = 6, 388 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */ 389 .num_ddc = 6, 390 }; 391 392 static const struct resource_caps polaris_11_resource_cap = { 393 .num_timing_generator = 5, 394 .num_audio = 5, 395 .num_stream_encoder = 5, 396 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */ 397 .num_ddc = 5, 398 }; 399 400 #define CTX ctx 401 #define REG(reg) mm ## reg 402 403 #ifndef mmCC_DC_HDMI_STRAPS 404 #define mmCC_DC_HDMI_STRAPS 0x4819 405 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 406 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 407 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 408 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 409 #endif 410 411 static void read_dce_straps( 412 struct dc_context *ctx, 413 struct resource_straps *straps) 414 { 415 REG_GET_2(CC_DC_HDMI_STRAPS, 416 HDMI_DISABLE, &straps->hdmi_disable, 417 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 418 419 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 420 } 421 422 static struct audio *create_audio( 423 struct dc_context *ctx, unsigned int inst) 424 { 425 return dce_audio_create(ctx, inst, 426 &audio_regs[inst], &audio_shift, &audio_mask); 427 } 428 429 430 static struct timing_generator *dce112_timing_generator_create( 431 struct dc_context *ctx, 432 uint32_t instance, 433 const struct dce110_timing_generator_offsets *offsets) 434 { 435 struct dce110_timing_generator *tg110 = 436 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 437 438 if (!tg110) 439 return NULL; 440 441 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 442 return &tg110->base; 443 } 444 445 static struct stream_encoder *dce112_stream_encoder_create( 446 enum engine_id eng_id, 447 struct dc_context *ctx) 448 { 449 struct dce110_stream_encoder *enc110 = 450 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 451 452 if (!enc110) 453 return NULL; 454 455 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 456 &stream_enc_regs[eng_id], 457 &se_shift, &se_mask); 458 return &enc110->base; 459 } 460 461 #define SRII(reg_name, block, id)\ 462 .reg_name[id] = mm ## block ## id ## _ ## reg_name 463 464 static const struct dce_hwseq_registers hwseq_reg = { 465 HWSEQ_DCE112_REG_LIST() 466 }; 467 468 static const struct dce_hwseq_shift hwseq_shift = { 469 HWSEQ_DCE112_MASK_SH_LIST(__SHIFT) 470 }; 471 472 static const struct dce_hwseq_mask hwseq_mask = { 473 HWSEQ_DCE112_MASK_SH_LIST(_MASK) 474 }; 475 476 static struct dce_hwseq *dce112_hwseq_create( 477 struct dc_context *ctx) 478 { 479 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 480 481 if (hws) { 482 hws->ctx = ctx; 483 hws->regs = &hwseq_reg; 484 hws->shifts = &hwseq_shift; 485 hws->masks = &hwseq_mask; 486 } 487 return hws; 488 } 489 490 static const struct resource_create_funcs res_create_funcs = { 491 .read_dce_straps = read_dce_straps, 492 .create_audio = create_audio, 493 .create_stream_encoder = dce112_stream_encoder_create, 494 .create_hwseq = dce112_hwseq_create, 495 }; 496 497 #define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) } 498 static const struct dce_mem_input_registers mi_regs[] = { 499 mi_inst_regs(0), 500 mi_inst_regs(1), 501 mi_inst_regs(2), 502 mi_inst_regs(3), 503 mi_inst_regs(4), 504 mi_inst_regs(5), 505 }; 506 507 static const struct dce_mem_input_shift mi_shifts = { 508 MI_DCE11_2_MASK_SH_LIST(__SHIFT) 509 }; 510 511 static const struct dce_mem_input_mask mi_masks = { 512 MI_DCE11_2_MASK_SH_LIST(_MASK) 513 }; 514 515 static struct mem_input *dce112_mem_input_create( 516 struct dc_context *ctx, 517 uint32_t inst) 518 { 519 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 520 GFP_KERNEL); 521 522 if (!dce_mi) { 523 BREAK_TO_DEBUGGER(); 524 return NULL; 525 } 526 527 dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 528 return &dce_mi->base; 529 } 530 531 static void dce112_transform_destroy(struct transform **xfm) 532 { 533 kfree(TO_DCE_TRANSFORM(*xfm)); 534 *xfm = NULL; 535 } 536 537 static struct transform *dce112_transform_create( 538 struct dc_context *ctx, 539 uint32_t inst) 540 { 541 struct dce_transform *transform = 542 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 543 544 if (!transform) 545 return NULL; 546 547 dce_transform_construct(transform, ctx, inst, 548 &xfm_regs[inst], &xfm_shift, &xfm_mask); 549 transform->lb_memory_size = 0x1404; /*5124*/ 550 return &transform->base; 551 } 552 553 static const struct encoder_feature_support link_enc_feature = { 554 .max_hdmi_deep_color = COLOR_DEPTH_121212, 555 .max_hdmi_pixel_clock = 600000, 556 .hdmi_ycbcr420_supported = true, 557 .dp_ycbcr420_supported = false, 558 .flags.bits.IS_HBR2_CAPABLE = true, 559 .flags.bits.IS_HBR3_CAPABLE = true, 560 .flags.bits.IS_TPS3_CAPABLE = true, 561 .flags.bits.IS_TPS4_CAPABLE = true 562 }; 563 564 struct link_encoder *dce112_link_encoder_create( 565 const struct encoder_init_data *enc_init_data) 566 { 567 struct dce110_link_encoder *enc110 = 568 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 569 570 if (!enc110) 571 return NULL; 572 573 dce110_link_encoder_construct(enc110, 574 enc_init_data, 575 &link_enc_feature, 576 &link_enc_regs[enc_init_data->transmitter], 577 &link_enc_aux_regs[enc_init_data->channel - 1], 578 &link_enc_hpd_regs[enc_init_data->hpd_source]); 579 return &enc110->base; 580 } 581 582 static struct input_pixel_processor *dce112_ipp_create( 583 struct dc_context *ctx, uint32_t inst) 584 { 585 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 586 587 if (!ipp) { 588 BREAK_TO_DEBUGGER(); 589 return NULL; 590 } 591 592 dce_ipp_construct(ipp, ctx, inst, 593 &ipp_regs[inst], &ipp_shift, &ipp_mask); 594 return &ipp->base; 595 } 596 597 struct output_pixel_processor *dce112_opp_create( 598 struct dc_context *ctx, 599 uint32_t inst) 600 { 601 struct dce110_opp *opp = 602 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 603 604 if (!opp) 605 return NULL; 606 607 dce110_opp_construct(opp, 608 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 609 return &opp->base; 610 } 611 612 struct dce_aux *dce112_aux_engine_create( 613 struct dc_context *ctx, 614 uint32_t inst) 615 { 616 struct aux_engine_dce110 *aux_engine = 617 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 618 619 if (!aux_engine) 620 return NULL; 621 622 dce110_aux_engine_construct(aux_engine, ctx, inst, 623 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 624 &aux_engine_regs[inst]); 625 626 return &aux_engine->base; 627 } 628 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 629 630 static const struct dce_i2c_registers i2c_hw_regs[] = { 631 i2c_inst_regs(1), 632 i2c_inst_regs(2), 633 i2c_inst_regs(3), 634 i2c_inst_regs(4), 635 i2c_inst_regs(5), 636 i2c_inst_regs(6), 637 }; 638 639 static const struct dce_i2c_shift i2c_shifts = { 640 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 641 }; 642 643 static const struct dce_i2c_mask i2c_masks = { 644 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 645 }; 646 647 struct dce_i2c_hw *dce112_i2c_hw_create( 648 struct dc_context *ctx, 649 uint32_t inst) 650 { 651 struct dce_i2c_hw *dce_i2c_hw = 652 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 653 654 if (!dce_i2c_hw) 655 return NULL; 656 657 dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst, 658 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 659 660 return dce_i2c_hw; 661 } 662 struct clock_source *dce112_clock_source_create( 663 struct dc_context *ctx, 664 struct dc_bios *bios, 665 enum clock_source_id id, 666 const struct dce110_clk_src_regs *regs, 667 bool dp_clk_src) 668 { 669 struct dce110_clk_src *clk_src = 670 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 671 672 if (!clk_src) 673 return NULL; 674 675 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 676 regs, &cs_shift, &cs_mask)) { 677 clk_src->base.dp_clk_src = dp_clk_src; 678 return &clk_src->base; 679 } 680 681 BREAK_TO_DEBUGGER(); 682 return NULL; 683 } 684 685 void dce112_clock_source_destroy(struct clock_source **clk_src) 686 { 687 kfree(TO_DCE110_CLK_SRC(*clk_src)); 688 *clk_src = NULL; 689 } 690 691 static void destruct(struct dce110_resource_pool *pool) 692 { 693 unsigned int i; 694 695 for (i = 0; i < pool->base.pipe_count; i++) { 696 if (pool->base.opps[i] != NULL) 697 dce110_opp_destroy(&pool->base.opps[i]); 698 699 if (pool->base.transforms[i] != NULL) 700 dce112_transform_destroy(&pool->base.transforms[i]); 701 702 if (pool->base.ipps[i] != NULL) 703 dce_ipp_destroy(&pool->base.ipps[i]); 704 705 if (pool->base.mis[i] != NULL) { 706 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 707 pool->base.mis[i] = NULL; 708 } 709 710 if (pool->base.timing_generators[i] != NULL) { 711 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 712 pool->base.timing_generators[i] = NULL; 713 } 714 } 715 716 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 717 if (pool->base.engines[i] != NULL) 718 dce110_engine_destroy(&pool->base.engines[i]); 719 if (pool->base.hw_i2cs[i] != NULL) { 720 kfree(pool->base.hw_i2cs[i]); 721 pool->base.hw_i2cs[i] = NULL; 722 } 723 if (pool->base.sw_i2cs[i] != NULL) { 724 kfree(pool->base.sw_i2cs[i]); 725 pool->base.sw_i2cs[i] = NULL; 726 } 727 } 728 729 for (i = 0; i < pool->base.stream_enc_count; i++) { 730 if (pool->base.stream_enc[i] != NULL) 731 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 732 } 733 734 for (i = 0; i < pool->base.clk_src_count; i++) { 735 if (pool->base.clock_sources[i] != NULL) { 736 dce112_clock_source_destroy(&pool->base.clock_sources[i]); 737 } 738 } 739 740 if (pool->base.dp_clock_source != NULL) 741 dce112_clock_source_destroy(&pool->base.dp_clock_source); 742 743 for (i = 0; i < pool->base.audio_count; i++) { 744 if (pool->base.audios[i] != NULL) { 745 dce_aud_destroy(&pool->base.audios[i]); 746 } 747 } 748 749 if (pool->base.abm != NULL) 750 dce_abm_destroy(&pool->base.abm); 751 752 if (pool->base.dmcu != NULL) 753 dce_dmcu_destroy(&pool->base.dmcu); 754 755 if (pool->base.clk_mgr != NULL) 756 dce_clk_mgr_destroy(&pool->base.clk_mgr); 757 758 if (pool->base.irqs != NULL) { 759 dal_irq_service_destroy(&pool->base.irqs); 760 } 761 } 762 763 static struct clock_source *find_matching_pll( 764 struct resource_context *res_ctx, 765 const struct resource_pool *pool, 766 const struct dc_stream_state *const stream) 767 { 768 switch (stream->link->link_enc->transmitter) { 769 case TRANSMITTER_UNIPHY_A: 770 return pool->clock_sources[DCE112_CLK_SRC_PLL0]; 771 case TRANSMITTER_UNIPHY_B: 772 return pool->clock_sources[DCE112_CLK_SRC_PLL1]; 773 case TRANSMITTER_UNIPHY_C: 774 return pool->clock_sources[DCE112_CLK_SRC_PLL2]; 775 case TRANSMITTER_UNIPHY_D: 776 return pool->clock_sources[DCE112_CLK_SRC_PLL3]; 777 case TRANSMITTER_UNIPHY_E: 778 return pool->clock_sources[DCE112_CLK_SRC_PLL4]; 779 case TRANSMITTER_UNIPHY_F: 780 return pool->clock_sources[DCE112_CLK_SRC_PLL5]; 781 default: 782 return NULL; 783 }; 784 785 return 0; 786 } 787 788 static enum dc_status build_mapped_resource( 789 const struct dc *dc, 790 struct dc_state *context, 791 struct dc_stream_state *stream) 792 { 793 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 794 795 if (!pipe_ctx) 796 return DC_ERROR_UNEXPECTED; 797 798 dce110_resource_build_pipe_hw_param(pipe_ctx); 799 800 resource_build_info_frame(pipe_ctx); 801 802 return DC_OK; 803 } 804 805 bool dce112_validate_bandwidth( 806 struct dc *dc, 807 struct dc_state *context) 808 { 809 bool result = false; 810 811 DC_LOG_BANDWIDTH_CALCS( 812 "%s: start", 813 __func__); 814 815 if (bw_calcs( 816 dc->ctx, 817 dc->bw_dceip, 818 dc->bw_vbios, 819 context->res_ctx.pipe_ctx, 820 dc->res_pool->pipe_count, 821 &context->bw.dce)) 822 result = true; 823 824 if (!result) 825 DC_LOG_BANDWIDTH_VALIDATION( 826 "%s: Bandwidth validation failed!", 827 __func__); 828 829 if (memcmp(&dc->current_state->bw.dce, 830 &context->bw.dce, sizeof(context->bw.dce))) { 831 832 DC_LOG_BANDWIDTH_CALCS( 833 "%s: finish,\n" 834 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 835 "stutMark_b: %d stutMark_a: %d\n" 836 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 837 "stutMark_b: %d stutMark_a: %d\n" 838 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 839 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n" 840 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" 841 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n" 842 , 843 __func__, 844 context->bw.dce.nbp_state_change_wm_ns[0].b_mark, 845 context->bw.dce.nbp_state_change_wm_ns[0].a_mark, 846 context->bw.dce.urgent_wm_ns[0].b_mark, 847 context->bw.dce.urgent_wm_ns[0].a_mark, 848 context->bw.dce.stutter_exit_wm_ns[0].b_mark, 849 context->bw.dce.stutter_exit_wm_ns[0].a_mark, 850 context->bw.dce.nbp_state_change_wm_ns[1].b_mark, 851 context->bw.dce.nbp_state_change_wm_ns[1].a_mark, 852 context->bw.dce.urgent_wm_ns[1].b_mark, 853 context->bw.dce.urgent_wm_ns[1].a_mark, 854 context->bw.dce.stutter_exit_wm_ns[1].b_mark, 855 context->bw.dce.stutter_exit_wm_ns[1].a_mark, 856 context->bw.dce.nbp_state_change_wm_ns[2].b_mark, 857 context->bw.dce.nbp_state_change_wm_ns[2].a_mark, 858 context->bw.dce.urgent_wm_ns[2].b_mark, 859 context->bw.dce.urgent_wm_ns[2].a_mark, 860 context->bw.dce.stutter_exit_wm_ns[2].b_mark, 861 context->bw.dce.stutter_exit_wm_ns[2].a_mark, 862 context->bw.dce.stutter_mode_enable, 863 context->bw.dce.cpuc_state_change_enable, 864 context->bw.dce.cpup_state_change_enable, 865 context->bw.dce.nbp_state_change_enable, 866 context->bw.dce.all_displays_in_sync, 867 context->bw.dce.dispclk_khz, 868 context->bw.dce.sclk_khz, 869 context->bw.dce.sclk_deep_sleep_khz, 870 context->bw.dce.yclk_khz, 871 context->bw.dce.blackout_recovery_time_us); 872 } 873 return result; 874 } 875 876 enum dc_status resource_map_phy_clock_resources( 877 const struct dc *dc, 878 struct dc_state *context, 879 struct dc_stream_state *stream) 880 { 881 882 /* acquire new resources */ 883 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( 884 &context->res_ctx, stream); 885 886 if (!pipe_ctx) 887 return DC_ERROR_UNEXPECTED; 888 889 if (dc_is_dp_signal(pipe_ctx->stream->signal) 890 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) 891 pipe_ctx->clock_source = 892 dc->res_pool->dp_clock_source; 893 else 894 pipe_ctx->clock_source = find_matching_pll( 895 &context->res_ctx, dc->res_pool, 896 stream); 897 898 if (pipe_ctx->clock_source == NULL) 899 return DC_NO_CLOCK_SOURCE_RESOURCE; 900 901 resource_reference_clock_source( 902 &context->res_ctx, 903 dc->res_pool, 904 pipe_ctx->clock_source); 905 906 return DC_OK; 907 } 908 909 static bool dce112_validate_surface_sets( 910 struct dc_state *context) 911 { 912 int i; 913 914 for (i = 0; i < context->stream_count; i++) { 915 if (context->stream_status[i].plane_count == 0) 916 continue; 917 918 if (context->stream_status[i].plane_count > 1) 919 return false; 920 921 if (context->stream_status[i].plane_states[0]->format 922 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 923 return false; 924 } 925 926 return true; 927 } 928 929 enum dc_status dce112_add_stream_to_ctx( 930 struct dc *dc, 931 struct dc_state *new_ctx, 932 struct dc_stream_state *dc_stream) 933 { 934 enum dc_status result = DC_ERROR_UNEXPECTED; 935 936 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 937 938 if (result == DC_OK) 939 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 940 941 942 if (result == DC_OK) 943 result = build_mapped_resource(dc, new_ctx, dc_stream); 944 945 return result; 946 } 947 948 enum dc_status dce112_validate_global( 949 struct dc *dc, 950 struct dc_state *context) 951 { 952 if (!dce112_validate_surface_sets(context)) 953 return DC_FAIL_SURFACE_VALIDATE; 954 955 return DC_OK; 956 } 957 958 static void dce112_destroy_resource_pool(struct resource_pool **pool) 959 { 960 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 961 962 destruct(dce110_pool); 963 kfree(dce110_pool); 964 *pool = NULL; 965 } 966 967 static const struct resource_funcs dce112_res_pool_funcs = { 968 .destroy = dce112_destroy_resource_pool, 969 .link_enc_create = dce112_link_encoder_create, 970 .validate_bandwidth = dce112_validate_bandwidth, 971 .validate_plane = dce100_validate_plane, 972 .add_stream_to_ctx = dce112_add_stream_to_ctx, 973 .validate_global = dce112_validate_global 974 }; 975 976 static void bw_calcs_data_update_from_pplib(struct dc *dc) 977 { 978 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 979 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 980 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; 981 struct dm_pp_clock_levels clks = {0}; 982 983 /*do system clock TODO PPLIB: after PPLIB implement, 984 * then remove old way 985 */ 986 if (!dm_pp_get_clock_levels_by_type_with_latency( 987 dc->ctx, 988 DM_PP_CLOCK_TYPE_ENGINE_CLK, 989 &eng_clks)) { 990 991 /* This is only for temporary */ 992 dm_pp_get_clock_levels_by_type( 993 dc->ctx, 994 DM_PP_CLOCK_TYPE_ENGINE_CLK, 995 &clks); 996 /* convert all the clock fro kHz to fix point mHz */ 997 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 998 clks.clocks_in_khz[clks.num_levels-1], 1000); 999 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 1000 clks.clocks_in_khz[clks.num_levels/8], 1000); 1001 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 1002 clks.clocks_in_khz[clks.num_levels*2/8], 1000); 1003 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 1004 clks.clocks_in_khz[clks.num_levels*3/8], 1000); 1005 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 1006 clks.clocks_in_khz[clks.num_levels*4/8], 1000); 1007 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 1008 clks.clocks_in_khz[clks.num_levels*5/8], 1000); 1009 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1010 clks.clocks_in_khz[clks.num_levels*6/8], 1000); 1011 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1012 clks.clocks_in_khz[0], 1000); 1013 1014 /*do memory clock*/ 1015 dm_pp_get_clock_levels_by_type( 1016 dc->ctx, 1017 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1018 &clks); 1019 1020 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1021 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER_CZ, 1000); 1022 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1023 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ, 1024 1000); 1025 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1026 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER_CZ, 1027 1000); 1028 1029 return; 1030 } 1031 1032 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ 1033 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 1034 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); 1035 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 1036 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); 1037 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 1038 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); 1039 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 1040 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); 1041 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 1042 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); 1043 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 1044 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); 1045 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1046 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); 1047 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1048 eng_clks.data[0].clocks_in_khz, 1000); 1049 1050 /*do memory clock*/ 1051 dm_pp_get_clock_levels_by_type_with_latency( 1052 dc->ctx, 1053 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1054 &mem_clks); 1055 1056 /* we don't need to call PPLIB for validation clock since they 1057 * also give us the highest sclk and highest mclk (UMA clock). 1058 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): 1059 * YCLK = UMACLK*m_memoryTypeMultiplier 1060 */ 1061 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1062 mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 1000); 1063 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1064 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 1065 1000); 1066 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1067 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 1068 1000); 1069 1070 /* Now notify PPLib/SMU about which Watermarks sets they should select 1071 * depending on DPM state they are in. And update BW MGR GFX Engine and 1072 * Memory clock member variables for Watermarks calculations for each 1073 * Watermark Set 1074 */ 1075 clk_ranges.num_wm_sets = 4; 1076 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; 1077 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = 1078 eng_clks.data[0].clocks_in_khz; 1079 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = 1080 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 1081 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz = 1082 mem_clks.data[0].clocks_in_khz; 1083 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = 1084 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 1085 1086 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; 1087 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = 1088 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 1089 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 1090 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; 1091 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz = 1092 mem_clks.data[0].clocks_in_khz; 1093 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = 1094 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 1095 1096 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; 1097 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = 1098 eng_clks.data[0].clocks_in_khz; 1099 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = 1100 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 1101 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz = 1102 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 1103 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 1104 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; 1105 1106 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; 1107 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = 1108 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 1109 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 1110 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; 1111 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz = 1112 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 1113 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 1114 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; 1115 1116 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 1117 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); 1118 } 1119 1120 const struct resource_caps *dce112_resource_cap( 1121 struct hw_asic_id *asic_id) 1122 { 1123 if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) || 1124 ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev)) 1125 return &polaris_11_resource_cap; 1126 else 1127 return &polaris_10_resource_cap; 1128 } 1129 1130 static bool construct( 1131 uint8_t num_virtual_links, 1132 struct dc *dc, 1133 struct dce110_resource_pool *pool) 1134 { 1135 unsigned int i; 1136 struct dc_context *ctx = dc->ctx; 1137 1138 ctx->dc_bios->regs = &bios_regs; 1139 1140 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id); 1141 pool->base.funcs = &dce112_res_pool_funcs; 1142 1143 /************************************************* 1144 * Resource + asic cap harcoding * 1145 *************************************************/ 1146 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1147 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1148 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1149 dc->caps.max_downscale_ratio = 200; 1150 dc->caps.i2c_speed_in_khz = 100; 1151 dc->caps.max_cursor_size = 128; 1152 dc->caps.dual_link_dvi = true; 1153 1154 1155 /************************************************* 1156 * Create resources * 1157 *************************************************/ 1158 1159 pool->base.clock_sources[DCE112_CLK_SRC_PLL0] = 1160 dce112_clock_source_create( 1161 ctx, ctx->dc_bios, 1162 CLOCK_SOURCE_COMBO_PHY_PLL0, 1163 &clk_src_regs[0], false); 1164 pool->base.clock_sources[DCE112_CLK_SRC_PLL1] = 1165 dce112_clock_source_create( 1166 ctx, ctx->dc_bios, 1167 CLOCK_SOURCE_COMBO_PHY_PLL1, 1168 &clk_src_regs[1], false); 1169 pool->base.clock_sources[DCE112_CLK_SRC_PLL2] = 1170 dce112_clock_source_create( 1171 ctx, ctx->dc_bios, 1172 CLOCK_SOURCE_COMBO_PHY_PLL2, 1173 &clk_src_regs[2], false); 1174 pool->base.clock_sources[DCE112_CLK_SRC_PLL3] = 1175 dce112_clock_source_create( 1176 ctx, ctx->dc_bios, 1177 CLOCK_SOURCE_COMBO_PHY_PLL3, 1178 &clk_src_regs[3], false); 1179 pool->base.clock_sources[DCE112_CLK_SRC_PLL4] = 1180 dce112_clock_source_create( 1181 ctx, ctx->dc_bios, 1182 CLOCK_SOURCE_COMBO_PHY_PLL4, 1183 &clk_src_regs[4], false); 1184 pool->base.clock_sources[DCE112_CLK_SRC_PLL5] = 1185 dce112_clock_source_create( 1186 ctx, ctx->dc_bios, 1187 CLOCK_SOURCE_COMBO_PHY_PLL5, 1188 &clk_src_regs[5], false); 1189 pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL; 1190 1191 pool->base.dp_clock_source = dce112_clock_source_create( 1192 ctx, ctx->dc_bios, 1193 CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); 1194 1195 1196 for (i = 0; i < pool->base.clk_src_count; i++) { 1197 if (pool->base.clock_sources[i] == NULL) { 1198 dm_error("DC: failed to create clock sources!\n"); 1199 BREAK_TO_DEBUGGER(); 1200 goto res_create_fail; 1201 } 1202 } 1203 1204 pool->base.clk_mgr = dce112_clk_mgr_create(ctx, 1205 &disp_clk_regs, 1206 &disp_clk_shift, 1207 &disp_clk_mask); 1208 if (pool->base.clk_mgr == NULL) { 1209 dm_error("DC: failed to create display clock!\n"); 1210 BREAK_TO_DEBUGGER(); 1211 goto res_create_fail; 1212 } 1213 1214 pool->base.dmcu = dce_dmcu_create(ctx, 1215 &dmcu_regs, 1216 &dmcu_shift, 1217 &dmcu_mask); 1218 if (pool->base.dmcu == NULL) { 1219 dm_error("DC: failed to create dmcu!\n"); 1220 BREAK_TO_DEBUGGER(); 1221 goto res_create_fail; 1222 } 1223 1224 pool->base.abm = dce_abm_create(ctx, 1225 &abm_regs, 1226 &abm_shift, 1227 &abm_mask); 1228 if (pool->base.abm == NULL) { 1229 dm_error("DC: failed to create abm!\n"); 1230 BREAK_TO_DEBUGGER(); 1231 goto res_create_fail; 1232 } 1233 1234 { 1235 struct irq_service_init_data init_data; 1236 init_data.ctx = dc->ctx; 1237 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 1238 if (!pool->base.irqs) 1239 goto res_create_fail; 1240 } 1241 1242 for (i = 0; i < pool->base.pipe_count; i++) { 1243 pool->base.timing_generators[i] = 1244 dce112_timing_generator_create( 1245 ctx, 1246 i, 1247 &dce112_tg_offsets[i]); 1248 if (pool->base.timing_generators[i] == NULL) { 1249 BREAK_TO_DEBUGGER(); 1250 dm_error("DC: failed to create tg!\n"); 1251 goto res_create_fail; 1252 } 1253 1254 pool->base.mis[i] = dce112_mem_input_create(ctx, i); 1255 if (pool->base.mis[i] == NULL) { 1256 BREAK_TO_DEBUGGER(); 1257 dm_error( 1258 "DC: failed to create memory input!\n"); 1259 goto res_create_fail; 1260 } 1261 1262 pool->base.ipps[i] = dce112_ipp_create(ctx, i); 1263 if (pool->base.ipps[i] == NULL) { 1264 BREAK_TO_DEBUGGER(); 1265 dm_error( 1266 "DC:failed to create input pixel processor!\n"); 1267 goto res_create_fail; 1268 } 1269 1270 pool->base.transforms[i] = dce112_transform_create(ctx, i); 1271 if (pool->base.transforms[i] == NULL) { 1272 BREAK_TO_DEBUGGER(); 1273 dm_error( 1274 "DC: failed to create transform!\n"); 1275 goto res_create_fail; 1276 } 1277 1278 pool->base.opps[i] = dce112_opp_create( 1279 ctx, 1280 i); 1281 if (pool->base.opps[i] == NULL) { 1282 BREAK_TO_DEBUGGER(); 1283 dm_error( 1284 "DC:failed to create output pixel processor!\n"); 1285 goto res_create_fail; 1286 } 1287 } 1288 1289 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1290 pool->base.engines[i] = dce112_aux_engine_create(ctx, i); 1291 if (pool->base.engines[i] == NULL) { 1292 BREAK_TO_DEBUGGER(); 1293 dm_error( 1294 "DC:failed to create aux engine!!\n"); 1295 goto res_create_fail; 1296 } 1297 pool->base.hw_i2cs[i] = dce112_i2c_hw_create(ctx, i); 1298 if (pool->base.hw_i2cs[i] == NULL) { 1299 BREAK_TO_DEBUGGER(); 1300 dm_error( 1301 "DC:failed to create i2c engine!!\n"); 1302 goto res_create_fail; 1303 } 1304 pool->base.sw_i2cs[i] = NULL; 1305 } 1306 1307 if (!resource_construct(num_virtual_links, dc, &pool->base, 1308 &res_create_funcs)) 1309 goto res_create_fail; 1310 1311 dc->caps.max_planes = pool->base.pipe_count; 1312 1313 /* Create hardware sequencer */ 1314 dce112_hw_sequencer_construct(dc); 1315 1316 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1317 1318 bw_calcs_data_update_from_pplib(dc); 1319 1320 return true; 1321 1322 res_create_fail: 1323 destruct(pool); 1324 return false; 1325 } 1326 1327 struct resource_pool *dce112_create_resource_pool( 1328 uint8_t num_virtual_links, 1329 struct dc *dc) 1330 { 1331 struct dce110_resource_pool *pool = 1332 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1333 1334 if (!pool) 1335 return NULL; 1336 1337 if (construct(num_virtual_links, dc, pool)) 1338 return &pool->base; 1339 1340 BREAK_TO_DEBUGGER(); 1341 return NULL; 1342 } 1343