1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "link_encoder.h" 29 #include "stream_encoder.h" 30 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dce110/dce110_resource.h" 34 #include "dce110/dce110_timing_generator.h" 35 36 #include "irq/dce110/irq_service_dce110.h" 37 38 #include "dce/dce_mem_input.h" 39 #include "dce/dce_transform.h" 40 #include "dce/dce_link_encoder.h" 41 #include "dce/dce_stream_encoder.h" 42 #include "dce/dce_audio.h" 43 #include "dce/dce_opp.h" 44 #include "dce/dce_ipp.h" 45 #include "dce/dce_clocks.h" 46 #include "dce/dce_clock_source.h" 47 48 #include "dce/dce_hwseq.h" 49 #include "dce112/dce112_hw_sequencer.h" 50 #include "dce/dce_abm.h" 51 #include "dce/dce_dmcu.h" 52 53 #include "reg_helper.h" 54 55 #include "dce/dce_11_2_d.h" 56 #include "dce/dce_11_2_sh_mask.h" 57 58 #include "dce100/dce100_resource.h" 59 60 #ifndef mmDP_DPHY_INTERNAL_CTRL 61 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 62 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 63 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 64 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 65 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 66 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 67 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 68 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 69 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 70 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 71 #endif 72 73 #ifndef mmBIOS_SCRATCH_2 74 #define mmBIOS_SCRATCH_2 0x05CB 75 #define mmBIOS_SCRATCH_6 0x05CF 76 #endif 77 78 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 79 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 80 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 81 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 82 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 83 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 84 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 85 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 86 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 87 #endif 88 89 #ifndef mmDP_DPHY_FAST_TRAINING 90 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 91 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 92 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 93 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 94 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 95 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 96 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 97 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 98 #endif 99 100 enum dce112_clk_src_array_id { 101 DCE112_CLK_SRC_PLL0, 102 DCE112_CLK_SRC_PLL1, 103 DCE112_CLK_SRC_PLL2, 104 DCE112_CLK_SRC_PLL3, 105 DCE112_CLK_SRC_PLL4, 106 DCE112_CLK_SRC_PLL5, 107 108 DCE112_CLK_SRC_TOTAL 109 }; 110 111 static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = { 112 { 113 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 114 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 115 }, 116 { 117 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 118 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 119 }, 120 { 121 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 122 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 123 }, 124 { 125 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 126 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 127 }, 128 { 129 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 130 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 131 }, 132 { 133 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 134 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 135 } 136 }; 137 138 /* set register offset */ 139 #define SR(reg_name)\ 140 .reg_name = mm ## reg_name 141 142 /* set register offset with instance */ 143 #define SRI(reg_name, block, id)\ 144 .reg_name = mm ## block ## id ## _ ## reg_name 145 146 147 static const struct dce_disp_clk_registers disp_clk_regs = { 148 CLK_COMMON_REG_LIST_DCE_BASE() 149 }; 150 151 static const struct dce_disp_clk_shift disp_clk_shift = { 152 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 153 }; 154 155 static const struct dce_disp_clk_mask disp_clk_mask = { 156 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 157 }; 158 159 static const struct dce_dmcu_registers dmcu_regs = { 160 DMCU_DCE110_COMMON_REG_LIST() 161 }; 162 163 static const struct dce_dmcu_shift dmcu_shift = { 164 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 165 }; 166 167 static const struct dce_dmcu_mask dmcu_mask = { 168 DMCU_MASK_SH_LIST_DCE110(_MASK) 169 }; 170 171 static const struct dce_abm_registers abm_regs = { 172 ABM_DCE110_COMMON_REG_LIST() 173 }; 174 175 static const struct dce_abm_shift abm_shift = { 176 ABM_MASK_SH_LIST_DCE110(__SHIFT) 177 }; 178 179 static const struct dce_abm_mask abm_mask = { 180 ABM_MASK_SH_LIST_DCE110(_MASK) 181 }; 182 183 #define ipp_regs(id)\ 184 [id] = {\ 185 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 186 } 187 188 static const struct dce_ipp_registers ipp_regs[] = { 189 ipp_regs(0), 190 ipp_regs(1), 191 ipp_regs(2), 192 ipp_regs(3), 193 ipp_regs(4), 194 ipp_regs(5) 195 }; 196 197 static const struct dce_ipp_shift ipp_shift = { 198 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 199 }; 200 201 static const struct dce_ipp_mask ipp_mask = { 202 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 203 }; 204 205 #define transform_regs(id)\ 206 [id] = {\ 207 XFM_COMMON_REG_LIST_DCE110(id)\ 208 } 209 210 static const struct dce_transform_registers xfm_regs[] = { 211 transform_regs(0), 212 transform_regs(1), 213 transform_regs(2), 214 transform_regs(3), 215 transform_regs(4), 216 transform_regs(5) 217 }; 218 219 static const struct dce_transform_shift xfm_shift = { 220 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 221 }; 222 223 static const struct dce_transform_mask xfm_mask = { 224 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 225 }; 226 227 #define aux_regs(id)\ 228 [id] = {\ 229 AUX_REG_LIST(id)\ 230 } 231 232 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 233 aux_regs(0), 234 aux_regs(1), 235 aux_regs(2), 236 aux_regs(3), 237 aux_regs(4), 238 aux_regs(5) 239 }; 240 241 #define hpd_regs(id)\ 242 [id] = {\ 243 HPD_REG_LIST(id)\ 244 } 245 246 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 247 hpd_regs(0), 248 hpd_regs(1), 249 hpd_regs(2), 250 hpd_regs(3), 251 hpd_regs(4), 252 hpd_regs(5) 253 }; 254 255 #define link_regs(id)\ 256 [id] = {\ 257 LE_DCE110_REG_LIST(id)\ 258 } 259 260 static const struct dce110_link_enc_registers link_enc_regs[] = { 261 link_regs(0), 262 link_regs(1), 263 link_regs(2), 264 link_regs(3), 265 link_regs(4), 266 link_regs(5), 267 link_regs(6), 268 }; 269 270 #define stream_enc_regs(id)\ 271 [id] = {\ 272 SE_COMMON_REG_LIST(id),\ 273 .TMDS_CNTL = 0,\ 274 } 275 276 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 277 stream_enc_regs(0), 278 stream_enc_regs(1), 279 stream_enc_regs(2), 280 stream_enc_regs(3), 281 stream_enc_regs(4), 282 stream_enc_regs(5) 283 }; 284 285 static const struct dce_stream_encoder_shift se_shift = { 286 SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT) 287 }; 288 289 static const struct dce_stream_encoder_mask se_mask = { 290 SE_COMMON_MASK_SH_LIST_DCE112(_MASK) 291 }; 292 293 #define opp_regs(id)\ 294 [id] = {\ 295 OPP_DCE_112_REG_LIST(id),\ 296 } 297 298 static const struct dce_opp_registers opp_regs[] = { 299 opp_regs(0), 300 opp_regs(1), 301 opp_regs(2), 302 opp_regs(3), 303 opp_regs(4), 304 opp_regs(5) 305 }; 306 307 static const struct dce_opp_shift opp_shift = { 308 OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 309 }; 310 311 static const struct dce_opp_mask opp_mask = { 312 OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK) 313 }; 314 315 #define audio_regs(id)\ 316 [id] = {\ 317 AUD_COMMON_REG_LIST(id)\ 318 } 319 320 static const struct dce_audio_registers audio_regs[] = { 321 audio_regs(0), 322 audio_regs(1), 323 audio_regs(2), 324 audio_regs(3), 325 audio_regs(4), 326 audio_regs(5) 327 }; 328 329 static const struct dce_audio_shift audio_shift = { 330 AUD_COMMON_MASK_SH_LIST(__SHIFT) 331 }; 332 333 static const struct dce_aduio_mask audio_mask = { 334 AUD_COMMON_MASK_SH_LIST(_MASK) 335 }; 336 337 #define clk_src_regs(index, id)\ 338 [index] = {\ 339 CS_COMMON_REG_LIST_DCE_112(id),\ 340 } 341 342 static const struct dce110_clk_src_regs clk_src_regs[] = { 343 clk_src_regs(0, A), 344 clk_src_regs(1, B), 345 clk_src_regs(2, C), 346 clk_src_regs(3, D), 347 clk_src_regs(4, E), 348 clk_src_regs(5, F) 349 }; 350 351 static const struct dce110_clk_src_shift cs_shift = { 352 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 353 }; 354 355 static const struct dce110_clk_src_mask cs_mask = { 356 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) 357 }; 358 359 static const struct bios_registers bios_regs = { 360 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 361 }; 362 363 static const struct resource_caps polaris_10_resource_cap = { 364 .num_timing_generator = 6, 365 .num_audio = 6, 366 .num_stream_encoder = 6, 367 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */ 368 }; 369 370 static const struct resource_caps polaris_11_resource_cap = { 371 .num_timing_generator = 5, 372 .num_audio = 5, 373 .num_stream_encoder = 5, 374 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */ 375 }; 376 377 #define CTX ctx 378 #define REG(reg) mm ## reg 379 380 #ifndef mmCC_DC_HDMI_STRAPS 381 #define mmCC_DC_HDMI_STRAPS 0x4819 382 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 383 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 384 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 385 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 386 #endif 387 388 static void read_dce_straps( 389 struct dc_context *ctx, 390 struct resource_straps *straps) 391 { 392 REG_GET_2(CC_DC_HDMI_STRAPS, 393 HDMI_DISABLE, &straps->hdmi_disable, 394 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 395 396 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 397 } 398 399 static struct audio *create_audio( 400 struct dc_context *ctx, unsigned int inst) 401 { 402 return dce_audio_create(ctx, inst, 403 &audio_regs[inst], &audio_shift, &audio_mask); 404 } 405 406 407 static struct timing_generator *dce112_timing_generator_create( 408 struct dc_context *ctx, 409 uint32_t instance, 410 const struct dce110_timing_generator_offsets *offsets) 411 { 412 struct dce110_timing_generator *tg110 = 413 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 414 415 if (!tg110) 416 return NULL; 417 418 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 419 return &tg110->base; 420 } 421 422 static struct stream_encoder *dce112_stream_encoder_create( 423 enum engine_id eng_id, 424 struct dc_context *ctx) 425 { 426 struct dce110_stream_encoder *enc110 = 427 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 428 429 if (!enc110) 430 return NULL; 431 432 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 433 &stream_enc_regs[eng_id], 434 &se_shift, &se_mask); 435 return &enc110->base; 436 } 437 438 #define SRII(reg_name, block, id)\ 439 .reg_name[id] = mm ## block ## id ## _ ## reg_name 440 441 static const struct dce_hwseq_registers hwseq_reg = { 442 HWSEQ_DCE112_REG_LIST() 443 }; 444 445 static const struct dce_hwseq_shift hwseq_shift = { 446 HWSEQ_DCE112_MASK_SH_LIST(__SHIFT) 447 }; 448 449 static const struct dce_hwseq_mask hwseq_mask = { 450 HWSEQ_DCE112_MASK_SH_LIST(_MASK) 451 }; 452 453 static struct dce_hwseq *dce112_hwseq_create( 454 struct dc_context *ctx) 455 { 456 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 457 458 if (hws) { 459 hws->ctx = ctx; 460 hws->regs = &hwseq_reg; 461 hws->shifts = &hwseq_shift; 462 hws->masks = &hwseq_mask; 463 } 464 return hws; 465 } 466 467 static const struct resource_create_funcs res_create_funcs = { 468 .read_dce_straps = read_dce_straps, 469 .create_audio = create_audio, 470 .create_stream_encoder = dce112_stream_encoder_create, 471 .create_hwseq = dce112_hwseq_create, 472 }; 473 474 #define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) } 475 static const struct dce_mem_input_registers mi_regs[] = { 476 mi_inst_regs(0), 477 mi_inst_regs(1), 478 mi_inst_regs(2), 479 mi_inst_regs(3), 480 mi_inst_regs(4), 481 mi_inst_regs(5), 482 }; 483 484 static const struct dce_mem_input_shift mi_shifts = { 485 MI_DCE11_2_MASK_SH_LIST(__SHIFT) 486 }; 487 488 static const struct dce_mem_input_mask mi_masks = { 489 MI_DCE11_2_MASK_SH_LIST(_MASK) 490 }; 491 492 static struct mem_input *dce112_mem_input_create( 493 struct dc_context *ctx, 494 uint32_t inst) 495 { 496 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 497 GFP_KERNEL); 498 499 if (!dce_mi) { 500 BREAK_TO_DEBUGGER(); 501 return NULL; 502 } 503 504 dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 505 return &dce_mi->base; 506 } 507 508 static void dce112_transform_destroy(struct transform **xfm) 509 { 510 kfree(TO_DCE_TRANSFORM(*xfm)); 511 *xfm = NULL; 512 } 513 514 static struct transform *dce112_transform_create( 515 struct dc_context *ctx, 516 uint32_t inst) 517 { 518 struct dce_transform *transform = 519 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 520 521 if (!transform) 522 return NULL; 523 524 dce_transform_construct(transform, ctx, inst, 525 &xfm_regs[inst], &xfm_shift, &xfm_mask); 526 transform->lb_memory_size = 0x1404; /*5124*/ 527 return &transform->base; 528 } 529 530 static const struct encoder_feature_support link_enc_feature = { 531 .max_hdmi_deep_color = COLOR_DEPTH_121212, 532 .max_hdmi_pixel_clock = 600000, 533 .ycbcr420_supported = true, 534 .flags.bits.IS_HBR2_CAPABLE = true, 535 .flags.bits.IS_HBR3_CAPABLE = true, 536 .flags.bits.IS_TPS3_CAPABLE = true, 537 .flags.bits.IS_TPS4_CAPABLE = true, 538 .flags.bits.IS_YCBCR_CAPABLE = true 539 }; 540 541 struct link_encoder *dce112_link_encoder_create( 542 const struct encoder_init_data *enc_init_data) 543 { 544 struct dce110_link_encoder *enc110 = 545 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 546 547 if (!enc110) 548 return NULL; 549 550 dce110_link_encoder_construct(enc110, 551 enc_init_data, 552 &link_enc_feature, 553 &link_enc_regs[enc_init_data->transmitter], 554 &link_enc_aux_regs[enc_init_data->channel - 1], 555 &link_enc_hpd_regs[enc_init_data->hpd_source]); 556 return &enc110->base; 557 } 558 559 static struct input_pixel_processor *dce112_ipp_create( 560 struct dc_context *ctx, uint32_t inst) 561 { 562 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 563 564 if (!ipp) { 565 BREAK_TO_DEBUGGER(); 566 return NULL; 567 } 568 569 dce_ipp_construct(ipp, ctx, inst, 570 &ipp_regs[inst], &ipp_shift, &ipp_mask); 571 return &ipp->base; 572 } 573 574 struct output_pixel_processor *dce112_opp_create( 575 struct dc_context *ctx, 576 uint32_t inst) 577 { 578 struct dce110_opp *opp = 579 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 580 581 if (!opp) 582 return NULL; 583 584 dce110_opp_construct(opp, 585 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 586 return &opp->base; 587 } 588 589 struct clock_source *dce112_clock_source_create( 590 struct dc_context *ctx, 591 struct dc_bios *bios, 592 enum clock_source_id id, 593 const struct dce110_clk_src_regs *regs, 594 bool dp_clk_src) 595 { 596 struct dce110_clk_src *clk_src = 597 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 598 599 if (!clk_src) 600 return NULL; 601 602 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 603 regs, &cs_shift, &cs_mask)) { 604 clk_src->base.dp_clk_src = dp_clk_src; 605 return &clk_src->base; 606 } 607 608 BREAK_TO_DEBUGGER(); 609 return NULL; 610 } 611 612 void dce112_clock_source_destroy(struct clock_source **clk_src) 613 { 614 kfree(TO_DCE110_CLK_SRC(*clk_src)); 615 *clk_src = NULL; 616 } 617 618 static void destruct(struct dce110_resource_pool *pool) 619 { 620 unsigned int i; 621 622 for (i = 0; i < pool->base.pipe_count; i++) { 623 if (pool->base.opps[i] != NULL) 624 dce110_opp_destroy(&pool->base.opps[i]); 625 626 if (pool->base.transforms[i] != NULL) 627 dce112_transform_destroy(&pool->base.transforms[i]); 628 629 if (pool->base.ipps[i] != NULL) 630 dce_ipp_destroy(&pool->base.ipps[i]); 631 632 if (pool->base.mis[i] != NULL) { 633 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 634 pool->base.mis[i] = NULL; 635 } 636 637 if (pool->base.timing_generators[i] != NULL) { 638 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 639 pool->base.timing_generators[i] = NULL; 640 } 641 } 642 643 for (i = 0; i < pool->base.stream_enc_count; i++) { 644 if (pool->base.stream_enc[i] != NULL) 645 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 646 } 647 648 for (i = 0; i < pool->base.clk_src_count; i++) { 649 if (pool->base.clock_sources[i] != NULL) { 650 dce112_clock_source_destroy(&pool->base.clock_sources[i]); 651 } 652 } 653 654 if (pool->base.dp_clock_source != NULL) 655 dce112_clock_source_destroy(&pool->base.dp_clock_source); 656 657 for (i = 0; i < pool->base.audio_count; i++) { 658 if (pool->base.audios[i] != NULL) { 659 dce_aud_destroy(&pool->base.audios[i]); 660 } 661 } 662 663 if (pool->base.abm != NULL) 664 dce_abm_destroy(&pool->base.abm); 665 666 if (pool->base.dmcu != NULL) 667 dce_dmcu_destroy(&pool->base.dmcu); 668 669 if (pool->base.display_clock != NULL) 670 dce_disp_clk_destroy(&pool->base.display_clock); 671 672 if (pool->base.irqs != NULL) { 673 dal_irq_service_destroy(&pool->base.irqs); 674 } 675 } 676 677 static struct clock_source *find_matching_pll( 678 struct resource_context *res_ctx, 679 const struct resource_pool *pool, 680 const struct dc_stream_state *const stream) 681 { 682 switch (stream->sink->link->link_enc->transmitter) { 683 case TRANSMITTER_UNIPHY_A: 684 return pool->clock_sources[DCE112_CLK_SRC_PLL0]; 685 case TRANSMITTER_UNIPHY_B: 686 return pool->clock_sources[DCE112_CLK_SRC_PLL1]; 687 case TRANSMITTER_UNIPHY_C: 688 return pool->clock_sources[DCE112_CLK_SRC_PLL2]; 689 case TRANSMITTER_UNIPHY_D: 690 return pool->clock_sources[DCE112_CLK_SRC_PLL3]; 691 case TRANSMITTER_UNIPHY_E: 692 return pool->clock_sources[DCE112_CLK_SRC_PLL4]; 693 case TRANSMITTER_UNIPHY_F: 694 return pool->clock_sources[DCE112_CLK_SRC_PLL5]; 695 default: 696 return NULL; 697 }; 698 699 return 0; 700 } 701 702 static enum dc_status build_mapped_resource( 703 const struct dc *dc, 704 struct dc_state *context, 705 struct dc_stream_state *stream) 706 { 707 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 708 709 if (!pipe_ctx) 710 return DC_ERROR_UNEXPECTED; 711 712 dce110_resource_build_pipe_hw_param(pipe_ctx); 713 714 resource_build_info_frame(pipe_ctx); 715 716 return DC_OK; 717 } 718 719 bool dce112_validate_bandwidth( 720 struct dc *dc, 721 struct dc_state *context) 722 { 723 bool result = false; 724 725 dm_logger_write( 726 dc->ctx->logger, LOG_BANDWIDTH_CALCS, 727 "%s: start", 728 __func__); 729 730 if (bw_calcs( 731 dc->ctx, 732 dc->bw_dceip, 733 dc->bw_vbios, 734 context->res_ctx.pipe_ctx, 735 dc->res_pool->pipe_count, 736 &context->bw.dce)) 737 result = true; 738 739 if (!result) 740 dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION, 741 "%s: Bandwidth validation failed!", 742 __func__); 743 744 if (memcmp(&dc->current_state->bw.dce, 745 &context->bw.dce, sizeof(context->bw.dce))) { 746 struct log_entry log_entry; 747 dm_logger_open( 748 dc->ctx->logger, 749 &log_entry, 750 LOG_BANDWIDTH_CALCS); 751 dm_logger_append(&log_entry, "%s: finish,\n" 752 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 753 "stutMark_b: %d stutMark_a: %d\n", 754 __func__, 755 context->bw.dce.nbp_state_change_wm_ns[0].b_mark, 756 context->bw.dce.nbp_state_change_wm_ns[0].a_mark, 757 context->bw.dce.urgent_wm_ns[0].b_mark, 758 context->bw.dce.urgent_wm_ns[0].a_mark, 759 context->bw.dce.stutter_exit_wm_ns[0].b_mark, 760 context->bw.dce.stutter_exit_wm_ns[0].a_mark); 761 dm_logger_append(&log_entry, 762 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 763 "stutMark_b: %d stutMark_a: %d\n", 764 context->bw.dce.nbp_state_change_wm_ns[1].b_mark, 765 context->bw.dce.nbp_state_change_wm_ns[1].a_mark, 766 context->bw.dce.urgent_wm_ns[1].b_mark, 767 context->bw.dce.urgent_wm_ns[1].a_mark, 768 context->bw.dce.stutter_exit_wm_ns[1].b_mark, 769 context->bw.dce.stutter_exit_wm_ns[1].a_mark); 770 dm_logger_append(&log_entry, 771 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 772 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n", 773 context->bw.dce.nbp_state_change_wm_ns[2].b_mark, 774 context->bw.dce.nbp_state_change_wm_ns[2].a_mark, 775 context->bw.dce.urgent_wm_ns[2].b_mark, 776 context->bw.dce.urgent_wm_ns[2].a_mark, 777 context->bw.dce.stutter_exit_wm_ns[2].b_mark, 778 context->bw.dce.stutter_exit_wm_ns[2].a_mark, 779 context->bw.dce.stutter_mode_enable); 780 dm_logger_append(&log_entry, 781 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" 782 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n", 783 context->bw.dce.cpuc_state_change_enable, 784 context->bw.dce.cpup_state_change_enable, 785 context->bw.dce.nbp_state_change_enable, 786 context->bw.dce.all_displays_in_sync, 787 context->bw.dce.dispclk_khz, 788 context->bw.dce.sclk_khz, 789 context->bw.dce.sclk_deep_sleep_khz, 790 context->bw.dce.yclk_khz, 791 context->bw.dce.blackout_recovery_time_us); 792 dm_logger_close(&log_entry); 793 } 794 return result; 795 } 796 797 enum dc_status resource_map_phy_clock_resources( 798 const struct dc *dc, 799 struct dc_state *context, 800 struct dc_stream_state *stream) 801 { 802 803 /* acquire new resources */ 804 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( 805 &context->res_ctx, stream); 806 807 if (!pipe_ctx) 808 return DC_ERROR_UNEXPECTED; 809 810 if (dc_is_dp_signal(pipe_ctx->stream->signal) 811 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) 812 pipe_ctx->clock_source = 813 dc->res_pool->dp_clock_source; 814 else 815 pipe_ctx->clock_source = find_matching_pll( 816 &context->res_ctx, dc->res_pool, 817 stream); 818 819 if (pipe_ctx->clock_source == NULL) 820 return DC_NO_CLOCK_SOURCE_RESOURCE; 821 822 resource_reference_clock_source( 823 &context->res_ctx, 824 dc->res_pool, 825 pipe_ctx->clock_source); 826 827 return DC_OK; 828 } 829 830 static bool dce112_validate_surface_sets( 831 struct dc_state *context) 832 { 833 int i; 834 835 for (i = 0; i < context->stream_count; i++) { 836 if (context->stream_status[i].plane_count == 0) 837 continue; 838 839 if (context->stream_status[i].plane_count > 1) 840 return false; 841 842 if (context->stream_status[i].plane_states[0]->format 843 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 844 return false; 845 } 846 847 return true; 848 } 849 850 enum dc_status dce112_add_stream_to_ctx( 851 struct dc *dc, 852 struct dc_state *new_ctx, 853 struct dc_stream_state *dc_stream) 854 { 855 enum dc_status result = DC_ERROR_UNEXPECTED; 856 857 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 858 859 if (result == DC_OK) 860 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 861 862 863 if (result == DC_OK) 864 result = build_mapped_resource(dc, new_ctx, dc_stream); 865 866 return result; 867 } 868 869 enum dc_status dce112_validate_guaranteed( 870 struct dc *dc, 871 struct dc_stream_state *stream, 872 struct dc_state *context) 873 { 874 enum dc_status result = DC_ERROR_UNEXPECTED; 875 876 context->streams[0] = stream; 877 dc_stream_retain(context->streams[0]); 878 context->stream_count++; 879 880 result = resource_map_pool_resources(dc, context, stream); 881 882 if (result == DC_OK) 883 result = resource_map_phy_clock_resources(dc, context, stream); 884 885 if (result == DC_OK) 886 result = build_mapped_resource(dc, context, stream); 887 888 if (result == DC_OK) { 889 validate_guaranteed_copy_streams( 890 context, dc->caps.max_streams); 891 result = resource_build_scaling_params_for_context(dc, context); 892 } 893 894 if (result == DC_OK) 895 if (!dce112_validate_bandwidth(dc, context)) 896 result = DC_FAIL_BANDWIDTH_VALIDATE; 897 898 return result; 899 } 900 901 enum dc_status dce112_validate_global( 902 struct dc *dc, 903 struct dc_state *context) 904 { 905 if (!dce112_validate_surface_sets(context)) 906 return DC_FAIL_SURFACE_VALIDATE; 907 908 return DC_OK; 909 } 910 911 static void dce112_destroy_resource_pool(struct resource_pool **pool) 912 { 913 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 914 915 destruct(dce110_pool); 916 kfree(dce110_pool); 917 *pool = NULL; 918 } 919 920 static const struct resource_funcs dce112_res_pool_funcs = { 921 .destroy = dce112_destroy_resource_pool, 922 .link_enc_create = dce112_link_encoder_create, 923 .validate_guaranteed = dce112_validate_guaranteed, 924 .validate_bandwidth = dce112_validate_bandwidth, 925 .validate_plane = dce100_validate_plane, 926 .add_stream_to_ctx = dce112_add_stream_to_ctx, 927 .validate_global = dce112_validate_global 928 }; 929 930 static void bw_calcs_data_update_from_pplib(struct dc *dc) 931 { 932 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 933 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 934 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; 935 struct dm_pp_clock_levels clks = {0}; 936 937 /*do system clock TODO PPLIB: after PPLIB implement, 938 * then remove old way 939 */ 940 if (!dm_pp_get_clock_levels_by_type_with_latency( 941 dc->ctx, 942 DM_PP_CLOCK_TYPE_ENGINE_CLK, 943 &eng_clks)) { 944 945 /* This is only for temporary */ 946 dm_pp_get_clock_levels_by_type( 947 dc->ctx, 948 DM_PP_CLOCK_TYPE_ENGINE_CLK, 949 &clks); 950 /* convert all the clock fro kHz to fix point mHz */ 951 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 952 clks.clocks_in_khz[clks.num_levels-1], 1000); 953 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 954 clks.clocks_in_khz[clks.num_levels/8], 1000); 955 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 956 clks.clocks_in_khz[clks.num_levels*2/8], 1000); 957 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 958 clks.clocks_in_khz[clks.num_levels*3/8], 1000); 959 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 960 clks.clocks_in_khz[clks.num_levels*4/8], 1000); 961 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 962 clks.clocks_in_khz[clks.num_levels*5/8], 1000); 963 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 964 clks.clocks_in_khz[clks.num_levels*6/8], 1000); 965 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 966 clks.clocks_in_khz[0], 1000); 967 968 /*do memory clock*/ 969 dm_pp_get_clock_levels_by_type( 970 dc->ctx, 971 DM_PP_CLOCK_TYPE_MEMORY_CLK, 972 &clks); 973 974 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 975 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000); 976 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 977 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER, 978 1000); 979 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 980 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER, 981 1000); 982 983 return; 984 } 985 986 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ 987 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 988 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); 989 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 990 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); 991 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 992 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); 993 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 994 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); 995 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 996 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); 997 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 998 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); 999 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1000 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); 1001 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1002 eng_clks.data[0].clocks_in_khz, 1000); 1003 1004 /*do memory clock*/ 1005 dm_pp_get_clock_levels_by_type_with_latency( 1006 dc->ctx, 1007 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1008 &mem_clks); 1009 1010 /* we don't need to call PPLIB for validation clock since they 1011 * also give us the highest sclk and highest mclk (UMA clock). 1012 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): 1013 * YCLK = UMACLK*m_memoryTypeMultiplier 1014 */ 1015 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1016 mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000); 1017 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1018 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1019 1000); 1020 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1021 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1022 1000); 1023 1024 /* Now notify PPLib/SMU about which Watermarks sets they should select 1025 * depending on DPM state they are in. And update BW MGR GFX Engine and 1026 * Memory clock member variables for Watermarks calculations for each 1027 * Watermark Set 1028 */ 1029 clk_ranges.num_wm_sets = 4; 1030 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; 1031 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = 1032 eng_clks.data[0].clocks_in_khz; 1033 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = 1034 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 1035 clk_ranges.wm_clk_ranges[0].wm_min_memg_clk_in_khz = 1036 mem_clks.data[0].clocks_in_khz; 1037 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = 1038 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 1039 1040 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; 1041 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = 1042 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 1043 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 1044 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; 1045 clk_ranges.wm_clk_ranges[1].wm_min_memg_clk_in_khz = 1046 mem_clks.data[0].clocks_in_khz; 1047 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = 1048 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 1049 1050 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; 1051 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = 1052 eng_clks.data[0].clocks_in_khz; 1053 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = 1054 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 1055 clk_ranges.wm_clk_ranges[2].wm_min_memg_clk_in_khz = 1056 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 1057 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 1058 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; 1059 1060 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; 1061 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = 1062 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 1063 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 1064 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; 1065 clk_ranges.wm_clk_ranges[3].wm_min_memg_clk_in_khz = 1066 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 1067 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 1068 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; 1069 1070 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 1071 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); 1072 } 1073 1074 const struct resource_caps *dce112_resource_cap( 1075 struct hw_asic_id *asic_id) 1076 { 1077 if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) || 1078 ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev)) 1079 return &polaris_11_resource_cap; 1080 else 1081 return &polaris_10_resource_cap; 1082 } 1083 1084 static bool construct( 1085 uint8_t num_virtual_links, 1086 struct dc *dc, 1087 struct dce110_resource_pool *pool) 1088 { 1089 unsigned int i; 1090 struct dc_context *ctx = dc->ctx; 1091 struct dm_pp_static_clock_info static_clk_info = {0}; 1092 1093 ctx->dc_bios->regs = &bios_regs; 1094 1095 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id); 1096 pool->base.funcs = &dce112_res_pool_funcs; 1097 1098 /************************************************* 1099 * Resource + asic cap harcoding * 1100 *************************************************/ 1101 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1102 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1103 dc->caps.max_downscale_ratio = 200; 1104 dc->caps.i2c_speed_in_khz = 100; 1105 dc->caps.max_cursor_size = 128; 1106 1107 /************************************************* 1108 * Create resources * 1109 *************************************************/ 1110 1111 pool->base.clock_sources[DCE112_CLK_SRC_PLL0] = 1112 dce112_clock_source_create( 1113 ctx, ctx->dc_bios, 1114 CLOCK_SOURCE_COMBO_PHY_PLL0, 1115 &clk_src_regs[0], false); 1116 pool->base.clock_sources[DCE112_CLK_SRC_PLL1] = 1117 dce112_clock_source_create( 1118 ctx, ctx->dc_bios, 1119 CLOCK_SOURCE_COMBO_PHY_PLL1, 1120 &clk_src_regs[1], false); 1121 pool->base.clock_sources[DCE112_CLK_SRC_PLL2] = 1122 dce112_clock_source_create( 1123 ctx, ctx->dc_bios, 1124 CLOCK_SOURCE_COMBO_PHY_PLL2, 1125 &clk_src_regs[2], false); 1126 pool->base.clock_sources[DCE112_CLK_SRC_PLL3] = 1127 dce112_clock_source_create( 1128 ctx, ctx->dc_bios, 1129 CLOCK_SOURCE_COMBO_PHY_PLL3, 1130 &clk_src_regs[3], false); 1131 pool->base.clock_sources[DCE112_CLK_SRC_PLL4] = 1132 dce112_clock_source_create( 1133 ctx, ctx->dc_bios, 1134 CLOCK_SOURCE_COMBO_PHY_PLL4, 1135 &clk_src_regs[4], false); 1136 pool->base.clock_sources[DCE112_CLK_SRC_PLL5] = 1137 dce112_clock_source_create( 1138 ctx, ctx->dc_bios, 1139 CLOCK_SOURCE_COMBO_PHY_PLL5, 1140 &clk_src_regs[5], false); 1141 pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL; 1142 1143 pool->base.dp_clock_source = dce112_clock_source_create( 1144 ctx, ctx->dc_bios, 1145 CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); 1146 1147 1148 for (i = 0; i < pool->base.clk_src_count; i++) { 1149 if (pool->base.clock_sources[i] == NULL) { 1150 dm_error("DC: failed to create clock sources!\n"); 1151 BREAK_TO_DEBUGGER(); 1152 goto res_create_fail; 1153 } 1154 } 1155 1156 pool->base.display_clock = dce112_disp_clk_create(ctx, 1157 &disp_clk_regs, 1158 &disp_clk_shift, 1159 &disp_clk_mask); 1160 if (pool->base.display_clock == NULL) { 1161 dm_error("DC: failed to create display clock!\n"); 1162 BREAK_TO_DEBUGGER(); 1163 goto res_create_fail; 1164 } 1165 1166 pool->base.dmcu = dce_dmcu_create(ctx, 1167 &dmcu_regs, 1168 &dmcu_shift, 1169 &dmcu_mask); 1170 if (pool->base.dmcu == NULL) { 1171 dm_error("DC: failed to create dmcu!\n"); 1172 BREAK_TO_DEBUGGER(); 1173 goto res_create_fail; 1174 } 1175 1176 pool->base.abm = dce_abm_create(ctx, 1177 &abm_regs, 1178 &abm_shift, 1179 &abm_mask); 1180 if (pool->base.abm == NULL) { 1181 dm_error("DC: failed to create abm!\n"); 1182 BREAK_TO_DEBUGGER(); 1183 goto res_create_fail; 1184 } 1185 1186 /* get static clock information for PPLIB or firmware, save 1187 * max_clock_state 1188 */ 1189 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 1190 pool->base.display_clock->max_clks_state = 1191 static_clk_info.max_clocks_state; 1192 1193 { 1194 struct irq_service_init_data init_data; 1195 init_data.ctx = dc->ctx; 1196 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 1197 if (!pool->base.irqs) 1198 goto res_create_fail; 1199 } 1200 1201 for (i = 0; i < pool->base.pipe_count; i++) { 1202 pool->base.timing_generators[i] = 1203 dce112_timing_generator_create( 1204 ctx, 1205 i, 1206 &dce112_tg_offsets[i]); 1207 if (pool->base.timing_generators[i] == NULL) { 1208 BREAK_TO_DEBUGGER(); 1209 dm_error("DC: failed to create tg!\n"); 1210 goto res_create_fail; 1211 } 1212 1213 pool->base.mis[i] = dce112_mem_input_create(ctx, i); 1214 if (pool->base.mis[i] == NULL) { 1215 BREAK_TO_DEBUGGER(); 1216 dm_error( 1217 "DC: failed to create memory input!\n"); 1218 goto res_create_fail; 1219 } 1220 1221 pool->base.ipps[i] = dce112_ipp_create(ctx, i); 1222 if (pool->base.ipps[i] == NULL) { 1223 BREAK_TO_DEBUGGER(); 1224 dm_error( 1225 "DC:failed to create input pixel processor!\n"); 1226 goto res_create_fail; 1227 } 1228 1229 pool->base.transforms[i] = dce112_transform_create(ctx, i); 1230 if (pool->base.transforms[i] == NULL) { 1231 BREAK_TO_DEBUGGER(); 1232 dm_error( 1233 "DC: failed to create transform!\n"); 1234 goto res_create_fail; 1235 } 1236 1237 pool->base.opps[i] = dce112_opp_create( 1238 ctx, 1239 i); 1240 if (pool->base.opps[i] == NULL) { 1241 BREAK_TO_DEBUGGER(); 1242 dm_error( 1243 "DC:failed to create output pixel processor!\n"); 1244 goto res_create_fail; 1245 } 1246 } 1247 1248 if (!resource_construct(num_virtual_links, dc, &pool->base, 1249 &res_create_funcs)) 1250 goto res_create_fail; 1251 1252 dc->caps.max_planes = pool->base.pipe_count; 1253 1254 /* Create hardware sequencer */ 1255 dce112_hw_sequencer_construct(dc); 1256 1257 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1258 1259 bw_calcs_data_update_from_pplib(dc); 1260 1261 return true; 1262 1263 res_create_fail: 1264 destruct(pool); 1265 return false; 1266 } 1267 1268 struct resource_pool *dce112_create_resource_pool( 1269 uint8_t num_virtual_links, 1270 struct dc *dc) 1271 { 1272 struct dce110_resource_pool *pool = 1273 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1274 1275 if (!pool) 1276 return NULL; 1277 1278 if (construct(num_virtual_links, dc, pool)) 1279 return &pool->base; 1280 1281 BREAK_TO_DEBUGGER(); 1282 return NULL; 1283 } 1284