1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 30 #include "link_encoder.h" 31 #include "stream_encoder.h" 32 33 #include "resource.h" 34 #include "include/irq_service_interface.h" 35 #include "dce110/dce110_resource.h" 36 #include "dce110/dce110_timing_generator.h" 37 38 #include "irq/dce110/irq_service_dce110.h" 39 #include "dce/dce_mem_input.h" 40 #include "dce/dce_transform.h" 41 #include "dce/dce_link_encoder.h" 42 #include "dce/dce_stream_encoder.h" 43 #include "dce/dce_audio.h" 44 #include "dce/dce_opp.h" 45 #include "dce/dce_ipp.h" 46 #include "dce/dce_clock_source.h" 47 48 #include "dce/dce_hwseq.h" 49 #include "dce112/dce112_hw_sequencer.h" 50 #include "dce/dce_abm.h" 51 #include "dce/dce_dmcu.h" 52 #include "dce/dce_aux.h" 53 #include "dce/dce_i2c.h" 54 55 #include "reg_helper.h" 56 57 #include "dce/dce_11_2_d.h" 58 #include "dce/dce_11_2_sh_mask.h" 59 60 #include "dce100/dce100_resource.h" 61 #define DC_LOGGER \ 62 dc->ctx->logger 63 64 #ifndef mmDP_DPHY_INTERNAL_CTRL 65 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 66 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 67 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 68 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 69 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 70 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 71 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 72 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 73 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 74 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 75 #endif 76 77 #ifndef mmBIOS_SCRATCH_2 78 #define mmBIOS_SCRATCH_2 0x05CB 79 #define mmBIOS_SCRATCH_3 0x05CC 80 #define mmBIOS_SCRATCH_6 0x05CF 81 #endif 82 83 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 84 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 85 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 86 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 87 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 88 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 89 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 90 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 91 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 92 #endif 93 94 #ifndef mmDP_DPHY_FAST_TRAINING 95 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 96 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 97 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 98 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 99 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 100 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 101 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 102 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 103 #endif 104 105 enum dce112_clk_src_array_id { 106 DCE112_CLK_SRC_PLL0, 107 DCE112_CLK_SRC_PLL1, 108 DCE112_CLK_SRC_PLL2, 109 DCE112_CLK_SRC_PLL3, 110 DCE112_CLK_SRC_PLL4, 111 DCE112_CLK_SRC_PLL5, 112 113 DCE112_CLK_SRC_TOTAL 114 }; 115 116 static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = { 117 { 118 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 119 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 120 }, 121 { 122 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 123 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 124 }, 125 { 126 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 127 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 128 }, 129 { 130 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 131 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 132 }, 133 { 134 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 135 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 136 }, 137 { 138 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 139 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 140 } 141 }; 142 143 /* set register offset */ 144 #define SR(reg_name)\ 145 .reg_name = mm ## reg_name 146 147 /* set register offset with instance */ 148 #define SRI(reg_name, block, id)\ 149 .reg_name = mm ## block ## id ## _ ## reg_name 150 151 static const struct dce_dmcu_registers dmcu_regs = { 152 DMCU_DCE110_COMMON_REG_LIST() 153 }; 154 155 static const struct dce_dmcu_shift dmcu_shift = { 156 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 157 }; 158 159 static const struct dce_dmcu_mask dmcu_mask = { 160 DMCU_MASK_SH_LIST_DCE110(_MASK) 161 }; 162 163 static const struct dce_abm_registers abm_regs = { 164 ABM_DCE110_COMMON_REG_LIST() 165 }; 166 167 static const struct dce_abm_shift abm_shift = { 168 ABM_MASK_SH_LIST_DCE110(__SHIFT) 169 }; 170 171 static const struct dce_abm_mask abm_mask = { 172 ABM_MASK_SH_LIST_DCE110(_MASK) 173 }; 174 175 static const struct dce110_aux_registers_shift aux_shift = { 176 DCE_AUX_MASK_SH_LIST(__SHIFT) 177 }; 178 179 static const struct dce110_aux_registers_mask aux_mask = { 180 DCE_AUX_MASK_SH_LIST(_MASK) 181 }; 182 183 #define ipp_regs(id)\ 184 [id] = {\ 185 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 186 } 187 188 static const struct dce_ipp_registers ipp_regs[] = { 189 ipp_regs(0), 190 ipp_regs(1), 191 ipp_regs(2), 192 ipp_regs(3), 193 ipp_regs(4), 194 ipp_regs(5) 195 }; 196 197 static const struct dce_ipp_shift ipp_shift = { 198 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 199 }; 200 201 static const struct dce_ipp_mask ipp_mask = { 202 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 203 }; 204 205 #define transform_regs(id)\ 206 [id] = {\ 207 XFM_COMMON_REG_LIST_DCE110(id)\ 208 } 209 210 static const struct dce_transform_registers xfm_regs[] = { 211 transform_regs(0), 212 transform_regs(1), 213 transform_regs(2), 214 transform_regs(3), 215 transform_regs(4), 216 transform_regs(5) 217 }; 218 219 static const struct dce_transform_shift xfm_shift = { 220 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 221 }; 222 223 static const struct dce_transform_mask xfm_mask = { 224 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 225 }; 226 227 #define aux_regs(id)\ 228 [id] = {\ 229 AUX_REG_LIST(id)\ 230 } 231 232 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 233 aux_regs(0), 234 aux_regs(1), 235 aux_regs(2), 236 aux_regs(3), 237 aux_regs(4), 238 aux_regs(5) 239 }; 240 241 #define hpd_regs(id)\ 242 [id] = {\ 243 HPD_REG_LIST(id)\ 244 } 245 246 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 247 hpd_regs(0), 248 hpd_regs(1), 249 hpd_regs(2), 250 hpd_regs(3), 251 hpd_regs(4), 252 hpd_regs(5) 253 }; 254 255 #define link_regs(id)\ 256 [id] = {\ 257 LE_DCE110_REG_LIST(id)\ 258 } 259 260 static const struct dce110_link_enc_registers link_enc_regs[] = { 261 link_regs(0), 262 link_regs(1), 263 link_regs(2), 264 link_regs(3), 265 link_regs(4), 266 link_regs(5), 267 link_regs(6), 268 }; 269 270 #define stream_enc_regs(id)\ 271 [id] = {\ 272 SE_COMMON_REG_LIST(id),\ 273 .TMDS_CNTL = 0,\ 274 } 275 276 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 277 stream_enc_regs(0), 278 stream_enc_regs(1), 279 stream_enc_regs(2), 280 stream_enc_regs(3), 281 stream_enc_regs(4), 282 stream_enc_regs(5) 283 }; 284 285 static const struct dce_stream_encoder_shift se_shift = { 286 SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT) 287 }; 288 289 static const struct dce_stream_encoder_mask se_mask = { 290 SE_COMMON_MASK_SH_LIST_DCE112(_MASK) 291 }; 292 293 #define opp_regs(id)\ 294 [id] = {\ 295 OPP_DCE_112_REG_LIST(id),\ 296 } 297 298 static const struct dce_opp_registers opp_regs[] = { 299 opp_regs(0), 300 opp_regs(1), 301 opp_regs(2), 302 opp_regs(3), 303 opp_regs(4), 304 opp_regs(5) 305 }; 306 307 static const struct dce_opp_shift opp_shift = { 308 OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 309 }; 310 311 static const struct dce_opp_mask opp_mask = { 312 OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK) 313 }; 314 315 #define aux_engine_regs(id)\ 316 [id] = {\ 317 AUX_COMMON_REG_LIST(id), \ 318 .AUX_RESET_MASK = 0 \ 319 } 320 321 static const struct dce110_aux_registers aux_engine_regs[] = { 322 aux_engine_regs(0), 323 aux_engine_regs(1), 324 aux_engine_regs(2), 325 aux_engine_regs(3), 326 aux_engine_regs(4), 327 aux_engine_regs(5) 328 }; 329 330 #define audio_regs(id)\ 331 [id] = {\ 332 AUD_COMMON_REG_LIST(id)\ 333 } 334 335 static const struct dce_audio_registers audio_regs[] = { 336 audio_regs(0), 337 audio_regs(1), 338 audio_regs(2), 339 audio_regs(3), 340 audio_regs(4), 341 audio_regs(5) 342 }; 343 344 static const struct dce_audio_shift audio_shift = { 345 AUD_COMMON_MASK_SH_LIST(__SHIFT) 346 }; 347 348 static const struct dce_audio_mask audio_mask = { 349 AUD_COMMON_MASK_SH_LIST(_MASK) 350 }; 351 352 #define clk_src_regs(index, id)\ 353 [index] = {\ 354 CS_COMMON_REG_LIST_DCE_112(id),\ 355 } 356 357 static const struct dce110_clk_src_regs clk_src_regs[] = { 358 clk_src_regs(0, A), 359 clk_src_regs(1, B), 360 clk_src_regs(2, C), 361 clk_src_regs(3, D), 362 clk_src_regs(4, E), 363 clk_src_regs(5, F) 364 }; 365 366 static const struct dce110_clk_src_shift cs_shift = { 367 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 368 }; 369 370 static const struct dce110_clk_src_mask cs_mask = { 371 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) 372 }; 373 374 static const struct bios_registers bios_regs = { 375 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 376 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 377 }; 378 379 static const struct resource_caps polaris_10_resource_cap = { 380 .num_timing_generator = 6, 381 .num_audio = 6, 382 .num_stream_encoder = 6, 383 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */ 384 .num_ddc = 6, 385 }; 386 387 static const struct resource_caps polaris_11_resource_cap = { 388 .num_timing_generator = 5, 389 .num_audio = 5, 390 .num_stream_encoder = 5, 391 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */ 392 .num_ddc = 5, 393 }; 394 395 static const struct dc_plane_cap plane_cap = { 396 .type = DC_PLANE_TYPE_DCE_RGB, 397 398 .pixel_format_support = { 399 .argb8888 = true, 400 .nv12 = false, 401 .fp16 = false 402 }, 403 404 .max_upscale_factor = { 405 .argb8888 = 16000, 406 .nv12 = 1, 407 .fp16 = 1 408 }, 409 410 .max_downscale_factor = { 411 .argb8888 = 250, 412 .nv12 = 1, 413 .fp16 = 1 414 } 415 }; 416 417 #define CTX ctx 418 #define REG(reg) mm ## reg 419 420 #ifndef mmCC_DC_HDMI_STRAPS 421 #define mmCC_DC_HDMI_STRAPS 0x4819 422 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 423 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 424 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 425 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 426 #endif 427 428 static void read_dce_straps( 429 struct dc_context *ctx, 430 struct resource_straps *straps) 431 { 432 REG_GET_2(CC_DC_HDMI_STRAPS, 433 HDMI_DISABLE, &straps->hdmi_disable, 434 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 435 436 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 437 } 438 439 static struct audio *create_audio( 440 struct dc_context *ctx, unsigned int inst) 441 { 442 return dce_audio_create(ctx, inst, 443 &audio_regs[inst], &audio_shift, &audio_mask); 444 } 445 446 447 static struct timing_generator *dce112_timing_generator_create( 448 struct dc_context *ctx, 449 uint32_t instance, 450 const struct dce110_timing_generator_offsets *offsets) 451 { 452 struct dce110_timing_generator *tg110 = 453 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 454 455 if (!tg110) 456 return NULL; 457 458 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 459 return &tg110->base; 460 } 461 462 static struct stream_encoder *dce112_stream_encoder_create( 463 enum engine_id eng_id, 464 struct dc_context *ctx) 465 { 466 struct dce110_stream_encoder *enc110 = 467 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 468 469 if (!enc110) 470 return NULL; 471 472 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 473 &stream_enc_regs[eng_id], 474 &se_shift, &se_mask); 475 return &enc110->base; 476 } 477 478 #define SRII(reg_name, block, id)\ 479 .reg_name[id] = mm ## block ## id ## _ ## reg_name 480 481 static const struct dce_hwseq_registers hwseq_reg = { 482 HWSEQ_DCE112_REG_LIST() 483 }; 484 485 static const struct dce_hwseq_shift hwseq_shift = { 486 HWSEQ_DCE112_MASK_SH_LIST(__SHIFT) 487 }; 488 489 static const struct dce_hwseq_mask hwseq_mask = { 490 HWSEQ_DCE112_MASK_SH_LIST(_MASK) 491 }; 492 493 static struct dce_hwseq *dce112_hwseq_create( 494 struct dc_context *ctx) 495 { 496 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 497 498 if (hws) { 499 hws->ctx = ctx; 500 hws->regs = &hwseq_reg; 501 hws->shifts = &hwseq_shift; 502 hws->masks = &hwseq_mask; 503 } 504 return hws; 505 } 506 507 static const struct resource_create_funcs res_create_funcs = { 508 .read_dce_straps = read_dce_straps, 509 .create_audio = create_audio, 510 .create_stream_encoder = dce112_stream_encoder_create, 511 .create_hwseq = dce112_hwseq_create, 512 }; 513 514 #define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) } 515 static const struct dce_mem_input_registers mi_regs[] = { 516 mi_inst_regs(0), 517 mi_inst_regs(1), 518 mi_inst_regs(2), 519 mi_inst_regs(3), 520 mi_inst_regs(4), 521 mi_inst_regs(5), 522 }; 523 524 static const struct dce_mem_input_shift mi_shifts = { 525 MI_DCE11_2_MASK_SH_LIST(__SHIFT) 526 }; 527 528 static const struct dce_mem_input_mask mi_masks = { 529 MI_DCE11_2_MASK_SH_LIST(_MASK) 530 }; 531 532 static struct mem_input *dce112_mem_input_create( 533 struct dc_context *ctx, 534 uint32_t inst) 535 { 536 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 537 GFP_KERNEL); 538 539 if (!dce_mi) { 540 BREAK_TO_DEBUGGER(); 541 return NULL; 542 } 543 544 dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 545 return &dce_mi->base; 546 } 547 548 static void dce112_transform_destroy(struct transform **xfm) 549 { 550 kfree(TO_DCE_TRANSFORM(*xfm)); 551 *xfm = NULL; 552 } 553 554 static struct transform *dce112_transform_create( 555 struct dc_context *ctx, 556 uint32_t inst) 557 { 558 struct dce_transform *transform = 559 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 560 561 if (!transform) 562 return NULL; 563 564 dce_transform_construct(transform, ctx, inst, 565 &xfm_regs[inst], &xfm_shift, &xfm_mask); 566 transform->lb_memory_size = 0x1404; /*5124*/ 567 return &transform->base; 568 } 569 570 static const struct encoder_feature_support link_enc_feature = { 571 .max_hdmi_deep_color = COLOR_DEPTH_121212, 572 .max_hdmi_pixel_clock = 600000, 573 .hdmi_ycbcr420_supported = true, 574 .dp_ycbcr420_supported = false, 575 .flags.bits.IS_HBR2_CAPABLE = true, 576 .flags.bits.IS_HBR3_CAPABLE = true, 577 .flags.bits.IS_TPS3_CAPABLE = true, 578 .flags.bits.IS_TPS4_CAPABLE = true 579 }; 580 581 struct link_encoder *dce112_link_encoder_create( 582 const struct encoder_init_data *enc_init_data) 583 { 584 struct dce110_link_encoder *enc110 = 585 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 586 587 if (!enc110) 588 return NULL; 589 590 dce110_link_encoder_construct(enc110, 591 enc_init_data, 592 &link_enc_feature, 593 &link_enc_regs[enc_init_data->transmitter], 594 &link_enc_aux_regs[enc_init_data->channel - 1], 595 &link_enc_hpd_regs[enc_init_data->hpd_source]); 596 return &enc110->base; 597 } 598 599 static struct input_pixel_processor *dce112_ipp_create( 600 struct dc_context *ctx, uint32_t inst) 601 { 602 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 603 604 if (!ipp) { 605 BREAK_TO_DEBUGGER(); 606 return NULL; 607 } 608 609 dce_ipp_construct(ipp, ctx, inst, 610 &ipp_regs[inst], &ipp_shift, &ipp_mask); 611 return &ipp->base; 612 } 613 614 struct output_pixel_processor *dce112_opp_create( 615 struct dc_context *ctx, 616 uint32_t inst) 617 { 618 struct dce110_opp *opp = 619 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 620 621 if (!opp) 622 return NULL; 623 624 dce110_opp_construct(opp, 625 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 626 return &opp->base; 627 } 628 629 struct dce_aux *dce112_aux_engine_create( 630 struct dc_context *ctx, 631 uint32_t inst) 632 { 633 struct aux_engine_dce110 *aux_engine = 634 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 635 636 if (!aux_engine) 637 return NULL; 638 639 dce110_aux_engine_construct(aux_engine, ctx, inst, 640 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 641 &aux_engine_regs[inst], 642 &aux_mask, 643 &aux_shift, 644 ctx->dc->caps.extended_aux_timeout_support); 645 646 return &aux_engine->base; 647 } 648 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 649 650 static const struct dce_i2c_registers i2c_hw_regs[] = { 651 i2c_inst_regs(1), 652 i2c_inst_regs(2), 653 i2c_inst_regs(3), 654 i2c_inst_regs(4), 655 i2c_inst_regs(5), 656 i2c_inst_regs(6), 657 }; 658 659 static const struct dce_i2c_shift i2c_shifts = { 660 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 661 }; 662 663 static const struct dce_i2c_mask i2c_masks = { 664 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 665 }; 666 667 struct dce_i2c_hw *dce112_i2c_hw_create( 668 struct dc_context *ctx, 669 uint32_t inst) 670 { 671 struct dce_i2c_hw *dce_i2c_hw = 672 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 673 674 if (!dce_i2c_hw) 675 return NULL; 676 677 dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst, 678 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 679 680 return dce_i2c_hw; 681 } 682 struct clock_source *dce112_clock_source_create( 683 struct dc_context *ctx, 684 struct dc_bios *bios, 685 enum clock_source_id id, 686 const struct dce110_clk_src_regs *regs, 687 bool dp_clk_src) 688 { 689 struct dce110_clk_src *clk_src = 690 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 691 692 if (!clk_src) 693 return NULL; 694 695 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 696 regs, &cs_shift, &cs_mask)) { 697 clk_src->base.dp_clk_src = dp_clk_src; 698 return &clk_src->base; 699 } 700 701 kfree(clk_src); 702 BREAK_TO_DEBUGGER(); 703 return NULL; 704 } 705 706 void dce112_clock_source_destroy(struct clock_source **clk_src) 707 { 708 kfree(TO_DCE110_CLK_SRC(*clk_src)); 709 *clk_src = NULL; 710 } 711 712 static void destruct(struct dce110_resource_pool *pool) 713 { 714 unsigned int i; 715 716 for (i = 0; i < pool->base.pipe_count; i++) { 717 if (pool->base.opps[i] != NULL) 718 dce110_opp_destroy(&pool->base.opps[i]); 719 720 if (pool->base.transforms[i] != NULL) 721 dce112_transform_destroy(&pool->base.transforms[i]); 722 723 if (pool->base.ipps[i] != NULL) 724 dce_ipp_destroy(&pool->base.ipps[i]); 725 726 if (pool->base.mis[i] != NULL) { 727 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 728 pool->base.mis[i] = NULL; 729 } 730 731 if (pool->base.timing_generators[i] != NULL) { 732 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 733 pool->base.timing_generators[i] = NULL; 734 } 735 } 736 737 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 738 if (pool->base.engines[i] != NULL) 739 dce110_engine_destroy(&pool->base.engines[i]); 740 if (pool->base.hw_i2cs[i] != NULL) { 741 kfree(pool->base.hw_i2cs[i]); 742 pool->base.hw_i2cs[i] = NULL; 743 } 744 if (pool->base.sw_i2cs[i] != NULL) { 745 kfree(pool->base.sw_i2cs[i]); 746 pool->base.sw_i2cs[i] = NULL; 747 } 748 } 749 750 for (i = 0; i < pool->base.stream_enc_count; i++) { 751 if (pool->base.stream_enc[i] != NULL) 752 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 753 } 754 755 for (i = 0; i < pool->base.clk_src_count; i++) { 756 if (pool->base.clock_sources[i] != NULL) { 757 dce112_clock_source_destroy(&pool->base.clock_sources[i]); 758 } 759 } 760 761 if (pool->base.dp_clock_source != NULL) 762 dce112_clock_source_destroy(&pool->base.dp_clock_source); 763 764 for (i = 0; i < pool->base.audio_count; i++) { 765 if (pool->base.audios[i] != NULL) { 766 dce_aud_destroy(&pool->base.audios[i]); 767 } 768 } 769 770 if (pool->base.abm != NULL) 771 dce_abm_destroy(&pool->base.abm); 772 773 if (pool->base.dmcu != NULL) 774 dce_dmcu_destroy(&pool->base.dmcu); 775 776 if (pool->base.irqs != NULL) { 777 dal_irq_service_destroy(&pool->base.irqs); 778 } 779 } 780 781 static struct clock_source *find_matching_pll( 782 struct resource_context *res_ctx, 783 const struct resource_pool *pool, 784 const struct dc_stream_state *const stream) 785 { 786 switch (stream->link->link_enc->transmitter) { 787 case TRANSMITTER_UNIPHY_A: 788 return pool->clock_sources[DCE112_CLK_SRC_PLL0]; 789 case TRANSMITTER_UNIPHY_B: 790 return pool->clock_sources[DCE112_CLK_SRC_PLL1]; 791 case TRANSMITTER_UNIPHY_C: 792 return pool->clock_sources[DCE112_CLK_SRC_PLL2]; 793 case TRANSMITTER_UNIPHY_D: 794 return pool->clock_sources[DCE112_CLK_SRC_PLL3]; 795 case TRANSMITTER_UNIPHY_E: 796 return pool->clock_sources[DCE112_CLK_SRC_PLL4]; 797 case TRANSMITTER_UNIPHY_F: 798 return pool->clock_sources[DCE112_CLK_SRC_PLL5]; 799 default: 800 return NULL; 801 }; 802 803 return 0; 804 } 805 806 static enum dc_status build_mapped_resource( 807 const struct dc *dc, 808 struct dc_state *context, 809 struct dc_stream_state *stream) 810 { 811 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 812 813 if (!pipe_ctx) 814 return DC_ERROR_UNEXPECTED; 815 816 dce110_resource_build_pipe_hw_param(pipe_ctx); 817 818 resource_build_info_frame(pipe_ctx); 819 820 return DC_OK; 821 } 822 823 bool dce112_validate_bandwidth( 824 struct dc *dc, 825 struct dc_state *context, 826 bool fast_validate) 827 { 828 bool result = false; 829 830 DC_LOG_BANDWIDTH_CALCS( 831 "%s: start", 832 __func__); 833 834 if (bw_calcs( 835 dc->ctx, 836 dc->bw_dceip, 837 dc->bw_vbios, 838 context->res_ctx.pipe_ctx, 839 dc->res_pool->pipe_count, 840 &context->bw_ctx.bw.dce)) 841 result = true; 842 843 if (!result) 844 DC_LOG_BANDWIDTH_VALIDATION( 845 "%s: Bandwidth validation failed!", 846 __func__); 847 848 if (memcmp(&dc->current_state->bw_ctx.bw.dce, 849 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { 850 851 DC_LOG_BANDWIDTH_CALCS( 852 "%s: finish,\n" 853 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 854 "stutMark_b: %d stutMark_a: %d\n" 855 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 856 "stutMark_b: %d stutMark_a: %d\n" 857 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 858 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n" 859 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" 860 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n" 861 , 862 __func__, 863 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark, 864 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark, 865 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, 866 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, 867 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark, 868 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark, 869 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark, 870 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark, 871 context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark, 872 context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark, 873 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark, 874 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark, 875 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark, 876 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark, 877 context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark, 878 context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark, 879 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark, 880 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark, 881 context->bw_ctx.bw.dce.stutter_mode_enable, 882 context->bw_ctx.bw.dce.cpuc_state_change_enable, 883 context->bw_ctx.bw.dce.cpup_state_change_enable, 884 context->bw_ctx.bw.dce.nbp_state_change_enable, 885 context->bw_ctx.bw.dce.all_displays_in_sync, 886 context->bw_ctx.bw.dce.dispclk_khz, 887 context->bw_ctx.bw.dce.sclk_khz, 888 context->bw_ctx.bw.dce.sclk_deep_sleep_khz, 889 context->bw_ctx.bw.dce.yclk_khz, 890 context->bw_ctx.bw.dce.blackout_recovery_time_us); 891 } 892 return result; 893 } 894 895 enum dc_status resource_map_phy_clock_resources( 896 const struct dc *dc, 897 struct dc_state *context, 898 struct dc_stream_state *stream) 899 { 900 901 /* acquire new resources */ 902 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( 903 &context->res_ctx, stream); 904 905 if (!pipe_ctx) 906 return DC_ERROR_UNEXPECTED; 907 908 if (dc_is_dp_signal(pipe_ctx->stream->signal) 909 || dc_is_virtual_signal(pipe_ctx->stream->signal)) 910 pipe_ctx->clock_source = 911 dc->res_pool->dp_clock_source; 912 else 913 pipe_ctx->clock_source = find_matching_pll( 914 &context->res_ctx, dc->res_pool, 915 stream); 916 917 if (pipe_ctx->clock_source == NULL) 918 return DC_NO_CLOCK_SOURCE_RESOURCE; 919 920 resource_reference_clock_source( 921 &context->res_ctx, 922 dc->res_pool, 923 pipe_ctx->clock_source); 924 925 return DC_OK; 926 } 927 928 static bool dce112_validate_surface_sets( 929 struct dc_state *context) 930 { 931 int i; 932 933 for (i = 0; i < context->stream_count; i++) { 934 if (context->stream_status[i].plane_count == 0) 935 continue; 936 937 if (context->stream_status[i].plane_count > 1) 938 return false; 939 940 if (context->stream_status[i].plane_states[0]->format 941 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 942 return false; 943 } 944 945 return true; 946 } 947 948 enum dc_status dce112_add_stream_to_ctx( 949 struct dc *dc, 950 struct dc_state *new_ctx, 951 struct dc_stream_state *dc_stream) 952 { 953 enum dc_status result = DC_ERROR_UNEXPECTED; 954 955 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 956 957 if (result == DC_OK) 958 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 959 960 961 if (result == DC_OK) 962 result = build_mapped_resource(dc, new_ctx, dc_stream); 963 964 return result; 965 } 966 967 enum dc_status dce112_validate_global( 968 struct dc *dc, 969 struct dc_state *context) 970 { 971 if (!dce112_validate_surface_sets(context)) 972 return DC_FAIL_SURFACE_VALIDATE; 973 974 return DC_OK; 975 } 976 977 static void dce112_destroy_resource_pool(struct resource_pool **pool) 978 { 979 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 980 981 destruct(dce110_pool); 982 kfree(dce110_pool); 983 *pool = NULL; 984 } 985 986 static const struct resource_funcs dce112_res_pool_funcs = { 987 .destroy = dce112_destroy_resource_pool, 988 .link_enc_create = dce112_link_encoder_create, 989 .validate_bandwidth = dce112_validate_bandwidth, 990 .validate_plane = dce100_validate_plane, 991 .add_stream_to_ctx = dce112_add_stream_to_ctx, 992 .validate_global = dce112_validate_global, 993 .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link 994 }; 995 996 static void bw_calcs_data_update_from_pplib(struct dc *dc) 997 { 998 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 999 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 1000 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; 1001 struct dm_pp_clock_levels clks = {0}; 1002 int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ; 1003 1004 if (dc->bw_vbios && dc->bw_vbios->memory_type == bw_def_hbm) 1005 memory_type_multiplier = MEMORY_TYPE_HBM; 1006 1007 /*do system clock TODO PPLIB: after PPLIB implement, 1008 * then remove old way 1009 */ 1010 if (!dm_pp_get_clock_levels_by_type_with_latency( 1011 dc->ctx, 1012 DM_PP_CLOCK_TYPE_ENGINE_CLK, 1013 &eng_clks)) { 1014 1015 /* This is only for temporary */ 1016 dm_pp_get_clock_levels_by_type( 1017 dc->ctx, 1018 DM_PP_CLOCK_TYPE_ENGINE_CLK, 1019 &clks); 1020 /* convert all the clock fro kHz to fix point mHz */ 1021 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 1022 clks.clocks_in_khz[clks.num_levels-1], 1000); 1023 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 1024 clks.clocks_in_khz[clks.num_levels/8], 1000); 1025 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 1026 clks.clocks_in_khz[clks.num_levels*2/8], 1000); 1027 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 1028 clks.clocks_in_khz[clks.num_levels*3/8], 1000); 1029 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 1030 clks.clocks_in_khz[clks.num_levels*4/8], 1000); 1031 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 1032 clks.clocks_in_khz[clks.num_levels*5/8], 1000); 1033 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1034 clks.clocks_in_khz[clks.num_levels*6/8], 1000); 1035 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1036 clks.clocks_in_khz[0], 1000); 1037 1038 /*do memory clock*/ 1039 dm_pp_get_clock_levels_by_type( 1040 dc->ctx, 1041 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1042 &clks); 1043 1044 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1045 clks.clocks_in_khz[0] * memory_type_multiplier, 1000); 1046 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1047 clks.clocks_in_khz[clks.num_levels>>1] * memory_type_multiplier, 1048 1000); 1049 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1050 clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier, 1051 1000); 1052 1053 return; 1054 } 1055 1056 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ 1057 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 1058 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); 1059 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 1060 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); 1061 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 1062 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); 1063 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 1064 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); 1065 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 1066 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); 1067 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 1068 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); 1069 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1070 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); 1071 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1072 eng_clks.data[0].clocks_in_khz, 1000); 1073 1074 /*do memory clock*/ 1075 dm_pp_get_clock_levels_by_type_with_latency( 1076 dc->ctx, 1077 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1078 &mem_clks); 1079 1080 /* we don't need to call PPLIB for validation clock since they 1081 * also give us the highest sclk and highest mclk (UMA clock). 1082 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): 1083 * YCLK = UMACLK*m_memoryTypeMultiplier 1084 */ 1085 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1086 mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000); 1087 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1088 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier, 1089 1000); 1090 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1091 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier, 1092 1000); 1093 1094 /* Now notify PPLib/SMU about which Watermarks sets they should select 1095 * depending on DPM state they are in. And update BW MGR GFX Engine and 1096 * Memory clock member variables for Watermarks calculations for each 1097 * Watermark Set 1098 */ 1099 clk_ranges.num_wm_sets = 4; 1100 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; 1101 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = 1102 eng_clks.data[0].clocks_in_khz; 1103 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = 1104 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 1105 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz = 1106 mem_clks.data[0].clocks_in_khz; 1107 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = 1108 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 1109 1110 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; 1111 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = 1112 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 1113 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 1114 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; 1115 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz = 1116 mem_clks.data[0].clocks_in_khz; 1117 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = 1118 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 1119 1120 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; 1121 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = 1122 eng_clks.data[0].clocks_in_khz; 1123 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = 1124 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 1125 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz = 1126 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 1127 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 1128 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; 1129 1130 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; 1131 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = 1132 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 1133 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 1134 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; 1135 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz = 1136 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 1137 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 1138 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; 1139 1140 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 1141 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); 1142 } 1143 1144 const struct resource_caps *dce112_resource_cap( 1145 struct hw_asic_id *asic_id) 1146 { 1147 if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) || 1148 ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev)) 1149 return &polaris_11_resource_cap; 1150 else 1151 return &polaris_10_resource_cap; 1152 } 1153 1154 static bool construct( 1155 uint8_t num_virtual_links, 1156 struct dc *dc, 1157 struct dce110_resource_pool *pool) 1158 { 1159 unsigned int i; 1160 struct dc_context *ctx = dc->ctx; 1161 1162 ctx->dc_bios->regs = &bios_regs; 1163 1164 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id); 1165 pool->base.funcs = &dce112_res_pool_funcs; 1166 1167 /************************************************* 1168 * Resource + asic cap harcoding * 1169 *************************************************/ 1170 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1171 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1172 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1173 dc->caps.max_downscale_ratio = 200; 1174 dc->caps.i2c_speed_in_khz = 100; 1175 dc->caps.max_cursor_size = 128; 1176 dc->caps.dual_link_dvi = true; 1177 dc->caps.extended_aux_timeout_support = false; 1178 1179 /************************************************* 1180 * Create resources * 1181 *************************************************/ 1182 1183 pool->base.clock_sources[DCE112_CLK_SRC_PLL0] = 1184 dce112_clock_source_create( 1185 ctx, ctx->dc_bios, 1186 CLOCK_SOURCE_COMBO_PHY_PLL0, 1187 &clk_src_regs[0], false); 1188 pool->base.clock_sources[DCE112_CLK_SRC_PLL1] = 1189 dce112_clock_source_create( 1190 ctx, ctx->dc_bios, 1191 CLOCK_SOURCE_COMBO_PHY_PLL1, 1192 &clk_src_regs[1], false); 1193 pool->base.clock_sources[DCE112_CLK_SRC_PLL2] = 1194 dce112_clock_source_create( 1195 ctx, ctx->dc_bios, 1196 CLOCK_SOURCE_COMBO_PHY_PLL2, 1197 &clk_src_regs[2], false); 1198 pool->base.clock_sources[DCE112_CLK_SRC_PLL3] = 1199 dce112_clock_source_create( 1200 ctx, ctx->dc_bios, 1201 CLOCK_SOURCE_COMBO_PHY_PLL3, 1202 &clk_src_regs[3], false); 1203 pool->base.clock_sources[DCE112_CLK_SRC_PLL4] = 1204 dce112_clock_source_create( 1205 ctx, ctx->dc_bios, 1206 CLOCK_SOURCE_COMBO_PHY_PLL4, 1207 &clk_src_regs[4], false); 1208 pool->base.clock_sources[DCE112_CLK_SRC_PLL5] = 1209 dce112_clock_source_create( 1210 ctx, ctx->dc_bios, 1211 CLOCK_SOURCE_COMBO_PHY_PLL5, 1212 &clk_src_regs[5], false); 1213 pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL; 1214 1215 pool->base.dp_clock_source = dce112_clock_source_create( 1216 ctx, ctx->dc_bios, 1217 CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); 1218 1219 1220 for (i = 0; i < pool->base.clk_src_count; i++) { 1221 if (pool->base.clock_sources[i] == NULL) { 1222 dm_error("DC: failed to create clock sources!\n"); 1223 BREAK_TO_DEBUGGER(); 1224 goto res_create_fail; 1225 } 1226 } 1227 1228 pool->base.dmcu = dce_dmcu_create(ctx, 1229 &dmcu_regs, 1230 &dmcu_shift, 1231 &dmcu_mask); 1232 if (pool->base.dmcu == NULL) { 1233 dm_error("DC: failed to create dmcu!\n"); 1234 BREAK_TO_DEBUGGER(); 1235 goto res_create_fail; 1236 } 1237 1238 pool->base.abm = dce_abm_create(ctx, 1239 &abm_regs, 1240 &abm_shift, 1241 &abm_mask); 1242 if (pool->base.abm == NULL) { 1243 dm_error("DC: failed to create abm!\n"); 1244 BREAK_TO_DEBUGGER(); 1245 goto res_create_fail; 1246 } 1247 1248 { 1249 struct irq_service_init_data init_data; 1250 init_data.ctx = dc->ctx; 1251 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 1252 if (!pool->base.irqs) 1253 goto res_create_fail; 1254 } 1255 1256 for (i = 0; i < pool->base.pipe_count; i++) { 1257 pool->base.timing_generators[i] = 1258 dce112_timing_generator_create( 1259 ctx, 1260 i, 1261 &dce112_tg_offsets[i]); 1262 if (pool->base.timing_generators[i] == NULL) { 1263 BREAK_TO_DEBUGGER(); 1264 dm_error("DC: failed to create tg!\n"); 1265 goto res_create_fail; 1266 } 1267 1268 pool->base.mis[i] = dce112_mem_input_create(ctx, i); 1269 if (pool->base.mis[i] == NULL) { 1270 BREAK_TO_DEBUGGER(); 1271 dm_error( 1272 "DC: failed to create memory input!\n"); 1273 goto res_create_fail; 1274 } 1275 1276 pool->base.ipps[i] = dce112_ipp_create(ctx, i); 1277 if (pool->base.ipps[i] == NULL) { 1278 BREAK_TO_DEBUGGER(); 1279 dm_error( 1280 "DC:failed to create input pixel processor!\n"); 1281 goto res_create_fail; 1282 } 1283 1284 pool->base.transforms[i] = dce112_transform_create(ctx, i); 1285 if (pool->base.transforms[i] == NULL) { 1286 BREAK_TO_DEBUGGER(); 1287 dm_error( 1288 "DC: failed to create transform!\n"); 1289 goto res_create_fail; 1290 } 1291 1292 pool->base.opps[i] = dce112_opp_create( 1293 ctx, 1294 i); 1295 if (pool->base.opps[i] == NULL) { 1296 BREAK_TO_DEBUGGER(); 1297 dm_error( 1298 "DC:failed to create output pixel processor!\n"); 1299 goto res_create_fail; 1300 } 1301 } 1302 1303 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1304 pool->base.engines[i] = dce112_aux_engine_create(ctx, i); 1305 if (pool->base.engines[i] == NULL) { 1306 BREAK_TO_DEBUGGER(); 1307 dm_error( 1308 "DC:failed to create aux engine!!\n"); 1309 goto res_create_fail; 1310 } 1311 pool->base.hw_i2cs[i] = dce112_i2c_hw_create(ctx, i); 1312 if (pool->base.hw_i2cs[i] == NULL) { 1313 BREAK_TO_DEBUGGER(); 1314 dm_error( 1315 "DC:failed to create i2c engine!!\n"); 1316 goto res_create_fail; 1317 } 1318 pool->base.sw_i2cs[i] = NULL; 1319 } 1320 1321 if (!resource_construct(num_virtual_links, dc, &pool->base, 1322 &res_create_funcs)) 1323 goto res_create_fail; 1324 1325 dc->caps.max_planes = pool->base.pipe_count; 1326 1327 for (i = 0; i < dc->caps.max_planes; ++i) 1328 dc->caps.planes[i] = plane_cap; 1329 1330 /* Create hardware sequencer */ 1331 dce112_hw_sequencer_construct(dc); 1332 1333 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1334 1335 bw_calcs_data_update_from_pplib(dc); 1336 1337 return true; 1338 1339 res_create_fail: 1340 destruct(pool); 1341 return false; 1342 } 1343 1344 struct resource_pool *dce112_create_resource_pool( 1345 uint8_t num_virtual_links, 1346 struct dc *dc) 1347 { 1348 struct dce110_resource_pool *pool = 1349 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1350 1351 if (!pool) 1352 return NULL; 1353 1354 if (construct(num_virtual_links, dc, pool)) 1355 return &pool->base; 1356 1357 kfree(pool); 1358 BREAK_TO_DEBUGGER(); 1359 return NULL; 1360 } 1361