1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include <linux/slab.h>
27 
28 #include "dm_services.h"
29 
30 #include "link_encoder.h"
31 #include "stream_encoder.h"
32 
33 #include "resource.h"
34 #include "include/irq_service_interface.h"
35 #include "dce110/dce110_resource.h"
36 #include "dce110/dce110_timing_generator.h"
37 
38 #include "irq/dce110/irq_service_dce110.h"
39 #include "dce/dce_mem_input.h"
40 #include "dce/dce_transform.h"
41 #include "dce/dce_link_encoder.h"
42 #include "dce/dce_stream_encoder.h"
43 #include "dce/dce_audio.h"
44 #include "dce/dce_opp.h"
45 #include "dce/dce_ipp.h"
46 #include "dce/dce_clock_source.h"
47 
48 #include "dce/dce_hwseq.h"
49 #include "dce112/dce112_hw_sequencer.h"
50 #include "dce/dce_abm.h"
51 #include "dce/dce_dmcu.h"
52 #include "dce/dce_aux.h"
53 #include "dce/dce_i2c.h"
54 #include "dce/dce_panel_cntl.h"
55 
56 #include "reg_helper.h"
57 
58 #include "dce/dce_11_2_d.h"
59 #include "dce/dce_11_2_sh_mask.h"
60 
61 #include "dce100/dce100_resource.h"
62 #include "dce112_resource.h"
63 
64 #define DC_LOGGER				\
65 		dc->ctx->logger
66 
67 #ifndef mmDP_DPHY_INTERNAL_CTRL
68 	#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
69 	#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
70 	#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
71 	#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
72 	#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
73 	#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
74 	#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
75 	#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
76 	#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
77 	#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
78 #endif
79 
80 #ifndef mmBIOS_SCRATCH_2
81 	#define mmBIOS_SCRATCH_2 0x05CB
82 	#define mmBIOS_SCRATCH_3 0x05CC
83 	#define mmBIOS_SCRATCH_6 0x05CF
84 #endif
85 
86 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
87 	#define mmDP_DPHY_BS_SR_SWAP_CNTL                       0x4ADC
88 	#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                   0x4ADC
89 	#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                   0x4BDC
90 	#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                   0x4CDC
91 	#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                   0x4DDC
92 	#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                   0x4EDC
93 	#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL                   0x4FDC
94 	#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL                   0x54DC
95 #endif
96 
97 #ifndef mmDP_DPHY_FAST_TRAINING
98 	#define mmDP_DPHY_FAST_TRAINING                         0x4ABC
99 	#define mmDP0_DP_DPHY_FAST_TRAINING                     0x4ABC
100 	#define mmDP1_DP_DPHY_FAST_TRAINING                     0x4BBC
101 	#define mmDP2_DP_DPHY_FAST_TRAINING                     0x4CBC
102 	#define mmDP3_DP_DPHY_FAST_TRAINING                     0x4DBC
103 	#define mmDP4_DP_DPHY_FAST_TRAINING                     0x4EBC
104 	#define mmDP5_DP_DPHY_FAST_TRAINING                     0x4FBC
105 	#define mmDP6_DP_DPHY_FAST_TRAINING                     0x54BC
106 #endif
107 
108 enum dce112_clk_src_array_id {
109 	DCE112_CLK_SRC_PLL0,
110 	DCE112_CLK_SRC_PLL1,
111 	DCE112_CLK_SRC_PLL2,
112 	DCE112_CLK_SRC_PLL3,
113 	DCE112_CLK_SRC_PLL4,
114 	DCE112_CLK_SRC_PLL5,
115 
116 	DCE112_CLK_SRC_TOTAL
117 };
118 
119 static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = {
120 	{
121 		.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
122 		.dcp =  (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
123 	},
124 	{
125 		.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
126 		.dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
127 	},
128 	{
129 		.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
130 		.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
131 	},
132 	{
133 		.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
134 		.dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
135 	},
136 	{
137 		.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
138 		.dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
139 	},
140 	{
141 		.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
142 		.dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
143 	}
144 };
145 
146 /* set register offset */
147 #define SR(reg_name)\
148 	.reg_name = mm ## reg_name
149 
150 /* set register offset with instance */
151 #define SRI(reg_name, block, id)\
152 	.reg_name = mm ## block ## id ## _ ## reg_name
153 
154 static const struct dce_dmcu_registers dmcu_regs = {
155 		DMCU_DCE110_COMMON_REG_LIST()
156 };
157 
158 static const struct dce_dmcu_shift dmcu_shift = {
159 		DMCU_MASK_SH_LIST_DCE110(__SHIFT)
160 };
161 
162 static const struct dce_dmcu_mask dmcu_mask = {
163 		DMCU_MASK_SH_LIST_DCE110(_MASK)
164 };
165 
166 static const struct dce_abm_registers abm_regs = {
167 		ABM_DCE110_COMMON_REG_LIST()
168 };
169 
170 static const struct dce_abm_shift abm_shift = {
171 		ABM_MASK_SH_LIST_DCE110(__SHIFT)
172 };
173 
174 static const struct dce_abm_mask abm_mask = {
175 		ABM_MASK_SH_LIST_DCE110(_MASK)
176 };
177 
178 static const struct dce110_aux_registers_shift aux_shift = {
179 	DCE_AUX_MASK_SH_LIST(__SHIFT)
180 };
181 
182 static const struct dce110_aux_registers_mask aux_mask = {
183 	DCE_AUX_MASK_SH_LIST(_MASK)
184 };
185 
186 #define ipp_regs(id)\
187 [id] = {\
188 		IPP_DCE110_REG_LIST_DCE_BASE(id)\
189 }
190 
191 static const struct dce_ipp_registers ipp_regs[] = {
192 		ipp_regs(0),
193 		ipp_regs(1),
194 		ipp_regs(2),
195 		ipp_regs(3),
196 		ipp_regs(4),
197 		ipp_regs(5)
198 };
199 
200 static const struct dce_ipp_shift ipp_shift = {
201 		IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
202 };
203 
204 static const struct dce_ipp_mask ipp_mask = {
205 		IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
206 };
207 
208 #define transform_regs(id)\
209 [id] = {\
210 		XFM_COMMON_REG_LIST_DCE110(id)\
211 }
212 
213 static const struct dce_transform_registers xfm_regs[] = {
214 		transform_regs(0),
215 		transform_regs(1),
216 		transform_regs(2),
217 		transform_regs(3),
218 		transform_regs(4),
219 		transform_regs(5)
220 };
221 
222 static const struct dce_transform_shift xfm_shift = {
223 		XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
224 };
225 
226 static const struct dce_transform_mask xfm_mask = {
227 		XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
228 };
229 
230 #define aux_regs(id)\
231 [id] = {\
232 	AUX_REG_LIST(id)\
233 }
234 
235 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
236 		aux_regs(0),
237 		aux_regs(1),
238 		aux_regs(2),
239 		aux_regs(3),
240 		aux_regs(4),
241 		aux_regs(5)
242 };
243 
244 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
245 	{ DCE_PANEL_CNTL_REG_LIST() }
246 };
247 
248 static const struct dce_panel_cntl_shift panel_cntl_shift = {
249 	DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
250 };
251 
252 static const struct dce_panel_cntl_mask panel_cntl_mask = {
253 	DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
254 };
255 
256 #define hpd_regs(id)\
257 [id] = {\
258 	HPD_REG_LIST(id)\
259 }
260 
261 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
262 		hpd_regs(0),
263 		hpd_regs(1),
264 		hpd_regs(2),
265 		hpd_regs(3),
266 		hpd_regs(4),
267 		hpd_regs(5)
268 };
269 
270 #define link_regs(id)\
271 [id] = {\
272 	LE_DCE110_REG_LIST(id)\
273 }
274 
275 static const struct dce110_link_enc_registers link_enc_regs[] = {
276 	link_regs(0),
277 	link_regs(1),
278 	link_regs(2),
279 	link_regs(3),
280 	link_regs(4),
281 	link_regs(5),
282 	link_regs(6),
283 };
284 
285 #define stream_enc_regs(id)\
286 [id] = {\
287 	SE_COMMON_REG_LIST(id),\
288 	.TMDS_CNTL = 0,\
289 }
290 
291 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
292 	stream_enc_regs(0),
293 	stream_enc_regs(1),
294 	stream_enc_regs(2),
295 	stream_enc_regs(3),
296 	stream_enc_regs(4),
297 	stream_enc_regs(5)
298 };
299 
300 static const struct dce_stream_encoder_shift se_shift = {
301 		SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT)
302 };
303 
304 static const struct dce_stream_encoder_mask se_mask = {
305 		SE_COMMON_MASK_SH_LIST_DCE112(_MASK)
306 };
307 
308 #define opp_regs(id)\
309 [id] = {\
310 	OPP_DCE_112_REG_LIST(id),\
311 }
312 
313 static const struct dce_opp_registers opp_regs[] = {
314 	opp_regs(0),
315 	opp_regs(1),
316 	opp_regs(2),
317 	opp_regs(3),
318 	opp_regs(4),
319 	opp_regs(5)
320 };
321 
322 static const struct dce_opp_shift opp_shift = {
323 	OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
324 };
325 
326 static const struct dce_opp_mask opp_mask = {
327 	OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK)
328 };
329 
330 #define aux_engine_regs(id)\
331 [id] = {\
332 	AUX_COMMON_REG_LIST(id), \
333 	.AUX_RESET_MASK = 0 \
334 }
335 
336 static const struct dce110_aux_registers aux_engine_regs[] = {
337 		aux_engine_regs(0),
338 		aux_engine_regs(1),
339 		aux_engine_regs(2),
340 		aux_engine_regs(3),
341 		aux_engine_regs(4),
342 		aux_engine_regs(5)
343 };
344 
345 #define audio_regs(id)\
346 [id] = {\
347 	AUD_COMMON_REG_LIST(id)\
348 }
349 
350 static const struct dce_audio_registers audio_regs[] = {
351 	audio_regs(0),
352 	audio_regs(1),
353 	audio_regs(2),
354 	audio_regs(3),
355 	audio_regs(4),
356 	audio_regs(5)
357 };
358 
359 static const struct dce_audio_shift audio_shift = {
360 		AUD_COMMON_MASK_SH_LIST(__SHIFT)
361 };
362 
363 static const struct dce_audio_mask audio_mask = {
364 		AUD_COMMON_MASK_SH_LIST(_MASK)
365 };
366 
367 #define clk_src_regs(index, id)\
368 [index] = {\
369 	CS_COMMON_REG_LIST_DCE_112(id),\
370 }
371 
372 static const struct dce110_clk_src_regs clk_src_regs[] = {
373 	clk_src_regs(0, A),
374 	clk_src_regs(1, B),
375 	clk_src_regs(2, C),
376 	clk_src_regs(3, D),
377 	clk_src_regs(4, E),
378 	clk_src_regs(5, F)
379 };
380 
381 static const struct dce110_clk_src_shift cs_shift = {
382 		CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
383 };
384 
385 static const struct dce110_clk_src_mask cs_mask = {
386 		CS_COMMON_MASK_SH_LIST_DCE_112(_MASK)
387 };
388 
389 static const struct bios_registers bios_regs = {
390 	.BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
391 	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
392 };
393 
394 static const struct resource_caps polaris_10_resource_cap = {
395 		.num_timing_generator = 6,
396 		.num_audio = 6,
397 		.num_stream_encoder = 6,
398 		.num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
399 		.num_ddc = 6,
400 };
401 
402 static const struct resource_caps polaris_11_resource_cap = {
403 		.num_timing_generator = 5,
404 		.num_audio = 5,
405 		.num_stream_encoder = 5,
406 		.num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
407 		.num_ddc = 5,
408 };
409 
410 static const struct dc_plane_cap plane_cap = {
411 	.type = DC_PLANE_TYPE_DCE_RGB,
412 
413 	.pixel_format_support = {
414 			.argb8888 = true,
415 			.nv12 = false,
416 			.fp16 = true
417 	},
418 
419 	.max_upscale_factor = {
420 			.argb8888 = 16000,
421 			.nv12 = 1,
422 			.fp16 = 1
423 	},
424 
425 	.max_downscale_factor = {
426 			.argb8888 = 250,
427 			.nv12 = 1,
428 			.fp16 = 1
429 	},
430 	64,
431 	64
432 };
433 
434 #define CTX  ctx
435 #define REG(reg) mm ## reg
436 
437 #ifndef mmCC_DC_HDMI_STRAPS
438 #define mmCC_DC_HDMI_STRAPS 0x4819
439 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
440 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
441 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
442 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
443 #endif
444 
445 static int map_transmitter_id_to_phy_instance(
446 	enum transmitter transmitter)
447 {
448 	switch (transmitter) {
449 	case TRANSMITTER_UNIPHY_A:
450 		return 0;
451 	case TRANSMITTER_UNIPHY_B:
452 		return 1;
453 	case TRANSMITTER_UNIPHY_C:
454 		return 2;
455 	case TRANSMITTER_UNIPHY_D:
456 		return 3;
457 	case TRANSMITTER_UNIPHY_E:
458 		return 4;
459 	case TRANSMITTER_UNIPHY_F:
460 		return 5;
461 	case TRANSMITTER_UNIPHY_G:
462 		return 6;
463 	default:
464 		ASSERT(0);
465 		return 0;
466 	}
467 }
468 
469 static void read_dce_straps(
470 	struct dc_context *ctx,
471 	struct resource_straps *straps)
472 {
473 	REG_GET_2(CC_DC_HDMI_STRAPS,
474 			HDMI_DISABLE, &straps->hdmi_disable,
475 			AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
476 
477 	REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
478 }
479 
480 static struct audio *create_audio(
481 		struct dc_context *ctx, unsigned int inst)
482 {
483 	return dce_audio_create(ctx, inst,
484 			&audio_regs[inst], &audio_shift, &audio_mask);
485 }
486 
487 
488 static struct timing_generator *dce112_timing_generator_create(
489 		struct dc_context *ctx,
490 		uint32_t instance,
491 		const struct dce110_timing_generator_offsets *offsets)
492 {
493 	struct dce110_timing_generator *tg110 =
494 		kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
495 
496 	if (!tg110)
497 		return NULL;
498 
499 	dce110_timing_generator_construct(tg110, ctx, instance, offsets);
500 	return &tg110->base;
501 }
502 
503 static struct stream_encoder *dce112_stream_encoder_create(
504 	enum engine_id eng_id,
505 	struct dc_context *ctx)
506 {
507 	struct dce110_stream_encoder *enc110 =
508 		kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
509 
510 	if (!enc110)
511 		return NULL;
512 
513 	dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
514 					&stream_enc_regs[eng_id],
515 					&se_shift, &se_mask);
516 	return &enc110->base;
517 }
518 
519 #define SRII(reg_name, block, id)\
520 	.reg_name[id] = mm ## block ## id ## _ ## reg_name
521 
522 static const struct dce_hwseq_registers hwseq_reg = {
523 		HWSEQ_DCE112_REG_LIST()
524 };
525 
526 static const struct dce_hwseq_shift hwseq_shift = {
527 		HWSEQ_DCE112_MASK_SH_LIST(__SHIFT)
528 };
529 
530 static const struct dce_hwseq_mask hwseq_mask = {
531 		HWSEQ_DCE112_MASK_SH_LIST(_MASK)
532 };
533 
534 static struct dce_hwseq *dce112_hwseq_create(
535 	struct dc_context *ctx)
536 {
537 	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
538 
539 	if (hws) {
540 		hws->ctx = ctx;
541 		hws->regs = &hwseq_reg;
542 		hws->shifts = &hwseq_shift;
543 		hws->masks = &hwseq_mask;
544 	}
545 	return hws;
546 }
547 
548 static const struct resource_create_funcs res_create_funcs = {
549 	.read_dce_straps = read_dce_straps,
550 	.create_audio = create_audio,
551 	.create_stream_encoder = dce112_stream_encoder_create,
552 	.create_hwseq = dce112_hwseq_create,
553 };
554 
555 #define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) }
556 static const struct dce_mem_input_registers mi_regs[] = {
557 		mi_inst_regs(0),
558 		mi_inst_regs(1),
559 		mi_inst_regs(2),
560 		mi_inst_regs(3),
561 		mi_inst_regs(4),
562 		mi_inst_regs(5),
563 };
564 
565 static const struct dce_mem_input_shift mi_shifts = {
566 		MI_DCE11_2_MASK_SH_LIST(__SHIFT)
567 };
568 
569 static const struct dce_mem_input_mask mi_masks = {
570 		MI_DCE11_2_MASK_SH_LIST(_MASK)
571 };
572 
573 static struct mem_input *dce112_mem_input_create(
574 	struct dc_context *ctx,
575 	uint32_t inst)
576 {
577 	struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
578 					       GFP_KERNEL);
579 
580 	if (!dce_mi) {
581 		BREAK_TO_DEBUGGER();
582 		return NULL;
583 	}
584 
585 	dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
586 	return &dce_mi->base;
587 }
588 
589 static void dce112_transform_destroy(struct transform **xfm)
590 {
591 	kfree(TO_DCE_TRANSFORM(*xfm));
592 	*xfm = NULL;
593 }
594 
595 static struct transform *dce112_transform_create(
596 	struct dc_context *ctx,
597 	uint32_t inst)
598 {
599 	struct dce_transform *transform =
600 		kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
601 
602 	if (!transform)
603 		return NULL;
604 
605 	dce_transform_construct(transform, ctx, inst,
606 				&xfm_regs[inst], &xfm_shift, &xfm_mask);
607 	transform->lb_memory_size = 0x1404; /*5124*/
608 	return &transform->base;
609 }
610 
611 static const struct encoder_feature_support link_enc_feature = {
612 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
613 		.max_hdmi_pixel_clock = 600000,
614 		.hdmi_ycbcr420_supported = true,
615 		.dp_ycbcr420_supported = false,
616 		.flags.bits.IS_HBR2_CAPABLE = true,
617 		.flags.bits.IS_HBR3_CAPABLE = true,
618 		.flags.bits.IS_TPS3_CAPABLE = true,
619 		.flags.bits.IS_TPS4_CAPABLE = true
620 };
621 
622 static struct link_encoder *dce112_link_encoder_create(
623 	const struct encoder_init_data *enc_init_data)
624 {
625 	struct dce110_link_encoder *enc110 =
626 		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
627 	int link_regs_id;
628 
629 	if (!enc110)
630 		return NULL;
631 
632 	link_regs_id =
633 		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
634 
635 	dce110_link_encoder_construct(enc110,
636 				      enc_init_data,
637 				      &link_enc_feature,
638 				      &link_enc_regs[link_regs_id],
639 				      &link_enc_aux_regs[enc_init_data->channel - 1],
640 				      &link_enc_hpd_regs[enc_init_data->hpd_source]);
641 	return &enc110->base;
642 }
643 
644 static struct panel_cntl *dce112_panel_cntl_create(const struct panel_cntl_init_data *init_data)
645 {
646 	struct dce_panel_cntl *panel_cntl =
647 		kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
648 
649 	if (!panel_cntl)
650 		return NULL;
651 
652 	dce_panel_cntl_construct(panel_cntl,
653 			init_data,
654 			&panel_cntl_regs[init_data->inst],
655 			&panel_cntl_shift,
656 			&panel_cntl_mask);
657 
658 	return &panel_cntl->base;
659 }
660 
661 static struct input_pixel_processor *dce112_ipp_create(
662 	struct dc_context *ctx, uint32_t inst)
663 {
664 	struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
665 
666 	if (!ipp) {
667 		BREAK_TO_DEBUGGER();
668 		return NULL;
669 	}
670 
671 	dce_ipp_construct(ipp, ctx, inst,
672 			&ipp_regs[inst], &ipp_shift, &ipp_mask);
673 	return &ipp->base;
674 }
675 
676 static struct output_pixel_processor *dce112_opp_create(
677 	struct dc_context *ctx,
678 	uint32_t inst)
679 {
680 	struct dce110_opp *opp =
681 		kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
682 
683 	if (!opp)
684 		return NULL;
685 
686 	dce110_opp_construct(opp,
687 			     ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
688 	return &opp->base;
689 }
690 
691 static struct dce_aux *dce112_aux_engine_create(
692 	struct dc_context *ctx,
693 	uint32_t inst)
694 {
695 	struct aux_engine_dce110 *aux_engine =
696 		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
697 
698 	if (!aux_engine)
699 		return NULL;
700 
701 	dce110_aux_engine_construct(aux_engine, ctx, inst,
702 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
703 				    &aux_engine_regs[inst],
704 					&aux_mask,
705 					&aux_shift,
706 					ctx->dc->caps.extended_aux_timeout_support);
707 
708 	return &aux_engine->base;
709 }
710 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
711 
712 static const struct dce_i2c_registers i2c_hw_regs[] = {
713 		i2c_inst_regs(1),
714 		i2c_inst_regs(2),
715 		i2c_inst_regs(3),
716 		i2c_inst_regs(4),
717 		i2c_inst_regs(5),
718 		i2c_inst_regs(6),
719 };
720 
721 static const struct dce_i2c_shift i2c_shifts = {
722 		I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
723 };
724 
725 static const struct dce_i2c_mask i2c_masks = {
726 		I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
727 };
728 
729 static struct dce_i2c_hw *dce112_i2c_hw_create(
730 	struct dc_context *ctx,
731 	uint32_t inst)
732 {
733 	struct dce_i2c_hw *dce_i2c_hw =
734 		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
735 
736 	if (!dce_i2c_hw)
737 		return NULL;
738 
739 	dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,
740 				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
741 
742 	return dce_i2c_hw;
743 }
744 static struct clock_source *dce112_clock_source_create(
745 	struct dc_context *ctx,
746 	struct dc_bios *bios,
747 	enum clock_source_id id,
748 	const struct dce110_clk_src_regs *regs,
749 	bool dp_clk_src)
750 {
751 	struct dce110_clk_src *clk_src =
752 		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
753 
754 	if (!clk_src)
755 		return NULL;
756 
757 	if (dce112_clk_src_construct(clk_src, ctx, bios, id,
758 			regs, &cs_shift, &cs_mask)) {
759 		clk_src->base.dp_clk_src = dp_clk_src;
760 		return &clk_src->base;
761 	}
762 
763 	kfree(clk_src);
764 	BREAK_TO_DEBUGGER();
765 	return NULL;
766 }
767 
768 static void dce112_clock_source_destroy(struct clock_source **clk_src)
769 {
770 	kfree(TO_DCE110_CLK_SRC(*clk_src));
771 	*clk_src = NULL;
772 }
773 
774 static void dce112_resource_destruct(struct dce110_resource_pool *pool)
775 {
776 	unsigned int i;
777 
778 	for (i = 0; i < pool->base.pipe_count; i++) {
779 		if (pool->base.opps[i] != NULL)
780 			dce110_opp_destroy(&pool->base.opps[i]);
781 
782 		if (pool->base.transforms[i] != NULL)
783 			dce112_transform_destroy(&pool->base.transforms[i]);
784 
785 		if (pool->base.ipps[i] != NULL)
786 			dce_ipp_destroy(&pool->base.ipps[i]);
787 
788 		if (pool->base.mis[i] != NULL) {
789 			kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
790 			pool->base.mis[i] = NULL;
791 		}
792 
793 		if (pool->base.timing_generators[i] != NULL) {
794 			kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
795 			pool->base.timing_generators[i] = NULL;
796 		}
797 	}
798 
799 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
800 		if (pool->base.engines[i] != NULL)
801 			dce110_engine_destroy(&pool->base.engines[i]);
802 		if (pool->base.hw_i2cs[i] != NULL) {
803 			kfree(pool->base.hw_i2cs[i]);
804 			pool->base.hw_i2cs[i] = NULL;
805 		}
806 		if (pool->base.sw_i2cs[i] != NULL) {
807 			kfree(pool->base.sw_i2cs[i]);
808 			pool->base.sw_i2cs[i] = NULL;
809 		}
810 	}
811 
812 	for (i = 0; i < pool->base.stream_enc_count; i++) {
813 		if (pool->base.stream_enc[i] != NULL)
814 			kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
815 	}
816 
817 	for (i = 0; i < pool->base.clk_src_count; i++) {
818 		if (pool->base.clock_sources[i] != NULL) {
819 			dce112_clock_source_destroy(&pool->base.clock_sources[i]);
820 		}
821 	}
822 
823 	if (pool->base.dp_clock_source != NULL)
824 		dce112_clock_source_destroy(&pool->base.dp_clock_source);
825 
826 	for (i = 0; i < pool->base.audio_count; i++)	{
827 		if (pool->base.audios[i] != NULL) {
828 			dce_aud_destroy(&pool->base.audios[i]);
829 		}
830 	}
831 
832 	if (pool->base.abm != NULL)
833 		dce_abm_destroy(&pool->base.abm);
834 
835 	if (pool->base.dmcu != NULL)
836 		dce_dmcu_destroy(&pool->base.dmcu);
837 
838 	if (pool->base.irqs != NULL) {
839 		dal_irq_service_destroy(&pool->base.irqs);
840 	}
841 }
842 
843 static struct clock_source *find_matching_pll(
844 		struct resource_context *res_ctx,
845 		const struct resource_pool *pool,
846 		const struct dc_stream_state *const stream)
847 {
848 	switch (stream->link->link_enc->transmitter) {
849 	case TRANSMITTER_UNIPHY_A:
850 		return pool->clock_sources[DCE112_CLK_SRC_PLL0];
851 	case TRANSMITTER_UNIPHY_B:
852 		return pool->clock_sources[DCE112_CLK_SRC_PLL1];
853 	case TRANSMITTER_UNIPHY_C:
854 		return pool->clock_sources[DCE112_CLK_SRC_PLL2];
855 	case TRANSMITTER_UNIPHY_D:
856 		return pool->clock_sources[DCE112_CLK_SRC_PLL3];
857 	case TRANSMITTER_UNIPHY_E:
858 		return pool->clock_sources[DCE112_CLK_SRC_PLL4];
859 	case TRANSMITTER_UNIPHY_F:
860 		return pool->clock_sources[DCE112_CLK_SRC_PLL5];
861 	default:
862 		return NULL;
863 	}
864 
865 	return NULL;
866 }
867 
868 static enum dc_status build_mapped_resource(
869 		const struct dc *dc,
870 		struct dc_state *context,
871 		struct dc_stream_state *stream)
872 {
873 	struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
874 
875 	if (!pipe_ctx)
876 		return DC_ERROR_UNEXPECTED;
877 
878 	dce110_resource_build_pipe_hw_param(pipe_ctx);
879 
880 	resource_build_info_frame(pipe_ctx);
881 
882 	return DC_OK;
883 }
884 
885 bool dce112_validate_bandwidth(
886 	struct dc *dc,
887 	struct dc_state *context,
888 	bool fast_validate)
889 {
890 	bool result = false;
891 
892 	DC_LOG_BANDWIDTH_CALCS(
893 		"%s: start",
894 		__func__);
895 
896 	if (bw_calcs(
897 			dc->ctx,
898 			dc->bw_dceip,
899 			dc->bw_vbios,
900 			context->res_ctx.pipe_ctx,
901 			dc->res_pool->pipe_count,
902 			&context->bw_ctx.bw.dce))
903 		result = true;
904 
905 	if (!result)
906 		DC_LOG_BANDWIDTH_VALIDATION(
907 			"%s: Bandwidth validation failed!",
908 			__func__);
909 
910 	if (memcmp(&dc->current_state->bw_ctx.bw.dce,
911 			&context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) {
912 
913 		DC_LOG_BANDWIDTH_CALCS(
914 			"%s: finish,\n"
915 			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
916 			"stutMark_b: %d stutMark_a: %d\n"
917 			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
918 			"stutMark_b: %d stutMark_a: %d\n"
919 			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
920 			"stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n"
921 			"cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
922 			"sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n"
923 			,
924 			__func__,
925 			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark,
926 			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark,
927 			context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark,
928 			context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark,
929 			context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark,
930 			context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark,
931 			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark,
932 			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark,
933 			context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark,
934 			context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark,
935 			context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark,
936 			context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark,
937 			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark,
938 			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark,
939 			context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark,
940 			context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark,
941 			context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark,
942 			context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark,
943 			context->bw_ctx.bw.dce.stutter_mode_enable,
944 			context->bw_ctx.bw.dce.cpuc_state_change_enable,
945 			context->bw_ctx.bw.dce.cpup_state_change_enable,
946 			context->bw_ctx.bw.dce.nbp_state_change_enable,
947 			context->bw_ctx.bw.dce.all_displays_in_sync,
948 			context->bw_ctx.bw.dce.dispclk_khz,
949 			context->bw_ctx.bw.dce.sclk_khz,
950 			context->bw_ctx.bw.dce.sclk_deep_sleep_khz,
951 			context->bw_ctx.bw.dce.yclk_khz,
952 			context->bw_ctx.bw.dce.blackout_recovery_time_us);
953 	}
954 	return result;
955 }
956 
957 enum dc_status resource_map_phy_clock_resources(
958 		const struct dc *dc,
959 		struct dc_state *context,
960 		struct dc_stream_state *stream)
961 {
962 
963 	/* acquire new resources */
964 	struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
965 			&context->res_ctx, stream);
966 
967 	if (!pipe_ctx)
968 		return DC_ERROR_UNEXPECTED;
969 
970 	if (dc_is_dp_signal(pipe_ctx->stream->signal)
971 		|| dc_is_virtual_signal(pipe_ctx->stream->signal))
972 		pipe_ctx->clock_source =
973 				dc->res_pool->dp_clock_source;
974 	else
975 		pipe_ctx->clock_source = find_matching_pll(
976 			&context->res_ctx, dc->res_pool,
977 			stream);
978 
979 	if (pipe_ctx->clock_source == NULL)
980 		return DC_NO_CLOCK_SOURCE_RESOURCE;
981 
982 	resource_reference_clock_source(
983 		&context->res_ctx,
984 		dc->res_pool,
985 		pipe_ctx->clock_source);
986 
987 	return DC_OK;
988 }
989 
990 static bool dce112_validate_surface_sets(
991 		struct dc_state *context)
992 {
993 	int i;
994 
995 	for (i = 0; i < context->stream_count; i++) {
996 		if (context->stream_status[i].plane_count == 0)
997 			continue;
998 
999 		if (context->stream_status[i].plane_count > 1)
1000 			return false;
1001 
1002 		if (context->stream_status[i].plane_states[0]->format
1003 				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
1004 			return false;
1005 	}
1006 
1007 	return true;
1008 }
1009 
1010 enum dc_status dce112_add_stream_to_ctx(
1011 		struct dc *dc,
1012 		struct dc_state *new_ctx,
1013 		struct dc_stream_state *dc_stream)
1014 {
1015 	enum dc_status result;
1016 
1017 	result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1018 
1019 	if (result == DC_OK)
1020 		result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1021 
1022 
1023 	if (result == DC_OK)
1024 		result = build_mapped_resource(dc, new_ctx, dc_stream);
1025 
1026 	return result;
1027 }
1028 
1029 static enum dc_status dce112_validate_global(
1030 		struct dc *dc,
1031 		struct dc_state *context)
1032 {
1033 	if (!dce112_validate_surface_sets(context))
1034 		return DC_FAIL_SURFACE_VALIDATE;
1035 
1036 	return DC_OK;
1037 }
1038 
1039 static void dce112_destroy_resource_pool(struct resource_pool **pool)
1040 {
1041 	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
1042 
1043 	dce112_resource_destruct(dce110_pool);
1044 	kfree(dce110_pool);
1045 	*pool = NULL;
1046 }
1047 
1048 static const struct resource_funcs dce112_res_pool_funcs = {
1049 	.destroy = dce112_destroy_resource_pool,
1050 	.link_enc_create = dce112_link_encoder_create,
1051 	.panel_cntl_create = dce112_panel_cntl_create,
1052 	.validate_bandwidth = dce112_validate_bandwidth,
1053 	.validate_plane = dce100_validate_plane,
1054 	.add_stream_to_ctx = dce112_add_stream_to_ctx,
1055 	.validate_global = dce112_validate_global,
1056 	.find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link
1057 };
1058 
1059 static void bw_calcs_data_update_from_pplib(struct dc *dc)
1060 {
1061 	struct dm_pp_clock_levels_with_latency eng_clks = {0};
1062 	struct dm_pp_clock_levels_with_latency mem_clks = {0};
1063 	struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
1064 	struct dm_pp_clock_levels clks = {0};
1065 	int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ;
1066 
1067 	if (dc->bw_vbios && dc->bw_vbios->memory_type == bw_def_hbm)
1068 		memory_type_multiplier = MEMORY_TYPE_HBM;
1069 
1070 	/*do system clock  TODO PPLIB: after PPLIB implement,
1071 	 * then remove old way
1072 	 */
1073 	if (!dm_pp_get_clock_levels_by_type_with_latency(
1074 			dc->ctx,
1075 			DM_PP_CLOCK_TYPE_ENGINE_CLK,
1076 			&eng_clks)) {
1077 
1078 		/* This is only for temporary */
1079 		dm_pp_get_clock_levels_by_type(
1080 				dc->ctx,
1081 				DM_PP_CLOCK_TYPE_ENGINE_CLK,
1082 				&clks);
1083 		/* convert all the clock fro kHz to fix point mHz */
1084 		dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1085 				clks.clocks_in_khz[clks.num_levels-1], 1000);
1086 		dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
1087 				clks.clocks_in_khz[clks.num_levels/8], 1000);
1088 		dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
1089 				clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1090 		dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
1091 				clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1092 		dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
1093 				clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1094 		dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
1095 				clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1096 		dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
1097 				clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1098 		dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
1099 				clks.clocks_in_khz[0], 1000);
1100 
1101 		/*do memory clock*/
1102 		dm_pp_get_clock_levels_by_type(
1103 				dc->ctx,
1104 				DM_PP_CLOCK_TYPE_MEMORY_CLK,
1105 				&clks);
1106 
1107 		dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1108 			clks.clocks_in_khz[0] * memory_type_multiplier, 1000);
1109 		dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1110 			clks.clocks_in_khz[clks.num_levels>>1] * memory_type_multiplier,
1111 			1000);
1112 		dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1113 			clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier,
1114 			1000);
1115 
1116 		return;
1117 	}
1118 
1119 	/* convert all the clock fro kHz to fix point mHz  TODO: wloop data */
1120 	dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1121 		eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
1122 	dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
1123 		eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
1124 	dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
1125 		eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
1126 	dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
1127 		eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
1128 	dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
1129 		eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
1130 	dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
1131 		eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
1132 	dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
1133 		eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
1134 	dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
1135 			eng_clks.data[0].clocks_in_khz, 1000);
1136 
1137 	/*do memory clock*/
1138 	dm_pp_get_clock_levels_by_type_with_latency(
1139 			dc->ctx,
1140 			DM_PP_CLOCK_TYPE_MEMORY_CLK,
1141 			&mem_clks);
1142 
1143 	/* we don't need to call PPLIB for validation clock since they
1144 	 * also give us the highest sclk and highest mclk (UMA clock).
1145 	 * ALSO always convert UMA clock (from PPLIB)  to YCLK (HW formula):
1146 	 * YCLK = UMACLK*m_memoryTypeMultiplier
1147 	 */
1148 	dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1149 		mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000);
1150 	dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1151 		mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier,
1152 		1000);
1153 	dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1154 		mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier,
1155 		1000);
1156 
1157 	/* Now notify PPLib/SMU about which Watermarks sets they should select
1158 	 * depending on DPM state they are in. And update BW MGR GFX Engine and
1159 	 * Memory clock member variables for Watermarks calculations for each
1160 	 * Watermark Set
1161 	 */
1162 	clk_ranges.num_wm_sets = 4;
1163 	clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
1164 	clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
1165 			eng_clks.data[0].clocks_in_khz;
1166 	clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
1167 			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1168 	clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz =
1169 			mem_clks.data[0].clocks_in_khz;
1170 	clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
1171 			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1172 
1173 	clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B;
1174 	clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz =
1175 			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1176 	/* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1177 	clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
1178 	clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz =
1179 			mem_clks.data[0].clocks_in_khz;
1180 	clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
1181 			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1182 
1183 	clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C;
1184 	clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz =
1185 			eng_clks.data[0].clocks_in_khz;
1186 	clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
1187 			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1188 	clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz =
1189 			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1190 	/* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1191 	clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
1192 
1193 	clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D;
1194 	clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz =
1195 			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1196 	/* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1197 	clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
1198 	clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz =
1199 			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1200 	/* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1201 	clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
1202 
1203 	/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1204 	dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
1205 }
1206 
1207 static const struct resource_caps *dce112_resource_cap(
1208 	struct hw_asic_id *asic_id)
1209 {
1210 	if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) ||
1211 	    ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev))
1212 		return &polaris_11_resource_cap;
1213 	else
1214 		return &polaris_10_resource_cap;
1215 }
1216 
1217 static bool dce112_resource_construct(
1218 	uint8_t num_virtual_links,
1219 	struct dc *dc,
1220 	struct dce110_resource_pool *pool)
1221 {
1222 	unsigned int i;
1223 	struct dc_context *ctx = dc->ctx;
1224 
1225 	ctx->dc_bios->regs = &bios_regs;
1226 
1227 	pool->base.res_cap = dce112_resource_cap(&ctx->asic_id);
1228 	pool->base.funcs = &dce112_res_pool_funcs;
1229 
1230 	/*************************************************
1231 	 *  Resource + asic cap harcoding                *
1232 	 *************************************************/
1233 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1234 	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1235 	pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1236 	dc->caps.max_downscale_ratio = 200;
1237 	dc->caps.i2c_speed_in_khz = 100;
1238 	dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
1239 	dc->caps.max_cursor_size = 128;
1240 	dc->caps.min_horizontal_blanking_period = 80;
1241 	dc->caps.dual_link_dvi = true;
1242 	dc->caps.extended_aux_timeout_support = false;
1243 
1244 	/*************************************************
1245 	 *  Create resources                             *
1246 	 *************************************************/
1247 
1248 	pool->base.clock_sources[DCE112_CLK_SRC_PLL0] =
1249 			dce112_clock_source_create(
1250 				ctx, ctx->dc_bios,
1251 				CLOCK_SOURCE_COMBO_PHY_PLL0,
1252 				&clk_src_regs[0], false);
1253 	pool->base.clock_sources[DCE112_CLK_SRC_PLL1] =
1254 			dce112_clock_source_create(
1255 				ctx, ctx->dc_bios,
1256 				CLOCK_SOURCE_COMBO_PHY_PLL1,
1257 				&clk_src_regs[1], false);
1258 	pool->base.clock_sources[DCE112_CLK_SRC_PLL2] =
1259 			dce112_clock_source_create(
1260 				ctx, ctx->dc_bios,
1261 				CLOCK_SOURCE_COMBO_PHY_PLL2,
1262 				&clk_src_regs[2], false);
1263 	pool->base.clock_sources[DCE112_CLK_SRC_PLL3] =
1264 			dce112_clock_source_create(
1265 				ctx, ctx->dc_bios,
1266 				CLOCK_SOURCE_COMBO_PHY_PLL3,
1267 				&clk_src_regs[3], false);
1268 	pool->base.clock_sources[DCE112_CLK_SRC_PLL4] =
1269 			dce112_clock_source_create(
1270 				ctx, ctx->dc_bios,
1271 				CLOCK_SOURCE_COMBO_PHY_PLL4,
1272 				&clk_src_regs[4], false);
1273 	pool->base.clock_sources[DCE112_CLK_SRC_PLL5] =
1274 			dce112_clock_source_create(
1275 				ctx, ctx->dc_bios,
1276 				CLOCK_SOURCE_COMBO_PHY_PLL5,
1277 				&clk_src_regs[5], false);
1278 	pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL;
1279 
1280 	pool->base.dp_clock_source =  dce112_clock_source_create(
1281 		ctx, ctx->dc_bios,
1282 		CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true);
1283 
1284 
1285 	for (i = 0; i < pool->base.clk_src_count; i++) {
1286 		if (pool->base.clock_sources[i] == NULL) {
1287 			dm_error("DC: failed to create clock sources!\n");
1288 			BREAK_TO_DEBUGGER();
1289 			goto res_create_fail;
1290 		}
1291 	}
1292 
1293 	pool->base.dmcu = dce_dmcu_create(ctx,
1294 			&dmcu_regs,
1295 			&dmcu_shift,
1296 			&dmcu_mask);
1297 	if (pool->base.dmcu == NULL) {
1298 		dm_error("DC: failed to create dmcu!\n");
1299 		BREAK_TO_DEBUGGER();
1300 		goto res_create_fail;
1301 	}
1302 
1303 	pool->base.abm = dce_abm_create(ctx,
1304 			&abm_regs,
1305 			&abm_shift,
1306 			&abm_mask);
1307 	if (pool->base.abm == NULL) {
1308 		dm_error("DC: failed to create abm!\n");
1309 		BREAK_TO_DEBUGGER();
1310 		goto res_create_fail;
1311 	}
1312 
1313 	{
1314 		struct irq_service_init_data init_data;
1315 		init_data.ctx = dc->ctx;
1316 		pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1317 		if (!pool->base.irqs)
1318 			goto res_create_fail;
1319 	}
1320 
1321 	for (i = 0; i < pool->base.pipe_count; i++) {
1322 		pool->base.timing_generators[i] =
1323 				dce112_timing_generator_create(
1324 					ctx,
1325 					i,
1326 					&dce112_tg_offsets[i]);
1327 		if (pool->base.timing_generators[i] == NULL) {
1328 			BREAK_TO_DEBUGGER();
1329 			dm_error("DC: failed to create tg!\n");
1330 			goto res_create_fail;
1331 		}
1332 
1333 		pool->base.mis[i] = dce112_mem_input_create(ctx, i);
1334 		if (pool->base.mis[i] == NULL) {
1335 			BREAK_TO_DEBUGGER();
1336 			dm_error(
1337 				"DC: failed to create memory input!\n");
1338 			goto res_create_fail;
1339 		}
1340 
1341 		pool->base.ipps[i] = dce112_ipp_create(ctx, i);
1342 		if (pool->base.ipps[i] == NULL) {
1343 			BREAK_TO_DEBUGGER();
1344 			dm_error(
1345 				"DC:failed to create input pixel processor!\n");
1346 			goto res_create_fail;
1347 		}
1348 
1349 		pool->base.transforms[i] = dce112_transform_create(ctx, i);
1350 		if (pool->base.transforms[i] == NULL) {
1351 			BREAK_TO_DEBUGGER();
1352 			dm_error(
1353 				"DC: failed to create transform!\n");
1354 			goto res_create_fail;
1355 		}
1356 
1357 		pool->base.opps[i] = dce112_opp_create(
1358 			ctx,
1359 			i);
1360 		if (pool->base.opps[i] == NULL) {
1361 			BREAK_TO_DEBUGGER();
1362 			dm_error(
1363 				"DC:failed to create output pixel processor!\n");
1364 			goto res_create_fail;
1365 		}
1366 	}
1367 
1368 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1369 		pool->base.engines[i] = dce112_aux_engine_create(ctx, i);
1370 		if (pool->base.engines[i] == NULL) {
1371 			BREAK_TO_DEBUGGER();
1372 			dm_error(
1373 				"DC:failed to create aux engine!!\n");
1374 			goto res_create_fail;
1375 		}
1376 		pool->base.hw_i2cs[i] = dce112_i2c_hw_create(ctx, i);
1377 		if (pool->base.hw_i2cs[i] == NULL) {
1378 			BREAK_TO_DEBUGGER();
1379 			dm_error(
1380 				"DC:failed to create i2c engine!!\n");
1381 			goto res_create_fail;
1382 		}
1383 		pool->base.sw_i2cs[i] = NULL;
1384 	}
1385 
1386 	if (!resource_construct(num_virtual_links, dc, &pool->base,
1387 			  &res_create_funcs))
1388 		goto res_create_fail;
1389 
1390 	dc->caps.max_planes =  pool->base.pipe_count;
1391 
1392 	for (i = 0; i < dc->caps.max_planes; ++i)
1393 		dc->caps.planes[i] = plane_cap;
1394 
1395 	/* Create hardware sequencer */
1396 	dce112_hw_sequencer_construct(dc);
1397 
1398 	bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1399 
1400 	bw_calcs_data_update_from_pplib(dc);
1401 
1402 	return true;
1403 
1404 res_create_fail:
1405 	dce112_resource_destruct(pool);
1406 	return false;
1407 }
1408 
1409 struct resource_pool *dce112_create_resource_pool(
1410 	uint8_t num_virtual_links,
1411 	struct dc *dc)
1412 {
1413 	struct dce110_resource_pool *pool =
1414 		kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1415 
1416 	if (!pool)
1417 		return NULL;
1418 
1419 	if (dce112_resource_construct(num_virtual_links, dc, pool))
1420 		return &pool->base;
1421 
1422 	kfree(pool);
1423 	BREAK_TO_DEBUGGER();
1424 	return NULL;
1425 }
1426