1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "link_encoder.h" 29 #include "stream_encoder.h" 30 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dce110/dce110_resource.h" 34 #include "dce110/dce110_timing_generator.h" 35 36 #include "irq/dce110/irq_service_dce110.h" 37 38 #include "dce/dce_mem_input.h" 39 #include "dce/dce_transform.h" 40 #include "dce/dce_link_encoder.h" 41 #include "dce/dce_stream_encoder.h" 42 #include "dce/dce_audio.h" 43 #include "dce/dce_opp.h" 44 #include "dce/dce_ipp.h" 45 #include "dce/dce_clocks.h" 46 #include "dce/dce_clock_source.h" 47 48 #include "dce/dce_hwseq.h" 49 #include "dce112/dce112_hw_sequencer.h" 50 #include "dce/dce_abm.h" 51 #include "dce/dce_dmcu.h" 52 53 #include "reg_helper.h" 54 55 #include "dce/dce_11_2_d.h" 56 #include "dce/dce_11_2_sh_mask.h" 57 58 #include "dce100/dce100_resource.h" 59 60 #ifndef mmDP_DPHY_INTERNAL_CTRL 61 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 62 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 63 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 64 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 65 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 66 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 67 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 68 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 69 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 70 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 71 #endif 72 73 #ifndef mmBIOS_SCRATCH_2 74 #define mmBIOS_SCRATCH_2 0x05CB 75 #define mmBIOS_SCRATCH_6 0x05CF 76 #endif 77 78 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 79 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 80 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 81 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 82 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 83 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 84 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 85 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 86 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 87 #endif 88 89 #ifndef mmDP_DPHY_FAST_TRAINING 90 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 91 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 92 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 93 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 94 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 95 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 96 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 97 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 98 #endif 99 100 enum dce112_clk_src_array_id { 101 DCE112_CLK_SRC_PLL0, 102 DCE112_CLK_SRC_PLL1, 103 DCE112_CLK_SRC_PLL2, 104 DCE112_CLK_SRC_PLL3, 105 DCE112_CLK_SRC_PLL4, 106 DCE112_CLK_SRC_PLL5, 107 108 DCE112_CLK_SRC_TOTAL 109 }; 110 111 static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = { 112 { 113 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 114 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 115 }, 116 { 117 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 118 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 119 }, 120 { 121 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 122 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 123 }, 124 { 125 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 126 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 127 }, 128 { 129 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 130 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 131 }, 132 { 133 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 134 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 135 } 136 }; 137 138 /* set register offset */ 139 #define SR(reg_name)\ 140 .reg_name = mm ## reg_name 141 142 /* set register offset with instance */ 143 #define SRI(reg_name, block, id)\ 144 .reg_name = mm ## block ## id ## _ ## reg_name 145 146 147 static const struct dce_disp_clk_registers disp_clk_regs = { 148 CLK_COMMON_REG_LIST_DCE_BASE() 149 }; 150 151 static const struct dce_disp_clk_shift disp_clk_shift = { 152 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 153 }; 154 155 static const struct dce_disp_clk_mask disp_clk_mask = { 156 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 157 }; 158 159 static const struct dce_dmcu_registers dmcu_regs = { 160 DMCU_DCE110_COMMON_REG_LIST() 161 }; 162 163 static const struct dce_dmcu_shift dmcu_shift = { 164 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 165 }; 166 167 static const struct dce_dmcu_mask dmcu_mask = { 168 DMCU_MASK_SH_LIST_DCE110(_MASK) 169 }; 170 171 static const struct dce_abm_registers abm_regs = { 172 ABM_DCE110_COMMON_REG_LIST() 173 }; 174 175 static const struct dce_abm_shift abm_shift = { 176 ABM_MASK_SH_LIST_DCE110(__SHIFT) 177 }; 178 179 static const struct dce_abm_mask abm_mask = { 180 ABM_MASK_SH_LIST_DCE110(_MASK) 181 }; 182 183 #define ipp_regs(id)\ 184 [id] = {\ 185 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 186 } 187 188 static const struct dce_ipp_registers ipp_regs[] = { 189 ipp_regs(0), 190 ipp_regs(1), 191 ipp_regs(2), 192 ipp_regs(3), 193 ipp_regs(4), 194 ipp_regs(5) 195 }; 196 197 static const struct dce_ipp_shift ipp_shift = { 198 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 199 }; 200 201 static const struct dce_ipp_mask ipp_mask = { 202 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 203 }; 204 205 #define transform_regs(id)\ 206 [id] = {\ 207 XFM_COMMON_REG_LIST_DCE110(id)\ 208 } 209 210 static const struct dce_transform_registers xfm_regs[] = { 211 transform_regs(0), 212 transform_regs(1), 213 transform_regs(2), 214 transform_regs(3), 215 transform_regs(4), 216 transform_regs(5) 217 }; 218 219 static const struct dce_transform_shift xfm_shift = { 220 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 221 }; 222 223 static const struct dce_transform_mask xfm_mask = { 224 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 225 }; 226 227 #define aux_regs(id)\ 228 [id] = {\ 229 AUX_REG_LIST(id)\ 230 } 231 232 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 233 aux_regs(0), 234 aux_regs(1), 235 aux_regs(2), 236 aux_regs(3), 237 aux_regs(4), 238 aux_regs(5) 239 }; 240 241 #define hpd_regs(id)\ 242 [id] = {\ 243 HPD_REG_LIST(id)\ 244 } 245 246 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 247 hpd_regs(0), 248 hpd_regs(1), 249 hpd_regs(2), 250 hpd_regs(3), 251 hpd_regs(4), 252 hpd_regs(5) 253 }; 254 255 #define link_regs(id)\ 256 [id] = {\ 257 LE_DCE110_REG_LIST(id)\ 258 } 259 260 static const struct dce110_link_enc_registers link_enc_regs[] = { 261 link_regs(0), 262 link_regs(1), 263 link_regs(2), 264 link_regs(3), 265 link_regs(4), 266 link_regs(5), 267 link_regs(6), 268 }; 269 270 #define stream_enc_regs(id)\ 271 [id] = {\ 272 SE_COMMON_REG_LIST(id),\ 273 .TMDS_CNTL = 0,\ 274 } 275 276 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 277 stream_enc_regs(0), 278 stream_enc_regs(1), 279 stream_enc_regs(2), 280 stream_enc_regs(3), 281 stream_enc_regs(4), 282 stream_enc_regs(5) 283 }; 284 285 static const struct dce_stream_encoder_shift se_shift = { 286 SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT) 287 }; 288 289 static const struct dce_stream_encoder_mask se_mask = { 290 SE_COMMON_MASK_SH_LIST_DCE112(_MASK) 291 }; 292 293 #define opp_regs(id)\ 294 [id] = {\ 295 OPP_DCE_112_REG_LIST(id),\ 296 } 297 298 static const struct dce_opp_registers opp_regs[] = { 299 opp_regs(0), 300 opp_regs(1), 301 opp_regs(2), 302 opp_regs(3), 303 opp_regs(4), 304 opp_regs(5) 305 }; 306 307 static const struct dce_opp_shift opp_shift = { 308 OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 309 }; 310 311 static const struct dce_opp_mask opp_mask = { 312 OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK) 313 }; 314 315 #define audio_regs(id)\ 316 [id] = {\ 317 AUD_COMMON_REG_LIST(id)\ 318 } 319 320 static const struct dce_audio_registers audio_regs[] = { 321 audio_regs(0), 322 audio_regs(1), 323 audio_regs(2), 324 audio_regs(3), 325 audio_regs(4), 326 audio_regs(5) 327 }; 328 329 static const struct dce_audio_shift audio_shift = { 330 AUD_COMMON_MASK_SH_LIST(__SHIFT) 331 }; 332 333 static const struct dce_aduio_mask audio_mask = { 334 AUD_COMMON_MASK_SH_LIST(_MASK) 335 }; 336 337 #define clk_src_regs(index, id)\ 338 [index] = {\ 339 CS_COMMON_REG_LIST_DCE_112(id),\ 340 } 341 342 static const struct dce110_clk_src_regs clk_src_regs[] = { 343 clk_src_regs(0, A), 344 clk_src_regs(1, B), 345 clk_src_regs(2, C), 346 clk_src_regs(3, D), 347 clk_src_regs(4, E), 348 clk_src_regs(5, F) 349 }; 350 351 static const struct dce110_clk_src_shift cs_shift = { 352 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 353 }; 354 355 static const struct dce110_clk_src_mask cs_mask = { 356 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) 357 }; 358 359 static const struct bios_registers bios_regs = { 360 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 361 }; 362 363 static const struct resource_caps polaris_10_resource_cap = { 364 .num_timing_generator = 6, 365 .num_audio = 6, 366 .num_stream_encoder = 6, 367 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */ 368 }; 369 370 static const struct resource_caps polaris_11_resource_cap = { 371 .num_timing_generator = 5, 372 .num_audio = 5, 373 .num_stream_encoder = 5, 374 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */ 375 }; 376 377 #define CTX ctx 378 #define REG(reg) mm ## reg 379 380 #ifndef mmCC_DC_HDMI_STRAPS 381 #define mmCC_DC_HDMI_STRAPS 0x4819 382 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 383 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 384 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 385 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 386 #endif 387 388 static void read_dce_straps( 389 struct dc_context *ctx, 390 struct resource_straps *straps) 391 { 392 REG_GET_2(CC_DC_HDMI_STRAPS, 393 HDMI_DISABLE, &straps->hdmi_disable, 394 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 395 396 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 397 } 398 399 static struct audio *create_audio( 400 struct dc_context *ctx, unsigned int inst) 401 { 402 return dce_audio_create(ctx, inst, 403 &audio_regs[inst], &audio_shift, &audio_mask); 404 } 405 406 407 static struct timing_generator *dce112_timing_generator_create( 408 struct dc_context *ctx, 409 uint32_t instance, 410 const struct dce110_timing_generator_offsets *offsets) 411 { 412 struct dce110_timing_generator *tg110 = 413 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 414 415 if (!tg110) 416 return NULL; 417 418 if (dce110_timing_generator_construct(tg110, ctx, instance, offsets)) 419 return &tg110->base; 420 421 BREAK_TO_DEBUGGER(); 422 kfree(tg110); 423 return NULL; 424 } 425 426 static struct stream_encoder *dce112_stream_encoder_create( 427 enum engine_id eng_id, 428 struct dc_context *ctx) 429 { 430 struct dce110_stream_encoder *enc110 = 431 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 432 433 if (!enc110) 434 return NULL; 435 436 if (dce110_stream_encoder_construct( 437 enc110, ctx, ctx->dc_bios, eng_id, 438 &stream_enc_regs[eng_id], &se_shift, &se_mask)) 439 return &enc110->base; 440 441 BREAK_TO_DEBUGGER(); 442 kfree(enc110); 443 return NULL; 444 } 445 446 #define SRII(reg_name, block, id)\ 447 .reg_name[id] = mm ## block ## id ## _ ## reg_name 448 449 static const struct dce_hwseq_registers hwseq_reg = { 450 HWSEQ_DCE112_REG_LIST() 451 }; 452 453 static const struct dce_hwseq_shift hwseq_shift = { 454 HWSEQ_DCE112_MASK_SH_LIST(__SHIFT) 455 }; 456 457 static const struct dce_hwseq_mask hwseq_mask = { 458 HWSEQ_DCE112_MASK_SH_LIST(_MASK) 459 }; 460 461 static struct dce_hwseq *dce112_hwseq_create( 462 struct dc_context *ctx) 463 { 464 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 465 466 if (hws) { 467 hws->ctx = ctx; 468 hws->regs = &hwseq_reg; 469 hws->shifts = &hwseq_shift; 470 hws->masks = &hwseq_mask; 471 } 472 return hws; 473 } 474 475 static const struct resource_create_funcs res_create_funcs = { 476 .read_dce_straps = read_dce_straps, 477 .create_audio = create_audio, 478 .create_stream_encoder = dce112_stream_encoder_create, 479 .create_hwseq = dce112_hwseq_create, 480 }; 481 482 #define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) } 483 static const struct dce_mem_input_registers mi_regs[] = { 484 mi_inst_regs(0), 485 mi_inst_regs(1), 486 mi_inst_regs(2), 487 mi_inst_regs(3), 488 mi_inst_regs(4), 489 mi_inst_regs(5), 490 }; 491 492 static const struct dce_mem_input_shift mi_shifts = { 493 MI_DCE11_2_MASK_SH_LIST(__SHIFT) 494 }; 495 496 static const struct dce_mem_input_mask mi_masks = { 497 MI_DCE11_2_MASK_SH_LIST(_MASK) 498 }; 499 500 static struct mem_input *dce112_mem_input_create( 501 struct dc_context *ctx, 502 uint32_t inst) 503 { 504 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 505 GFP_KERNEL); 506 507 if (!dce_mi) { 508 BREAK_TO_DEBUGGER(); 509 return NULL; 510 } 511 512 dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 513 return &dce_mi->base; 514 } 515 516 static void dce112_transform_destroy(struct transform **xfm) 517 { 518 kfree(TO_DCE_TRANSFORM(*xfm)); 519 *xfm = NULL; 520 } 521 522 static struct transform *dce112_transform_create( 523 struct dc_context *ctx, 524 uint32_t inst) 525 { 526 struct dce_transform *transform = 527 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 528 529 if (!transform) 530 return NULL; 531 532 if (dce_transform_construct(transform, ctx, inst, 533 &xfm_regs[inst], &xfm_shift, &xfm_mask)) { 534 transform->lb_memory_size = 0x1404; /*5124*/ 535 return &transform->base; 536 } 537 538 BREAK_TO_DEBUGGER(); 539 kfree(transform); 540 return NULL; 541 } 542 543 static const struct encoder_feature_support link_enc_feature = { 544 .max_hdmi_deep_color = COLOR_DEPTH_121212, 545 .max_hdmi_pixel_clock = 600000, 546 .ycbcr420_supported = true, 547 .flags.bits.IS_HBR2_CAPABLE = true, 548 .flags.bits.IS_HBR3_CAPABLE = true, 549 .flags.bits.IS_TPS3_CAPABLE = true, 550 .flags.bits.IS_TPS4_CAPABLE = true, 551 .flags.bits.IS_YCBCR_CAPABLE = true 552 }; 553 554 struct link_encoder *dce112_link_encoder_create( 555 const struct encoder_init_data *enc_init_data) 556 { 557 struct dce110_link_encoder *enc110 = 558 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 559 560 if (!enc110) 561 return NULL; 562 563 if (dce110_link_encoder_construct( 564 enc110, 565 enc_init_data, 566 &link_enc_feature, 567 &link_enc_regs[enc_init_data->transmitter], 568 &link_enc_aux_regs[enc_init_data->channel - 1], 569 &link_enc_hpd_regs[enc_init_data->hpd_source])) { 570 571 return &enc110->base; 572 } 573 574 BREAK_TO_DEBUGGER(); 575 kfree(enc110); 576 return NULL; 577 } 578 579 static struct input_pixel_processor *dce112_ipp_create( 580 struct dc_context *ctx, uint32_t inst) 581 { 582 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 583 584 if (!ipp) { 585 BREAK_TO_DEBUGGER(); 586 return NULL; 587 } 588 589 dce_ipp_construct(ipp, ctx, inst, 590 &ipp_regs[inst], &ipp_shift, &ipp_mask); 591 return &ipp->base; 592 } 593 594 struct output_pixel_processor *dce112_opp_create( 595 struct dc_context *ctx, 596 uint32_t inst) 597 { 598 struct dce110_opp *opp = 599 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 600 601 if (!opp) 602 return NULL; 603 604 if (dce110_opp_construct(opp, 605 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask)) 606 return &opp->base; 607 608 BREAK_TO_DEBUGGER(); 609 kfree(opp); 610 return NULL; 611 } 612 613 struct clock_source *dce112_clock_source_create( 614 struct dc_context *ctx, 615 struct dc_bios *bios, 616 enum clock_source_id id, 617 const struct dce110_clk_src_regs *regs, 618 bool dp_clk_src) 619 { 620 struct dce110_clk_src *clk_src = 621 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 622 623 if (!clk_src) 624 return NULL; 625 626 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 627 regs, &cs_shift, &cs_mask)) { 628 clk_src->base.dp_clk_src = dp_clk_src; 629 return &clk_src->base; 630 } 631 632 BREAK_TO_DEBUGGER(); 633 return NULL; 634 } 635 636 void dce112_clock_source_destroy(struct clock_source **clk_src) 637 { 638 kfree(TO_DCE110_CLK_SRC(*clk_src)); 639 *clk_src = NULL; 640 } 641 642 static void destruct(struct dce110_resource_pool *pool) 643 { 644 unsigned int i; 645 646 for (i = 0; i < pool->base.pipe_count; i++) { 647 if (pool->base.opps[i] != NULL) 648 dce110_opp_destroy(&pool->base.opps[i]); 649 650 if (pool->base.transforms[i] != NULL) 651 dce112_transform_destroy(&pool->base.transforms[i]); 652 653 if (pool->base.ipps[i] != NULL) 654 dce_ipp_destroy(&pool->base.ipps[i]); 655 656 if (pool->base.mis[i] != NULL) { 657 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 658 pool->base.mis[i] = NULL; 659 } 660 661 if (pool->base.timing_generators[i] != NULL) { 662 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 663 pool->base.timing_generators[i] = NULL; 664 } 665 } 666 667 for (i = 0; i < pool->base.stream_enc_count; i++) { 668 if (pool->base.stream_enc[i] != NULL) 669 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 670 } 671 672 for (i = 0; i < pool->base.clk_src_count; i++) { 673 if (pool->base.clock_sources[i] != NULL) { 674 dce112_clock_source_destroy(&pool->base.clock_sources[i]); 675 } 676 } 677 678 if (pool->base.dp_clock_source != NULL) 679 dce112_clock_source_destroy(&pool->base.dp_clock_source); 680 681 for (i = 0; i < pool->base.audio_count; i++) { 682 if (pool->base.audios[i] != NULL) { 683 dce_aud_destroy(&pool->base.audios[i]); 684 } 685 } 686 687 if (pool->base.abm != NULL) 688 dce_abm_destroy(&pool->base.abm); 689 690 if (pool->base.dmcu != NULL) 691 dce_dmcu_destroy(&pool->base.dmcu); 692 693 if (pool->base.display_clock != NULL) 694 dce_disp_clk_destroy(&pool->base.display_clock); 695 696 if (pool->base.irqs != NULL) { 697 dal_irq_service_destroy(&pool->base.irqs); 698 } 699 } 700 701 static struct clock_source *find_matching_pll( 702 struct resource_context *res_ctx, 703 const struct resource_pool *pool, 704 const struct dc_stream_state *const stream) 705 { 706 switch (stream->sink->link->link_enc->transmitter) { 707 case TRANSMITTER_UNIPHY_A: 708 return pool->clock_sources[DCE112_CLK_SRC_PLL0]; 709 case TRANSMITTER_UNIPHY_B: 710 return pool->clock_sources[DCE112_CLK_SRC_PLL1]; 711 case TRANSMITTER_UNIPHY_C: 712 return pool->clock_sources[DCE112_CLK_SRC_PLL2]; 713 case TRANSMITTER_UNIPHY_D: 714 return pool->clock_sources[DCE112_CLK_SRC_PLL3]; 715 case TRANSMITTER_UNIPHY_E: 716 return pool->clock_sources[DCE112_CLK_SRC_PLL4]; 717 case TRANSMITTER_UNIPHY_F: 718 return pool->clock_sources[DCE112_CLK_SRC_PLL5]; 719 default: 720 return NULL; 721 }; 722 723 return 0; 724 } 725 726 static enum dc_status build_mapped_resource( 727 const struct dc *dc, 728 struct dc_state *context, 729 struct dc_stream_state *stream) 730 { 731 enum dc_status status = DC_OK; 732 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 733 734 if (!pipe_ctx) 735 return DC_ERROR_UNEXPECTED; 736 737 status = dce110_resource_build_pipe_hw_param(pipe_ctx); 738 739 if (status != DC_OK) 740 return status; 741 742 resource_build_info_frame(pipe_ctx); 743 744 return DC_OK; 745 } 746 747 bool dce112_validate_bandwidth( 748 struct dc *dc, 749 struct dc_state *context) 750 { 751 bool result = false; 752 753 dm_logger_write( 754 dc->ctx->logger, LOG_BANDWIDTH_CALCS, 755 "%s: start", 756 __func__); 757 758 if (bw_calcs( 759 dc->ctx, 760 dc->bw_dceip, 761 dc->bw_vbios, 762 context->res_ctx.pipe_ctx, 763 dc->res_pool->pipe_count, 764 &context->bw.dce)) 765 result = true; 766 767 if (!result) 768 dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION, 769 "%s: Bandwidth validation failed!", 770 __func__); 771 772 if (memcmp(&dc->current_state->bw.dce, 773 &context->bw.dce, sizeof(context->bw.dce))) { 774 struct log_entry log_entry; 775 dm_logger_open( 776 dc->ctx->logger, 777 &log_entry, 778 LOG_BANDWIDTH_CALCS); 779 dm_logger_append(&log_entry, "%s: finish,\n" 780 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 781 "stutMark_b: %d stutMark_a: %d\n", 782 __func__, 783 context->bw.dce.nbp_state_change_wm_ns[0].b_mark, 784 context->bw.dce.nbp_state_change_wm_ns[0].a_mark, 785 context->bw.dce.urgent_wm_ns[0].b_mark, 786 context->bw.dce.urgent_wm_ns[0].a_mark, 787 context->bw.dce.stutter_exit_wm_ns[0].b_mark, 788 context->bw.dce.stutter_exit_wm_ns[0].a_mark); 789 dm_logger_append(&log_entry, 790 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 791 "stutMark_b: %d stutMark_a: %d\n", 792 context->bw.dce.nbp_state_change_wm_ns[1].b_mark, 793 context->bw.dce.nbp_state_change_wm_ns[1].a_mark, 794 context->bw.dce.urgent_wm_ns[1].b_mark, 795 context->bw.dce.urgent_wm_ns[1].a_mark, 796 context->bw.dce.stutter_exit_wm_ns[1].b_mark, 797 context->bw.dce.stutter_exit_wm_ns[1].a_mark); 798 dm_logger_append(&log_entry, 799 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 800 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n", 801 context->bw.dce.nbp_state_change_wm_ns[2].b_mark, 802 context->bw.dce.nbp_state_change_wm_ns[2].a_mark, 803 context->bw.dce.urgent_wm_ns[2].b_mark, 804 context->bw.dce.urgent_wm_ns[2].a_mark, 805 context->bw.dce.stutter_exit_wm_ns[2].b_mark, 806 context->bw.dce.stutter_exit_wm_ns[2].a_mark, 807 context->bw.dce.stutter_mode_enable); 808 dm_logger_append(&log_entry, 809 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" 810 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n", 811 context->bw.dce.cpuc_state_change_enable, 812 context->bw.dce.cpup_state_change_enable, 813 context->bw.dce.nbp_state_change_enable, 814 context->bw.dce.all_displays_in_sync, 815 context->bw.dce.dispclk_khz, 816 context->bw.dce.sclk_khz, 817 context->bw.dce.sclk_deep_sleep_khz, 818 context->bw.dce.yclk_khz, 819 context->bw.dce.blackout_recovery_time_us); 820 dm_logger_close(&log_entry); 821 } 822 return result; 823 } 824 825 enum dc_status resource_map_phy_clock_resources( 826 const struct dc *dc, 827 struct dc_state *context, 828 struct dc_stream_state *stream) 829 { 830 831 /* acquire new resources */ 832 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( 833 &context->res_ctx, stream); 834 835 if (!pipe_ctx) 836 return DC_ERROR_UNEXPECTED; 837 838 if (dc_is_dp_signal(pipe_ctx->stream->signal) 839 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) 840 pipe_ctx->clock_source = 841 dc->res_pool->dp_clock_source; 842 else 843 pipe_ctx->clock_source = find_matching_pll( 844 &context->res_ctx, dc->res_pool, 845 stream); 846 847 if (pipe_ctx->clock_source == NULL) 848 return DC_NO_CLOCK_SOURCE_RESOURCE; 849 850 resource_reference_clock_source( 851 &context->res_ctx, 852 dc->res_pool, 853 pipe_ctx->clock_source); 854 855 return DC_OK; 856 } 857 858 static bool dce112_validate_surface_sets( 859 struct dc_state *context) 860 { 861 int i; 862 863 for (i = 0; i < context->stream_count; i++) { 864 if (context->stream_status[i].plane_count == 0) 865 continue; 866 867 if (context->stream_status[i].plane_count > 1) 868 return false; 869 870 if (context->stream_status[i].plane_states[0]->format 871 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 872 return false; 873 } 874 875 return true; 876 } 877 878 enum dc_status dce112_add_stream_to_ctx( 879 struct dc *dc, 880 struct dc_state *new_ctx, 881 struct dc_stream_state *dc_stream) 882 { 883 enum dc_status result = DC_ERROR_UNEXPECTED; 884 885 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 886 887 if (result == DC_OK) 888 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 889 890 891 if (result == DC_OK) 892 result = build_mapped_resource(dc, new_ctx, dc_stream); 893 894 return result; 895 } 896 897 enum dc_status dce112_validate_guaranteed( 898 struct dc *dc, 899 struct dc_stream_state *stream, 900 struct dc_state *context) 901 { 902 enum dc_status result = DC_ERROR_UNEXPECTED; 903 904 context->streams[0] = stream; 905 dc_stream_retain(context->streams[0]); 906 context->stream_count++; 907 908 result = resource_map_pool_resources(dc, context, stream); 909 910 if (result == DC_OK) 911 result = resource_map_phy_clock_resources(dc, context, stream); 912 913 if (result == DC_OK) 914 result = build_mapped_resource(dc, context, stream); 915 916 if (result == DC_OK) { 917 validate_guaranteed_copy_streams( 918 context, dc->caps.max_streams); 919 result = resource_build_scaling_params_for_context(dc, context); 920 } 921 922 if (result == DC_OK) 923 if (!dce112_validate_bandwidth(dc, context)) 924 result = DC_FAIL_BANDWIDTH_VALIDATE; 925 926 return result; 927 } 928 929 enum dc_status dce112_validate_global( 930 struct dc *dc, 931 struct dc_state *context) 932 { 933 if (!dce112_validate_surface_sets(context)) 934 return DC_FAIL_SURFACE_VALIDATE; 935 936 return DC_OK; 937 } 938 939 static void dce112_destroy_resource_pool(struct resource_pool **pool) 940 { 941 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 942 943 destruct(dce110_pool); 944 kfree(dce110_pool); 945 *pool = NULL; 946 } 947 948 static const struct resource_funcs dce112_res_pool_funcs = { 949 .destroy = dce112_destroy_resource_pool, 950 .link_enc_create = dce112_link_encoder_create, 951 .validate_guaranteed = dce112_validate_guaranteed, 952 .validate_bandwidth = dce112_validate_bandwidth, 953 .validate_plane = dce100_validate_plane, 954 .add_stream_to_ctx = dce112_add_stream_to_ctx, 955 .validate_global = dce112_validate_global 956 }; 957 958 static void bw_calcs_data_update_from_pplib(struct dc *dc) 959 { 960 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 961 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 962 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; 963 struct dm_pp_clock_levels clks = {0}; 964 965 /*do system clock TODO PPLIB: after PPLIB implement, 966 * then remove old way 967 */ 968 if (!dm_pp_get_clock_levels_by_type_with_latency( 969 dc->ctx, 970 DM_PP_CLOCK_TYPE_ENGINE_CLK, 971 &eng_clks)) { 972 973 /* This is only for temporary */ 974 dm_pp_get_clock_levels_by_type( 975 dc->ctx, 976 DM_PP_CLOCK_TYPE_ENGINE_CLK, 977 &clks); 978 /* convert all the clock fro kHz to fix point mHz */ 979 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 980 clks.clocks_in_khz[clks.num_levels-1], 1000); 981 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 982 clks.clocks_in_khz[clks.num_levels/8], 1000); 983 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 984 clks.clocks_in_khz[clks.num_levels*2/8], 1000); 985 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 986 clks.clocks_in_khz[clks.num_levels*3/8], 1000); 987 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 988 clks.clocks_in_khz[clks.num_levels*4/8], 1000); 989 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 990 clks.clocks_in_khz[clks.num_levels*5/8], 1000); 991 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 992 clks.clocks_in_khz[clks.num_levels*6/8], 1000); 993 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 994 clks.clocks_in_khz[0], 1000); 995 996 /*do memory clock*/ 997 dm_pp_get_clock_levels_by_type( 998 dc->ctx, 999 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1000 &clks); 1001 1002 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1003 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000); 1004 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1005 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER, 1006 1000); 1007 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1008 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER, 1009 1000); 1010 1011 return; 1012 } 1013 1014 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ 1015 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 1016 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); 1017 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 1018 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); 1019 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 1020 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); 1021 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 1022 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); 1023 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 1024 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); 1025 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 1026 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); 1027 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1028 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); 1029 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1030 eng_clks.data[0].clocks_in_khz, 1000); 1031 1032 /*do memory clock*/ 1033 dm_pp_get_clock_levels_by_type_with_latency( 1034 dc->ctx, 1035 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1036 &mem_clks); 1037 1038 /* we don't need to call PPLIB for validation clock since they 1039 * also give us the highest sclk and highest mclk (UMA clock). 1040 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): 1041 * YCLK = UMACLK*m_memoryTypeMultiplier 1042 */ 1043 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1044 mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000); 1045 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1046 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1047 1000); 1048 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1049 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1050 1000); 1051 1052 /* Now notify PPLib/SMU about which Watermarks sets they should select 1053 * depending on DPM state they are in. And update BW MGR GFX Engine and 1054 * Memory clock member variables for Watermarks calculations for each 1055 * Watermark Set 1056 */ 1057 clk_ranges.num_wm_sets = 4; 1058 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; 1059 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = 1060 eng_clks.data[0].clocks_in_khz; 1061 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = 1062 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 1063 clk_ranges.wm_clk_ranges[0].wm_min_memg_clk_in_khz = 1064 mem_clks.data[0].clocks_in_khz; 1065 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = 1066 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 1067 1068 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; 1069 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = 1070 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 1071 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 1072 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; 1073 clk_ranges.wm_clk_ranges[1].wm_min_memg_clk_in_khz = 1074 mem_clks.data[0].clocks_in_khz; 1075 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = 1076 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 1077 1078 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; 1079 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = 1080 eng_clks.data[0].clocks_in_khz; 1081 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = 1082 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 1083 clk_ranges.wm_clk_ranges[2].wm_min_memg_clk_in_khz = 1084 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 1085 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 1086 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; 1087 1088 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; 1089 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = 1090 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 1091 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 1092 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; 1093 clk_ranges.wm_clk_ranges[3].wm_min_memg_clk_in_khz = 1094 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 1095 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 1096 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; 1097 1098 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 1099 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); 1100 } 1101 1102 const struct resource_caps *dce112_resource_cap( 1103 struct hw_asic_id *asic_id) 1104 { 1105 if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) || 1106 ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev)) 1107 return &polaris_11_resource_cap; 1108 else 1109 return &polaris_10_resource_cap; 1110 } 1111 1112 static bool construct( 1113 uint8_t num_virtual_links, 1114 struct dc *dc, 1115 struct dce110_resource_pool *pool) 1116 { 1117 unsigned int i; 1118 struct dc_context *ctx = dc->ctx; 1119 struct dm_pp_static_clock_info static_clk_info = {0}; 1120 1121 ctx->dc_bios->regs = &bios_regs; 1122 1123 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id); 1124 pool->base.funcs = &dce112_res_pool_funcs; 1125 1126 /************************************************* 1127 * Resource + asic cap harcoding * 1128 *************************************************/ 1129 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1130 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1131 dc->caps.max_downscale_ratio = 200; 1132 dc->caps.i2c_speed_in_khz = 100; 1133 dc->caps.max_cursor_size = 128; 1134 1135 /************************************************* 1136 * Create resources * 1137 *************************************************/ 1138 1139 pool->base.clock_sources[DCE112_CLK_SRC_PLL0] = 1140 dce112_clock_source_create( 1141 ctx, ctx->dc_bios, 1142 CLOCK_SOURCE_COMBO_PHY_PLL0, 1143 &clk_src_regs[0], false); 1144 pool->base.clock_sources[DCE112_CLK_SRC_PLL1] = 1145 dce112_clock_source_create( 1146 ctx, ctx->dc_bios, 1147 CLOCK_SOURCE_COMBO_PHY_PLL1, 1148 &clk_src_regs[1], false); 1149 pool->base.clock_sources[DCE112_CLK_SRC_PLL2] = 1150 dce112_clock_source_create( 1151 ctx, ctx->dc_bios, 1152 CLOCK_SOURCE_COMBO_PHY_PLL2, 1153 &clk_src_regs[2], false); 1154 pool->base.clock_sources[DCE112_CLK_SRC_PLL3] = 1155 dce112_clock_source_create( 1156 ctx, ctx->dc_bios, 1157 CLOCK_SOURCE_COMBO_PHY_PLL3, 1158 &clk_src_regs[3], false); 1159 pool->base.clock_sources[DCE112_CLK_SRC_PLL4] = 1160 dce112_clock_source_create( 1161 ctx, ctx->dc_bios, 1162 CLOCK_SOURCE_COMBO_PHY_PLL4, 1163 &clk_src_regs[4], false); 1164 pool->base.clock_sources[DCE112_CLK_SRC_PLL5] = 1165 dce112_clock_source_create( 1166 ctx, ctx->dc_bios, 1167 CLOCK_SOURCE_COMBO_PHY_PLL5, 1168 &clk_src_regs[5], false); 1169 pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL; 1170 1171 pool->base.dp_clock_source = dce112_clock_source_create( 1172 ctx, ctx->dc_bios, 1173 CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); 1174 1175 1176 for (i = 0; i < pool->base.clk_src_count; i++) { 1177 if (pool->base.clock_sources[i] == NULL) { 1178 dm_error("DC: failed to create clock sources!\n"); 1179 BREAK_TO_DEBUGGER(); 1180 goto res_create_fail; 1181 } 1182 } 1183 1184 pool->base.display_clock = dce112_disp_clk_create(ctx, 1185 &disp_clk_regs, 1186 &disp_clk_shift, 1187 &disp_clk_mask); 1188 if (pool->base.display_clock == NULL) { 1189 dm_error("DC: failed to create display clock!\n"); 1190 BREAK_TO_DEBUGGER(); 1191 goto res_create_fail; 1192 } 1193 1194 pool->base.dmcu = dce_dmcu_create(ctx, 1195 &dmcu_regs, 1196 &dmcu_shift, 1197 &dmcu_mask); 1198 if (pool->base.dmcu == NULL) { 1199 dm_error("DC: failed to create dmcu!\n"); 1200 BREAK_TO_DEBUGGER(); 1201 goto res_create_fail; 1202 } 1203 1204 pool->base.abm = dce_abm_create(ctx, 1205 &abm_regs, 1206 &abm_shift, 1207 &abm_mask); 1208 if (pool->base.abm == NULL) { 1209 dm_error("DC: failed to create abm!\n"); 1210 BREAK_TO_DEBUGGER(); 1211 goto res_create_fail; 1212 } 1213 1214 /* get static clock information for PPLIB or firmware, save 1215 * max_clock_state 1216 */ 1217 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 1218 pool->base.display_clock->max_clks_state = 1219 static_clk_info.max_clocks_state; 1220 1221 { 1222 struct irq_service_init_data init_data; 1223 init_data.ctx = dc->ctx; 1224 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 1225 if (!pool->base.irqs) 1226 goto res_create_fail; 1227 } 1228 1229 for (i = 0; i < pool->base.pipe_count; i++) { 1230 pool->base.timing_generators[i] = 1231 dce112_timing_generator_create( 1232 ctx, 1233 i, 1234 &dce112_tg_offsets[i]); 1235 if (pool->base.timing_generators[i] == NULL) { 1236 BREAK_TO_DEBUGGER(); 1237 dm_error("DC: failed to create tg!\n"); 1238 goto res_create_fail; 1239 } 1240 1241 pool->base.mis[i] = dce112_mem_input_create(ctx, i); 1242 if (pool->base.mis[i] == NULL) { 1243 BREAK_TO_DEBUGGER(); 1244 dm_error( 1245 "DC: failed to create memory input!\n"); 1246 goto res_create_fail; 1247 } 1248 1249 pool->base.ipps[i] = dce112_ipp_create(ctx, i); 1250 if (pool->base.ipps[i] == NULL) { 1251 BREAK_TO_DEBUGGER(); 1252 dm_error( 1253 "DC:failed to create input pixel processor!\n"); 1254 goto res_create_fail; 1255 } 1256 1257 pool->base.transforms[i] = dce112_transform_create(ctx, i); 1258 if (pool->base.transforms[i] == NULL) { 1259 BREAK_TO_DEBUGGER(); 1260 dm_error( 1261 "DC: failed to create transform!\n"); 1262 goto res_create_fail; 1263 } 1264 1265 pool->base.opps[i] = dce112_opp_create( 1266 ctx, 1267 i); 1268 if (pool->base.opps[i] == NULL) { 1269 BREAK_TO_DEBUGGER(); 1270 dm_error( 1271 "DC:failed to create output pixel processor!\n"); 1272 goto res_create_fail; 1273 } 1274 } 1275 1276 if (!resource_construct(num_virtual_links, dc, &pool->base, 1277 &res_create_funcs)) 1278 goto res_create_fail; 1279 1280 dc->caps.max_planes = pool->base.pipe_count; 1281 1282 /* Create hardware sequencer */ 1283 if (!dce112_hw_sequencer_construct(dc)) 1284 goto res_create_fail; 1285 1286 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1287 1288 bw_calcs_data_update_from_pplib(dc); 1289 1290 return true; 1291 1292 res_create_fail: 1293 destruct(pool); 1294 return false; 1295 } 1296 1297 struct resource_pool *dce112_create_resource_pool( 1298 uint8_t num_virtual_links, 1299 struct dc *dc) 1300 { 1301 struct dce110_resource_pool *pool = 1302 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1303 1304 if (!pool) 1305 return NULL; 1306 1307 if (construct(num_virtual_links, dc, pool)) 1308 return &pool->base; 1309 1310 BREAK_TO_DEBUGGER(); 1311 return NULL; 1312 } 1313