1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "link_encoder.h" 29 #include "stream_encoder.h" 30 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dce110/dce110_resource.h" 34 #include "dce110/dce110_timing_generator.h" 35 36 #include "irq/dce110/irq_service_dce110.h" 37 38 #include "dce/dce_mem_input.h" 39 #include "dce/dce_transform.h" 40 #include "dce/dce_link_encoder.h" 41 #include "dce/dce_stream_encoder.h" 42 #include "dce/dce_audio.h" 43 #include "dce/dce_opp.h" 44 #include "dce/dce_ipp.h" 45 #include "dce/dce_clocks.h" 46 #include "dce/dce_clock_source.h" 47 48 #include "dce/dce_hwseq.h" 49 #include "dce112/dce112_hw_sequencer.h" 50 #include "dce/dce_abm.h" 51 #include "dce/dce_dmcu.h" 52 #include "dce/dce_aux.h" 53 #include "dce/dce_i2c.h" 54 55 #include "reg_helper.h" 56 57 #include "dce/dce_11_2_d.h" 58 #include "dce/dce_11_2_sh_mask.h" 59 60 #include "dce100/dce100_resource.h" 61 #define DC_LOGGER \ 62 dc->ctx->logger 63 64 #ifndef mmDP_DPHY_INTERNAL_CTRL 65 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 66 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 67 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 68 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 69 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 70 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 71 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 72 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 73 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 74 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 75 #endif 76 77 #ifndef mmBIOS_SCRATCH_2 78 #define mmBIOS_SCRATCH_2 0x05CB 79 #define mmBIOS_SCRATCH_6 0x05CF 80 #endif 81 82 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 83 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 84 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 85 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 86 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 87 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 88 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 89 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 90 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 91 #endif 92 93 #ifndef mmDP_DPHY_FAST_TRAINING 94 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 95 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 96 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 97 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 98 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 99 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 100 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 101 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 102 #endif 103 104 enum dce112_clk_src_array_id { 105 DCE112_CLK_SRC_PLL0, 106 DCE112_CLK_SRC_PLL1, 107 DCE112_CLK_SRC_PLL2, 108 DCE112_CLK_SRC_PLL3, 109 DCE112_CLK_SRC_PLL4, 110 DCE112_CLK_SRC_PLL5, 111 112 DCE112_CLK_SRC_TOTAL 113 }; 114 115 static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = { 116 { 117 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 118 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 119 }, 120 { 121 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 122 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 123 }, 124 { 125 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 126 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 127 }, 128 { 129 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 130 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 131 }, 132 { 133 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 134 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 135 }, 136 { 137 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 138 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 139 } 140 }; 141 142 /* set register offset */ 143 #define SR(reg_name)\ 144 .reg_name = mm ## reg_name 145 146 /* set register offset with instance */ 147 #define SRI(reg_name, block, id)\ 148 .reg_name = mm ## block ## id ## _ ## reg_name 149 150 151 static const struct dccg_registers disp_clk_regs = { 152 CLK_COMMON_REG_LIST_DCE_BASE() 153 }; 154 155 static const struct dccg_shift disp_clk_shift = { 156 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 157 }; 158 159 static const struct dccg_mask disp_clk_mask = { 160 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 161 }; 162 163 static const struct dce_dmcu_registers dmcu_regs = { 164 DMCU_DCE110_COMMON_REG_LIST() 165 }; 166 167 static const struct dce_dmcu_shift dmcu_shift = { 168 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 169 }; 170 171 static const struct dce_dmcu_mask dmcu_mask = { 172 DMCU_MASK_SH_LIST_DCE110(_MASK) 173 }; 174 175 static const struct dce_abm_registers abm_regs = { 176 ABM_DCE110_COMMON_REG_LIST() 177 }; 178 179 static const struct dce_abm_shift abm_shift = { 180 ABM_MASK_SH_LIST_DCE110(__SHIFT) 181 }; 182 183 static const struct dce_abm_mask abm_mask = { 184 ABM_MASK_SH_LIST_DCE110(_MASK) 185 }; 186 187 #define ipp_regs(id)\ 188 [id] = {\ 189 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 190 } 191 192 static const struct dce_ipp_registers ipp_regs[] = { 193 ipp_regs(0), 194 ipp_regs(1), 195 ipp_regs(2), 196 ipp_regs(3), 197 ipp_regs(4), 198 ipp_regs(5) 199 }; 200 201 static const struct dce_ipp_shift ipp_shift = { 202 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 203 }; 204 205 static const struct dce_ipp_mask ipp_mask = { 206 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 207 }; 208 209 #define transform_regs(id)\ 210 [id] = {\ 211 XFM_COMMON_REG_LIST_DCE110(id)\ 212 } 213 214 static const struct dce_transform_registers xfm_regs[] = { 215 transform_regs(0), 216 transform_regs(1), 217 transform_regs(2), 218 transform_regs(3), 219 transform_regs(4), 220 transform_regs(5) 221 }; 222 223 static const struct dce_transform_shift xfm_shift = { 224 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 225 }; 226 227 static const struct dce_transform_mask xfm_mask = { 228 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 229 }; 230 231 #define aux_regs(id)\ 232 [id] = {\ 233 AUX_REG_LIST(id)\ 234 } 235 236 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 237 aux_regs(0), 238 aux_regs(1), 239 aux_regs(2), 240 aux_regs(3), 241 aux_regs(4), 242 aux_regs(5) 243 }; 244 245 #define hpd_regs(id)\ 246 [id] = {\ 247 HPD_REG_LIST(id)\ 248 } 249 250 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 251 hpd_regs(0), 252 hpd_regs(1), 253 hpd_regs(2), 254 hpd_regs(3), 255 hpd_regs(4), 256 hpd_regs(5) 257 }; 258 259 #define link_regs(id)\ 260 [id] = {\ 261 LE_DCE110_REG_LIST(id)\ 262 } 263 264 static const struct dce110_link_enc_registers link_enc_regs[] = { 265 link_regs(0), 266 link_regs(1), 267 link_regs(2), 268 link_regs(3), 269 link_regs(4), 270 link_regs(5), 271 link_regs(6), 272 }; 273 274 #define stream_enc_regs(id)\ 275 [id] = {\ 276 SE_COMMON_REG_LIST(id),\ 277 .TMDS_CNTL = 0,\ 278 } 279 280 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 281 stream_enc_regs(0), 282 stream_enc_regs(1), 283 stream_enc_regs(2), 284 stream_enc_regs(3), 285 stream_enc_regs(4), 286 stream_enc_regs(5) 287 }; 288 289 static const struct dce_stream_encoder_shift se_shift = { 290 SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT) 291 }; 292 293 static const struct dce_stream_encoder_mask se_mask = { 294 SE_COMMON_MASK_SH_LIST_DCE112(_MASK) 295 }; 296 297 #define opp_regs(id)\ 298 [id] = {\ 299 OPP_DCE_112_REG_LIST(id),\ 300 } 301 302 static const struct dce_opp_registers opp_regs[] = { 303 opp_regs(0), 304 opp_regs(1), 305 opp_regs(2), 306 opp_regs(3), 307 opp_regs(4), 308 opp_regs(5) 309 }; 310 311 static const struct dce_opp_shift opp_shift = { 312 OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 313 }; 314 315 static const struct dce_opp_mask opp_mask = { 316 OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK) 317 }; 318 319 #define aux_engine_regs(id)\ 320 [id] = {\ 321 AUX_COMMON_REG_LIST(id), \ 322 .AUX_RESET_MASK = 0 \ 323 } 324 325 static const struct dce110_aux_registers aux_engine_regs[] = { 326 aux_engine_regs(0), 327 aux_engine_regs(1), 328 aux_engine_regs(2), 329 aux_engine_regs(3), 330 aux_engine_regs(4), 331 aux_engine_regs(5) 332 }; 333 334 #define audio_regs(id)\ 335 [id] = {\ 336 AUD_COMMON_REG_LIST(id)\ 337 } 338 339 static const struct dce_audio_registers audio_regs[] = { 340 audio_regs(0), 341 audio_regs(1), 342 audio_regs(2), 343 audio_regs(3), 344 audio_regs(4), 345 audio_regs(5) 346 }; 347 348 static const struct dce_audio_shift audio_shift = { 349 AUD_COMMON_MASK_SH_LIST(__SHIFT) 350 }; 351 352 static const struct dce_aduio_mask audio_mask = { 353 AUD_COMMON_MASK_SH_LIST(_MASK) 354 }; 355 356 #define clk_src_regs(index, id)\ 357 [index] = {\ 358 CS_COMMON_REG_LIST_DCE_112(id),\ 359 } 360 361 static const struct dce110_clk_src_regs clk_src_regs[] = { 362 clk_src_regs(0, A), 363 clk_src_regs(1, B), 364 clk_src_regs(2, C), 365 clk_src_regs(3, D), 366 clk_src_regs(4, E), 367 clk_src_regs(5, F) 368 }; 369 370 static const struct dce110_clk_src_shift cs_shift = { 371 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 372 }; 373 374 static const struct dce110_clk_src_mask cs_mask = { 375 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) 376 }; 377 378 static const struct bios_registers bios_regs = { 379 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 380 }; 381 382 static const struct resource_caps polaris_10_resource_cap = { 383 .num_timing_generator = 6, 384 .num_audio = 6, 385 .num_stream_encoder = 6, 386 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */ 387 .num_ddc = 6, 388 }; 389 390 static const struct resource_caps polaris_11_resource_cap = { 391 .num_timing_generator = 5, 392 .num_audio = 5, 393 .num_stream_encoder = 5, 394 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */ 395 .num_ddc = 5, 396 }; 397 398 #define CTX ctx 399 #define REG(reg) mm ## reg 400 401 #ifndef mmCC_DC_HDMI_STRAPS 402 #define mmCC_DC_HDMI_STRAPS 0x4819 403 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 404 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 405 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 406 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 407 #endif 408 409 static void read_dce_straps( 410 struct dc_context *ctx, 411 struct resource_straps *straps) 412 { 413 REG_GET_2(CC_DC_HDMI_STRAPS, 414 HDMI_DISABLE, &straps->hdmi_disable, 415 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 416 417 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 418 } 419 420 static struct audio *create_audio( 421 struct dc_context *ctx, unsigned int inst) 422 { 423 return dce_audio_create(ctx, inst, 424 &audio_regs[inst], &audio_shift, &audio_mask); 425 } 426 427 428 static struct timing_generator *dce112_timing_generator_create( 429 struct dc_context *ctx, 430 uint32_t instance, 431 const struct dce110_timing_generator_offsets *offsets) 432 { 433 struct dce110_timing_generator *tg110 = 434 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 435 436 if (!tg110) 437 return NULL; 438 439 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 440 return &tg110->base; 441 } 442 443 static struct stream_encoder *dce112_stream_encoder_create( 444 enum engine_id eng_id, 445 struct dc_context *ctx) 446 { 447 struct dce110_stream_encoder *enc110 = 448 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 449 450 if (!enc110) 451 return NULL; 452 453 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 454 &stream_enc_regs[eng_id], 455 &se_shift, &se_mask); 456 return &enc110->base; 457 } 458 459 #define SRII(reg_name, block, id)\ 460 .reg_name[id] = mm ## block ## id ## _ ## reg_name 461 462 static const struct dce_hwseq_registers hwseq_reg = { 463 HWSEQ_DCE112_REG_LIST() 464 }; 465 466 static const struct dce_hwseq_shift hwseq_shift = { 467 HWSEQ_DCE112_MASK_SH_LIST(__SHIFT) 468 }; 469 470 static const struct dce_hwseq_mask hwseq_mask = { 471 HWSEQ_DCE112_MASK_SH_LIST(_MASK) 472 }; 473 474 static struct dce_hwseq *dce112_hwseq_create( 475 struct dc_context *ctx) 476 { 477 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 478 479 if (hws) { 480 hws->ctx = ctx; 481 hws->regs = &hwseq_reg; 482 hws->shifts = &hwseq_shift; 483 hws->masks = &hwseq_mask; 484 } 485 return hws; 486 } 487 488 static const struct resource_create_funcs res_create_funcs = { 489 .read_dce_straps = read_dce_straps, 490 .create_audio = create_audio, 491 .create_stream_encoder = dce112_stream_encoder_create, 492 .create_hwseq = dce112_hwseq_create, 493 }; 494 495 #define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) } 496 static const struct dce_mem_input_registers mi_regs[] = { 497 mi_inst_regs(0), 498 mi_inst_regs(1), 499 mi_inst_regs(2), 500 mi_inst_regs(3), 501 mi_inst_regs(4), 502 mi_inst_regs(5), 503 }; 504 505 static const struct dce_mem_input_shift mi_shifts = { 506 MI_DCE11_2_MASK_SH_LIST(__SHIFT) 507 }; 508 509 static const struct dce_mem_input_mask mi_masks = { 510 MI_DCE11_2_MASK_SH_LIST(_MASK) 511 }; 512 513 static struct mem_input *dce112_mem_input_create( 514 struct dc_context *ctx, 515 uint32_t inst) 516 { 517 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 518 GFP_KERNEL); 519 520 if (!dce_mi) { 521 BREAK_TO_DEBUGGER(); 522 return NULL; 523 } 524 525 dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 526 return &dce_mi->base; 527 } 528 529 static void dce112_transform_destroy(struct transform **xfm) 530 { 531 kfree(TO_DCE_TRANSFORM(*xfm)); 532 *xfm = NULL; 533 } 534 535 static struct transform *dce112_transform_create( 536 struct dc_context *ctx, 537 uint32_t inst) 538 { 539 struct dce_transform *transform = 540 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 541 542 if (!transform) 543 return NULL; 544 545 dce_transform_construct(transform, ctx, inst, 546 &xfm_regs[inst], &xfm_shift, &xfm_mask); 547 transform->lb_memory_size = 0x1404; /*5124*/ 548 return &transform->base; 549 } 550 551 static const struct encoder_feature_support link_enc_feature = { 552 .max_hdmi_deep_color = COLOR_DEPTH_121212, 553 .max_hdmi_pixel_clock = 600000, 554 .ycbcr420_supported = true, 555 .flags.bits.IS_HBR2_CAPABLE = true, 556 .flags.bits.IS_HBR3_CAPABLE = true, 557 .flags.bits.IS_TPS3_CAPABLE = true, 558 .flags.bits.IS_TPS4_CAPABLE = true 559 }; 560 561 struct link_encoder *dce112_link_encoder_create( 562 const struct encoder_init_data *enc_init_data) 563 { 564 struct dce110_link_encoder *enc110 = 565 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 566 567 if (!enc110) 568 return NULL; 569 570 dce110_link_encoder_construct(enc110, 571 enc_init_data, 572 &link_enc_feature, 573 &link_enc_regs[enc_init_data->transmitter], 574 &link_enc_aux_regs[enc_init_data->channel - 1], 575 &link_enc_hpd_regs[enc_init_data->hpd_source]); 576 return &enc110->base; 577 } 578 579 static struct input_pixel_processor *dce112_ipp_create( 580 struct dc_context *ctx, uint32_t inst) 581 { 582 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 583 584 if (!ipp) { 585 BREAK_TO_DEBUGGER(); 586 return NULL; 587 } 588 589 dce_ipp_construct(ipp, ctx, inst, 590 &ipp_regs[inst], &ipp_shift, &ipp_mask); 591 return &ipp->base; 592 } 593 594 struct output_pixel_processor *dce112_opp_create( 595 struct dc_context *ctx, 596 uint32_t inst) 597 { 598 struct dce110_opp *opp = 599 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 600 601 if (!opp) 602 return NULL; 603 604 dce110_opp_construct(opp, 605 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 606 return &opp->base; 607 } 608 609 struct aux_engine *dce112_aux_engine_create( 610 struct dc_context *ctx, 611 uint32_t inst) 612 { 613 struct aux_engine_dce110 *aux_engine = 614 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 615 616 if (!aux_engine) 617 return NULL; 618 619 dce110_aux_engine_construct(aux_engine, ctx, inst, 620 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 621 &aux_engine_regs[inst]); 622 623 return &aux_engine->base; 624 } 625 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 626 627 static const struct dce_i2c_registers i2c_hw_regs[] = { 628 i2c_inst_regs(1), 629 i2c_inst_regs(2), 630 i2c_inst_regs(3), 631 i2c_inst_regs(4), 632 i2c_inst_regs(5), 633 i2c_inst_regs(6), 634 }; 635 636 static const struct dce_i2c_shift i2c_shifts = { 637 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 638 }; 639 640 static const struct dce_i2c_mask i2c_masks = { 641 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 642 }; 643 644 struct dce_i2c_hw *dce112_i2c_hw_create( 645 struct dc_context *ctx, 646 uint32_t inst) 647 { 648 struct dce_i2c_hw *dce_i2c_hw = 649 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 650 651 if (!dce_i2c_hw) 652 return NULL; 653 654 dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst, 655 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 656 657 return dce_i2c_hw; 658 } 659 struct clock_source *dce112_clock_source_create( 660 struct dc_context *ctx, 661 struct dc_bios *bios, 662 enum clock_source_id id, 663 const struct dce110_clk_src_regs *regs, 664 bool dp_clk_src) 665 { 666 struct dce110_clk_src *clk_src = 667 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 668 669 if (!clk_src) 670 return NULL; 671 672 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 673 regs, &cs_shift, &cs_mask)) { 674 clk_src->base.dp_clk_src = dp_clk_src; 675 return &clk_src->base; 676 } 677 678 BREAK_TO_DEBUGGER(); 679 return NULL; 680 } 681 682 void dce112_clock_source_destroy(struct clock_source **clk_src) 683 { 684 kfree(TO_DCE110_CLK_SRC(*clk_src)); 685 *clk_src = NULL; 686 } 687 688 static void destruct(struct dce110_resource_pool *pool) 689 { 690 unsigned int i; 691 692 for (i = 0; i < pool->base.pipe_count; i++) { 693 if (pool->base.opps[i] != NULL) 694 dce110_opp_destroy(&pool->base.opps[i]); 695 696 if (pool->base.transforms[i] != NULL) 697 dce112_transform_destroy(&pool->base.transforms[i]); 698 699 if (pool->base.ipps[i] != NULL) 700 dce_ipp_destroy(&pool->base.ipps[i]); 701 702 if (pool->base.mis[i] != NULL) { 703 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 704 pool->base.mis[i] = NULL; 705 } 706 707 if (pool->base.timing_generators[i] != NULL) { 708 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 709 pool->base.timing_generators[i] = NULL; 710 } 711 } 712 713 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 714 if (pool->base.engines[i] != NULL) 715 dce110_engine_destroy(&pool->base.engines[i]); 716 if (pool->base.hw_i2cs[i] != NULL) { 717 kfree(pool->base.hw_i2cs[i]); 718 pool->base.hw_i2cs[i] = NULL; 719 } 720 if (pool->base.sw_i2cs[i] != NULL) { 721 kfree(pool->base.sw_i2cs[i]); 722 pool->base.sw_i2cs[i] = NULL; 723 } 724 } 725 726 for (i = 0; i < pool->base.stream_enc_count; i++) { 727 if (pool->base.stream_enc[i] != NULL) 728 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 729 } 730 731 for (i = 0; i < pool->base.clk_src_count; i++) { 732 if (pool->base.clock_sources[i] != NULL) { 733 dce112_clock_source_destroy(&pool->base.clock_sources[i]); 734 } 735 } 736 737 if (pool->base.dp_clock_source != NULL) 738 dce112_clock_source_destroy(&pool->base.dp_clock_source); 739 740 for (i = 0; i < pool->base.audio_count; i++) { 741 if (pool->base.audios[i] != NULL) { 742 dce_aud_destroy(&pool->base.audios[i]); 743 } 744 } 745 746 if (pool->base.abm != NULL) 747 dce_abm_destroy(&pool->base.abm); 748 749 if (pool->base.dmcu != NULL) 750 dce_dmcu_destroy(&pool->base.dmcu); 751 752 if (pool->base.dccg != NULL) 753 dce_dccg_destroy(&pool->base.dccg); 754 755 if (pool->base.irqs != NULL) { 756 dal_irq_service_destroy(&pool->base.irqs); 757 } 758 } 759 760 static struct clock_source *find_matching_pll( 761 struct resource_context *res_ctx, 762 const struct resource_pool *pool, 763 const struct dc_stream_state *const stream) 764 { 765 switch (stream->sink->link->link_enc->transmitter) { 766 case TRANSMITTER_UNIPHY_A: 767 return pool->clock_sources[DCE112_CLK_SRC_PLL0]; 768 case TRANSMITTER_UNIPHY_B: 769 return pool->clock_sources[DCE112_CLK_SRC_PLL1]; 770 case TRANSMITTER_UNIPHY_C: 771 return pool->clock_sources[DCE112_CLK_SRC_PLL2]; 772 case TRANSMITTER_UNIPHY_D: 773 return pool->clock_sources[DCE112_CLK_SRC_PLL3]; 774 case TRANSMITTER_UNIPHY_E: 775 return pool->clock_sources[DCE112_CLK_SRC_PLL4]; 776 case TRANSMITTER_UNIPHY_F: 777 return pool->clock_sources[DCE112_CLK_SRC_PLL5]; 778 default: 779 return NULL; 780 }; 781 782 return 0; 783 } 784 785 static enum dc_status build_mapped_resource( 786 const struct dc *dc, 787 struct dc_state *context, 788 struct dc_stream_state *stream) 789 { 790 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 791 792 if (!pipe_ctx) 793 return DC_ERROR_UNEXPECTED; 794 795 dce110_resource_build_pipe_hw_param(pipe_ctx); 796 797 resource_build_info_frame(pipe_ctx); 798 799 return DC_OK; 800 } 801 802 bool dce112_validate_bandwidth( 803 struct dc *dc, 804 struct dc_state *context) 805 { 806 bool result = false; 807 808 DC_LOG_BANDWIDTH_CALCS( 809 "%s: start", 810 __func__); 811 812 if (bw_calcs( 813 dc->ctx, 814 dc->bw_dceip, 815 dc->bw_vbios, 816 context->res_ctx.pipe_ctx, 817 dc->res_pool->pipe_count, 818 &context->bw.dce)) 819 result = true; 820 821 if (!result) 822 DC_LOG_BANDWIDTH_VALIDATION( 823 "%s: Bandwidth validation failed!", 824 __func__); 825 826 if (memcmp(&dc->current_state->bw.dce, 827 &context->bw.dce, sizeof(context->bw.dce))) { 828 829 DC_LOG_BANDWIDTH_CALCS( 830 "%s: finish,\n" 831 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 832 "stutMark_b: %d stutMark_a: %d\n" 833 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 834 "stutMark_b: %d stutMark_a: %d\n" 835 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 836 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n" 837 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" 838 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n" 839 , 840 __func__, 841 context->bw.dce.nbp_state_change_wm_ns[0].b_mark, 842 context->bw.dce.nbp_state_change_wm_ns[0].a_mark, 843 context->bw.dce.urgent_wm_ns[0].b_mark, 844 context->bw.dce.urgent_wm_ns[0].a_mark, 845 context->bw.dce.stutter_exit_wm_ns[0].b_mark, 846 context->bw.dce.stutter_exit_wm_ns[0].a_mark, 847 context->bw.dce.nbp_state_change_wm_ns[1].b_mark, 848 context->bw.dce.nbp_state_change_wm_ns[1].a_mark, 849 context->bw.dce.urgent_wm_ns[1].b_mark, 850 context->bw.dce.urgent_wm_ns[1].a_mark, 851 context->bw.dce.stutter_exit_wm_ns[1].b_mark, 852 context->bw.dce.stutter_exit_wm_ns[1].a_mark, 853 context->bw.dce.nbp_state_change_wm_ns[2].b_mark, 854 context->bw.dce.nbp_state_change_wm_ns[2].a_mark, 855 context->bw.dce.urgent_wm_ns[2].b_mark, 856 context->bw.dce.urgent_wm_ns[2].a_mark, 857 context->bw.dce.stutter_exit_wm_ns[2].b_mark, 858 context->bw.dce.stutter_exit_wm_ns[2].a_mark, 859 context->bw.dce.stutter_mode_enable, 860 context->bw.dce.cpuc_state_change_enable, 861 context->bw.dce.cpup_state_change_enable, 862 context->bw.dce.nbp_state_change_enable, 863 context->bw.dce.all_displays_in_sync, 864 context->bw.dce.dispclk_khz, 865 context->bw.dce.sclk_khz, 866 context->bw.dce.sclk_deep_sleep_khz, 867 context->bw.dce.yclk_khz, 868 context->bw.dce.blackout_recovery_time_us); 869 } 870 return result; 871 } 872 873 enum dc_status resource_map_phy_clock_resources( 874 const struct dc *dc, 875 struct dc_state *context, 876 struct dc_stream_state *stream) 877 { 878 879 /* acquire new resources */ 880 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( 881 &context->res_ctx, stream); 882 883 if (!pipe_ctx) 884 return DC_ERROR_UNEXPECTED; 885 886 if (dc_is_dp_signal(pipe_ctx->stream->signal) 887 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) 888 pipe_ctx->clock_source = 889 dc->res_pool->dp_clock_source; 890 else 891 pipe_ctx->clock_source = find_matching_pll( 892 &context->res_ctx, dc->res_pool, 893 stream); 894 895 if (pipe_ctx->clock_source == NULL) 896 return DC_NO_CLOCK_SOURCE_RESOURCE; 897 898 resource_reference_clock_source( 899 &context->res_ctx, 900 dc->res_pool, 901 pipe_ctx->clock_source); 902 903 return DC_OK; 904 } 905 906 static bool dce112_validate_surface_sets( 907 struct dc_state *context) 908 { 909 int i; 910 911 for (i = 0; i < context->stream_count; i++) { 912 if (context->stream_status[i].plane_count == 0) 913 continue; 914 915 if (context->stream_status[i].plane_count > 1) 916 return false; 917 918 if (context->stream_status[i].plane_states[0]->format 919 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 920 return false; 921 } 922 923 return true; 924 } 925 926 enum dc_status dce112_add_stream_to_ctx( 927 struct dc *dc, 928 struct dc_state *new_ctx, 929 struct dc_stream_state *dc_stream) 930 { 931 enum dc_status result = DC_ERROR_UNEXPECTED; 932 933 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 934 935 if (result == DC_OK) 936 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 937 938 939 if (result == DC_OK) 940 result = build_mapped_resource(dc, new_ctx, dc_stream); 941 942 return result; 943 } 944 945 enum dc_status dce112_validate_global( 946 struct dc *dc, 947 struct dc_state *context) 948 { 949 if (!dce112_validate_surface_sets(context)) 950 return DC_FAIL_SURFACE_VALIDATE; 951 952 return DC_OK; 953 } 954 955 static void dce112_destroy_resource_pool(struct resource_pool **pool) 956 { 957 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 958 959 destruct(dce110_pool); 960 kfree(dce110_pool); 961 *pool = NULL; 962 } 963 964 static const struct resource_funcs dce112_res_pool_funcs = { 965 .destroy = dce112_destroy_resource_pool, 966 .link_enc_create = dce112_link_encoder_create, 967 .validate_bandwidth = dce112_validate_bandwidth, 968 .validate_plane = dce100_validate_plane, 969 .add_stream_to_ctx = dce112_add_stream_to_ctx, 970 .validate_global = dce112_validate_global 971 }; 972 973 static void bw_calcs_data_update_from_pplib(struct dc *dc) 974 { 975 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 976 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 977 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; 978 struct dm_pp_clock_levels clks = {0}; 979 980 /*do system clock TODO PPLIB: after PPLIB implement, 981 * then remove old way 982 */ 983 if (!dm_pp_get_clock_levels_by_type_with_latency( 984 dc->ctx, 985 DM_PP_CLOCK_TYPE_ENGINE_CLK, 986 &eng_clks)) { 987 988 /* This is only for temporary */ 989 dm_pp_get_clock_levels_by_type( 990 dc->ctx, 991 DM_PP_CLOCK_TYPE_ENGINE_CLK, 992 &clks); 993 /* convert all the clock fro kHz to fix point mHz */ 994 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 995 clks.clocks_in_khz[clks.num_levels-1], 1000); 996 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 997 clks.clocks_in_khz[clks.num_levels/8], 1000); 998 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 999 clks.clocks_in_khz[clks.num_levels*2/8], 1000); 1000 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 1001 clks.clocks_in_khz[clks.num_levels*3/8], 1000); 1002 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 1003 clks.clocks_in_khz[clks.num_levels*4/8], 1000); 1004 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 1005 clks.clocks_in_khz[clks.num_levels*5/8], 1000); 1006 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1007 clks.clocks_in_khz[clks.num_levels*6/8], 1000); 1008 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1009 clks.clocks_in_khz[0], 1000); 1010 1011 /*do memory clock*/ 1012 dm_pp_get_clock_levels_by_type( 1013 dc->ctx, 1014 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1015 &clks); 1016 1017 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1018 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000); 1019 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1020 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER, 1021 1000); 1022 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1023 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER, 1024 1000); 1025 1026 return; 1027 } 1028 1029 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ 1030 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 1031 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); 1032 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 1033 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); 1034 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 1035 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); 1036 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 1037 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); 1038 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 1039 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); 1040 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 1041 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); 1042 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1043 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); 1044 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1045 eng_clks.data[0].clocks_in_khz, 1000); 1046 1047 /*do memory clock*/ 1048 dm_pp_get_clock_levels_by_type_with_latency( 1049 dc->ctx, 1050 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1051 &mem_clks); 1052 1053 /* we don't need to call PPLIB for validation clock since they 1054 * also give us the highest sclk and highest mclk (UMA clock). 1055 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): 1056 * YCLK = UMACLK*m_memoryTypeMultiplier 1057 */ 1058 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1059 mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000); 1060 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1061 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1062 1000); 1063 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1064 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1065 1000); 1066 1067 /* Now notify PPLib/SMU about which Watermarks sets they should select 1068 * depending on DPM state they are in. And update BW MGR GFX Engine and 1069 * Memory clock member variables for Watermarks calculations for each 1070 * Watermark Set 1071 */ 1072 clk_ranges.num_wm_sets = 4; 1073 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; 1074 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = 1075 eng_clks.data[0].clocks_in_khz; 1076 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = 1077 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 1078 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz = 1079 mem_clks.data[0].clocks_in_khz; 1080 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = 1081 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 1082 1083 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; 1084 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = 1085 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 1086 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 1087 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; 1088 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz = 1089 mem_clks.data[0].clocks_in_khz; 1090 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = 1091 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 1092 1093 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; 1094 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = 1095 eng_clks.data[0].clocks_in_khz; 1096 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = 1097 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 1098 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz = 1099 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 1100 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 1101 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; 1102 1103 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; 1104 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = 1105 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 1106 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 1107 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; 1108 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz = 1109 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 1110 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 1111 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; 1112 1113 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 1114 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); 1115 } 1116 1117 const struct resource_caps *dce112_resource_cap( 1118 struct hw_asic_id *asic_id) 1119 { 1120 if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) || 1121 ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev)) 1122 return &polaris_11_resource_cap; 1123 else 1124 return &polaris_10_resource_cap; 1125 } 1126 1127 static bool construct( 1128 uint8_t num_virtual_links, 1129 struct dc *dc, 1130 struct dce110_resource_pool *pool) 1131 { 1132 unsigned int i; 1133 struct dc_context *ctx = dc->ctx; 1134 struct dm_pp_static_clock_info static_clk_info = {0}; 1135 1136 ctx->dc_bios->regs = &bios_regs; 1137 1138 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id); 1139 pool->base.funcs = &dce112_res_pool_funcs; 1140 1141 /************************************************* 1142 * Resource + asic cap harcoding * 1143 *************************************************/ 1144 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1145 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1146 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1147 dc->caps.max_downscale_ratio = 200; 1148 dc->caps.i2c_speed_in_khz = 100; 1149 dc->caps.max_cursor_size = 128; 1150 dc->caps.dual_link_dvi = true; 1151 1152 1153 /************************************************* 1154 * Create resources * 1155 *************************************************/ 1156 1157 pool->base.clock_sources[DCE112_CLK_SRC_PLL0] = 1158 dce112_clock_source_create( 1159 ctx, ctx->dc_bios, 1160 CLOCK_SOURCE_COMBO_PHY_PLL0, 1161 &clk_src_regs[0], false); 1162 pool->base.clock_sources[DCE112_CLK_SRC_PLL1] = 1163 dce112_clock_source_create( 1164 ctx, ctx->dc_bios, 1165 CLOCK_SOURCE_COMBO_PHY_PLL1, 1166 &clk_src_regs[1], false); 1167 pool->base.clock_sources[DCE112_CLK_SRC_PLL2] = 1168 dce112_clock_source_create( 1169 ctx, ctx->dc_bios, 1170 CLOCK_SOURCE_COMBO_PHY_PLL2, 1171 &clk_src_regs[2], false); 1172 pool->base.clock_sources[DCE112_CLK_SRC_PLL3] = 1173 dce112_clock_source_create( 1174 ctx, ctx->dc_bios, 1175 CLOCK_SOURCE_COMBO_PHY_PLL3, 1176 &clk_src_regs[3], false); 1177 pool->base.clock_sources[DCE112_CLK_SRC_PLL4] = 1178 dce112_clock_source_create( 1179 ctx, ctx->dc_bios, 1180 CLOCK_SOURCE_COMBO_PHY_PLL4, 1181 &clk_src_regs[4], false); 1182 pool->base.clock_sources[DCE112_CLK_SRC_PLL5] = 1183 dce112_clock_source_create( 1184 ctx, ctx->dc_bios, 1185 CLOCK_SOURCE_COMBO_PHY_PLL5, 1186 &clk_src_regs[5], false); 1187 pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL; 1188 1189 pool->base.dp_clock_source = dce112_clock_source_create( 1190 ctx, ctx->dc_bios, 1191 CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); 1192 1193 1194 for (i = 0; i < pool->base.clk_src_count; i++) { 1195 if (pool->base.clock_sources[i] == NULL) { 1196 dm_error("DC: failed to create clock sources!\n"); 1197 BREAK_TO_DEBUGGER(); 1198 goto res_create_fail; 1199 } 1200 } 1201 1202 pool->base.dccg = dce112_dccg_create(ctx, 1203 &disp_clk_regs, 1204 &disp_clk_shift, 1205 &disp_clk_mask); 1206 if (pool->base.dccg == NULL) { 1207 dm_error("DC: failed to create display clock!\n"); 1208 BREAK_TO_DEBUGGER(); 1209 goto res_create_fail; 1210 } 1211 1212 pool->base.dmcu = dce_dmcu_create(ctx, 1213 &dmcu_regs, 1214 &dmcu_shift, 1215 &dmcu_mask); 1216 if (pool->base.dmcu == NULL) { 1217 dm_error("DC: failed to create dmcu!\n"); 1218 BREAK_TO_DEBUGGER(); 1219 goto res_create_fail; 1220 } 1221 1222 pool->base.abm = dce_abm_create(ctx, 1223 &abm_regs, 1224 &abm_shift, 1225 &abm_mask); 1226 if (pool->base.abm == NULL) { 1227 dm_error("DC: failed to create abm!\n"); 1228 BREAK_TO_DEBUGGER(); 1229 goto res_create_fail; 1230 } 1231 1232 /* get static clock information for PPLIB or firmware, save 1233 * max_clock_state 1234 */ 1235 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 1236 pool->base.dccg->max_clks_state = 1237 static_clk_info.max_clocks_state; 1238 1239 { 1240 struct irq_service_init_data init_data; 1241 init_data.ctx = dc->ctx; 1242 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 1243 if (!pool->base.irqs) 1244 goto res_create_fail; 1245 } 1246 1247 for (i = 0; i < pool->base.pipe_count; i++) { 1248 pool->base.timing_generators[i] = 1249 dce112_timing_generator_create( 1250 ctx, 1251 i, 1252 &dce112_tg_offsets[i]); 1253 if (pool->base.timing_generators[i] == NULL) { 1254 BREAK_TO_DEBUGGER(); 1255 dm_error("DC: failed to create tg!\n"); 1256 goto res_create_fail; 1257 } 1258 1259 pool->base.mis[i] = dce112_mem_input_create(ctx, i); 1260 if (pool->base.mis[i] == NULL) { 1261 BREAK_TO_DEBUGGER(); 1262 dm_error( 1263 "DC: failed to create memory input!\n"); 1264 goto res_create_fail; 1265 } 1266 1267 pool->base.ipps[i] = dce112_ipp_create(ctx, i); 1268 if (pool->base.ipps[i] == NULL) { 1269 BREAK_TO_DEBUGGER(); 1270 dm_error( 1271 "DC:failed to create input pixel processor!\n"); 1272 goto res_create_fail; 1273 } 1274 1275 pool->base.transforms[i] = dce112_transform_create(ctx, i); 1276 if (pool->base.transforms[i] == NULL) { 1277 BREAK_TO_DEBUGGER(); 1278 dm_error( 1279 "DC: failed to create transform!\n"); 1280 goto res_create_fail; 1281 } 1282 1283 pool->base.opps[i] = dce112_opp_create( 1284 ctx, 1285 i); 1286 if (pool->base.opps[i] == NULL) { 1287 BREAK_TO_DEBUGGER(); 1288 dm_error( 1289 "DC:failed to create output pixel processor!\n"); 1290 goto res_create_fail; 1291 } 1292 } 1293 1294 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1295 pool->base.engines[i] = dce112_aux_engine_create(ctx, i); 1296 if (pool->base.engines[i] == NULL) { 1297 BREAK_TO_DEBUGGER(); 1298 dm_error( 1299 "DC:failed to create aux engine!!\n"); 1300 goto res_create_fail; 1301 } 1302 pool->base.hw_i2cs[i] = dce112_i2c_hw_create(ctx, i); 1303 if (pool->base.hw_i2cs[i] == NULL) { 1304 BREAK_TO_DEBUGGER(); 1305 dm_error( 1306 "DC:failed to create i2c engine!!\n"); 1307 goto res_create_fail; 1308 } 1309 pool->base.sw_i2cs[i] = NULL; 1310 } 1311 1312 if (!resource_construct(num_virtual_links, dc, &pool->base, 1313 &res_create_funcs)) 1314 goto res_create_fail; 1315 1316 dc->caps.max_planes = pool->base.pipe_count; 1317 1318 /* Create hardware sequencer */ 1319 dce112_hw_sequencer_construct(dc); 1320 1321 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1322 1323 bw_calcs_data_update_from_pplib(dc); 1324 1325 return true; 1326 1327 res_create_fail: 1328 destruct(pool); 1329 return false; 1330 } 1331 1332 struct resource_pool *dce112_create_resource_pool( 1333 uint8_t num_virtual_links, 1334 struct dc *dc) 1335 { 1336 struct dce110_resource_pool *pool = 1337 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1338 1339 if (!pool) 1340 return NULL; 1341 1342 if (construct(num_virtual_links, dc, pool)) 1343 return &pool->base; 1344 1345 BREAK_TO_DEBUGGER(); 1346 return NULL; 1347 } 1348