1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/delay.h> 27 28 #include "dm_services.h" 29 30 #include "dce/dce_11_2_d.h" 31 #include "dce/dce_11_2_sh_mask.h" 32 #include "gmc/gmc_8_1_sh_mask.h" 33 #include "gmc/gmc_8_1_d.h" 34 35 #include "include/logger_interface.h" 36 37 #include "dce112_compressor.h" 38 #define DC_LOGGER \ 39 cp110->base.ctx->logger 40 #define DCP_REG(reg)\ 41 (reg + cp110->offsets.dcp_offset) 42 #define DMIF_REG(reg)\ 43 (reg + cp110->offsets.dmif_offset) 44 45 static const struct dce112_compressor_reg_offsets reg_offsets[] = { 46 { 47 .dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 48 .dmif_offset = 49 (mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 50 - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL), 51 }, 52 { 53 .dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 54 .dmif_offset = 55 (mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 56 - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL), 57 }, 58 { 59 .dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 60 .dmif_offset = 61 (mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 62 - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL), 63 } 64 }; 65 66 static const uint32_t dce11_one_lpt_channel_max_resolution = 2560 * 1600; 67 68 enum fbc_idle_force { 69 /* Bit 0 - Display registers updated */ 70 FBC_IDLE_FORCE_DISPLAY_REGISTER_UPDATE = 0x00000001, 71 72 /* Bit 2 - FBC_GRPH_COMP_EN register updated */ 73 FBC_IDLE_FORCE_GRPH_COMP_EN = 0x00000002, 74 /* Bit 3 - FBC_SRC_SEL register updated */ 75 FBC_IDLE_FORCE_SRC_SEL_CHANGE = 0x00000004, 76 /* Bit 4 - FBC_MIN_COMPRESSION register updated */ 77 FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE = 0x00000008, 78 /* Bit 5 - FBC_ALPHA_COMP_EN register updated */ 79 FBC_IDLE_FORCE_ALPHA_COMP_EN = 0x00000010, 80 /* Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated */ 81 FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN = 0x00000020, 82 /* Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated */ 83 FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF = 0x00000040, 84 85 /* Bit 24 - Memory write to region 0 defined by MC registers. */ 86 FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION0 = 0x01000000, 87 /* Bit 25 - Memory write to region 1 defined by MC registers */ 88 FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION1 = 0x02000000, 89 /* Bit 26 - Memory write to region 2 defined by MC registers */ 90 FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION2 = 0x04000000, 91 /* Bit 27 - Memory write to region 3 defined by MC registers. */ 92 FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION3 = 0x08000000, 93 94 /* Bit 28 - Memory write from any client other than MCIF */ 95 FBC_IDLE_FORCE_MEMORY_WRITE_OTHER_THAN_MCIF = 0x10000000, 96 /* Bit 29 - CG statics screen signal is inactive */ 97 FBC_IDLE_FORCE_CG_STATIC_SCREEN_IS_INACTIVE = 0x20000000, 98 }; 99 100 static uint32_t lpt_size_alignment(struct dce112_compressor *cp110) 101 { 102 /*LPT_ALIGNMENT (in bytes) = ROW_SIZE * #BANKS * # DRAM CHANNELS. */ 103 return cp110->base.raw_size * cp110->base.banks_num * 104 cp110->base.dram_channels_num; 105 } 106 107 static uint32_t lpt_memory_control_config(struct dce112_compressor *cp110, 108 uint32_t lpt_control) 109 { 110 /*LPT MC Config */ 111 if (cp110->base.options.bits.LPT_MC_CONFIG == 1) { 112 /* POSSIBLE VALUES for LPT NUM_PIPES (DRAM CHANNELS): 113 * 00 - 1 CHANNEL 114 * 01 - 2 CHANNELS 115 * 02 - 4 OR 6 CHANNELS 116 * (Only for discrete GPU, N/A for CZ) 117 * 03 - 8 OR 12 CHANNELS 118 * (Only for discrete GPU, N/A for CZ) */ 119 switch (cp110->base.dram_channels_num) { 120 case 2: 121 set_reg_field_value( 122 lpt_control, 123 1, 124 LOW_POWER_TILING_CONTROL, 125 LOW_POWER_TILING_NUM_PIPES); 126 break; 127 case 1: 128 set_reg_field_value( 129 lpt_control, 130 0, 131 LOW_POWER_TILING_CONTROL, 132 LOW_POWER_TILING_NUM_PIPES); 133 break; 134 default: 135 DC_LOG_WARNING( 136 "%s: Invalid LPT NUM_PIPES!!!", 137 __func__); 138 break; 139 } 140 141 /* The mapping for LPT NUM_BANKS is in 142 * GRPH_CONTROL.GRPH_NUM_BANKS register field 143 * Specifies the number of memory banks for tiling 144 * purposes. Only applies to 2D and 3D tiling modes. 145 * POSSIBLE VALUES: 146 * 00 - DCP_GRPH_NUM_BANKS_2BANK: ADDR_SURF_2_BANK 147 * 01 - DCP_GRPH_NUM_BANKS_4BANK: ADDR_SURF_4_BANK 148 * 02 - DCP_GRPH_NUM_BANKS_8BANK: ADDR_SURF_8_BANK 149 * 03 - DCP_GRPH_NUM_BANKS_16BANK: ADDR_SURF_16_BANK */ 150 switch (cp110->base.banks_num) { 151 case 16: 152 set_reg_field_value( 153 lpt_control, 154 3, 155 LOW_POWER_TILING_CONTROL, 156 LOW_POWER_TILING_NUM_BANKS); 157 break; 158 case 8: 159 set_reg_field_value( 160 lpt_control, 161 2, 162 LOW_POWER_TILING_CONTROL, 163 LOW_POWER_TILING_NUM_BANKS); 164 break; 165 case 4: 166 set_reg_field_value( 167 lpt_control, 168 1, 169 LOW_POWER_TILING_CONTROL, 170 LOW_POWER_TILING_NUM_BANKS); 171 break; 172 case 2: 173 set_reg_field_value( 174 lpt_control, 175 0, 176 LOW_POWER_TILING_CONTROL, 177 LOW_POWER_TILING_NUM_BANKS); 178 break; 179 default: 180 DC_LOG_WARNING( 181 "%s: Invalid LPT NUM_BANKS!!!", 182 __func__); 183 break; 184 } 185 186 /* The mapping is in DMIF_ADDR_CALC. 187 * ADDR_CONFIG_PIPE_INTERLEAVE_SIZE register field for 188 * Carrizo specifies the memory interleave per pipe. 189 * It effectively specifies the location of pipe bits in 190 * the memory address. 191 * POSSIBLE VALUES: 192 * 00 - ADDR_CONFIG_PIPE_INTERLEAVE_256B: 256 byte 193 * interleave 194 * 01 - ADDR_CONFIG_PIPE_INTERLEAVE_512B: 512 byte 195 * interleave 196 */ 197 switch (cp110->base.channel_interleave_size) { 198 case 256: /*256B */ 199 set_reg_field_value( 200 lpt_control, 201 0, 202 LOW_POWER_TILING_CONTROL, 203 LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE); 204 break; 205 case 512: /*512B */ 206 set_reg_field_value( 207 lpt_control, 208 1, 209 LOW_POWER_TILING_CONTROL, 210 LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE); 211 break; 212 default: 213 DC_LOG_WARNING( 214 "%s: Invalid LPT INTERLEAVE_SIZE!!!", 215 __func__); 216 break; 217 } 218 219 /* The mapping for LOW_POWER_TILING_ROW_SIZE is in 220 * DMIF_ADDR_CALC.ADDR_CONFIG_ROW_SIZE register field 221 * for Carrizo. Specifies the size of dram row in bytes. 222 * This should match up with NOOFCOLS field in 223 * MC_ARB_RAMCFG (ROW_SIZE = 4 * 2 ^^ columns). 224 * This register DMIF_ADDR_CALC is not used by the 225 * hardware as it is only used for addrlib assertions. 226 * POSSIBLE VALUES: 227 * 00 - ADDR_CONFIG_1KB_ROW: Treat 1KB as DRAM row 228 * boundary 229 * 01 - ADDR_CONFIG_2KB_ROW: Treat 2KB as DRAM row 230 * boundary 231 * 02 - ADDR_CONFIG_4KB_ROW: Treat 4KB as DRAM row 232 * boundary */ 233 switch (cp110->base.raw_size) { 234 case 4096: /*4 KB */ 235 set_reg_field_value( 236 lpt_control, 237 2, 238 LOW_POWER_TILING_CONTROL, 239 LOW_POWER_TILING_ROW_SIZE); 240 break; 241 case 2048: 242 set_reg_field_value( 243 lpt_control, 244 1, 245 LOW_POWER_TILING_CONTROL, 246 LOW_POWER_TILING_ROW_SIZE); 247 break; 248 case 1024: 249 set_reg_field_value( 250 lpt_control, 251 0, 252 LOW_POWER_TILING_CONTROL, 253 LOW_POWER_TILING_ROW_SIZE); 254 break; 255 default: 256 DC_LOG_WARNING( 257 "%s: Invalid LPT ROW_SIZE!!!", 258 __func__); 259 break; 260 } 261 } else { 262 DC_LOG_WARNING( 263 "%s: LPT MC Configuration is not provided", 264 __func__); 265 } 266 267 return lpt_control; 268 } 269 270 static bool is_source_bigger_than_epanel_size( 271 struct dce112_compressor *cp110, 272 uint32_t source_view_width, 273 uint32_t source_view_height) 274 { 275 if (cp110->base.embedded_panel_h_size != 0 && 276 cp110->base.embedded_panel_v_size != 0 && 277 ((source_view_width * source_view_height) > 278 (cp110->base.embedded_panel_h_size * 279 cp110->base.embedded_panel_v_size))) 280 return true; 281 282 return false; 283 } 284 285 static uint32_t align_to_chunks_number_per_line( 286 struct dce112_compressor *cp110, 287 uint32_t pixels) 288 { 289 return 256 * ((pixels + 255) / 256); 290 } 291 292 static void wait_for_fbc_state_changed( 293 struct dce112_compressor *cp110, 294 bool enabled) 295 { 296 uint8_t counter = 0; 297 uint32_t addr = mmFBC_STATUS; 298 uint32_t value; 299 300 while (counter < 10) { 301 value = dm_read_reg(cp110->base.ctx, addr); 302 if (get_reg_field_value( 303 value, 304 FBC_STATUS, 305 FBC_ENABLE_STATUS) == enabled) 306 break; 307 udelay(10); 308 counter++; 309 } 310 311 if (counter == 10) { 312 DC_LOG_WARNING( 313 "%s: wait counter exceeded, changes to HW not applied", 314 __func__); 315 } 316 } 317 318 void dce112_compressor_power_up_fbc(struct compressor *compressor) 319 { 320 uint32_t value; 321 uint32_t addr; 322 323 addr = mmFBC_CNTL; 324 value = dm_read_reg(compressor->ctx, addr); 325 set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN); 326 set_reg_field_value(value, 1, FBC_CNTL, FBC_EN); 327 set_reg_field_value(value, 2, FBC_CNTL, FBC_COHERENCY_MODE); 328 if (compressor->options.bits.CLK_GATING_DISABLED == 1) { 329 /* HW needs to do power measurement comparison. */ 330 set_reg_field_value( 331 value, 332 0, 333 FBC_CNTL, 334 FBC_COMP_CLK_GATE_EN); 335 } 336 dm_write_reg(compressor->ctx, addr, value); 337 338 addr = mmFBC_COMP_MODE; 339 value = dm_read_reg(compressor->ctx, addr); 340 set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_RLE_EN); 341 set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_DPCM4_RGB_EN); 342 set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_IND_EN); 343 dm_write_reg(compressor->ctx, addr, value); 344 345 addr = mmFBC_COMP_CNTL; 346 value = dm_read_reg(compressor->ctx, addr); 347 set_reg_field_value(value, 1, FBC_COMP_CNTL, FBC_DEPTH_RGB08_EN); 348 dm_write_reg(compressor->ctx, addr, value); 349 /*FBC_MIN_COMPRESSION 0 ==> 2:1 */ 350 /* 1 ==> 4:1 */ 351 /* 2 ==> 8:1 */ 352 /* 0xF ==> 1:1 */ 353 set_reg_field_value(value, 0xF, FBC_COMP_CNTL, FBC_MIN_COMPRESSION); 354 dm_write_reg(compressor->ctx, addr, value); 355 compressor->min_compress_ratio = FBC_COMPRESS_RATIO_1TO1; 356 357 value = 0; 358 dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value); 359 360 value = 0xFFFFFF; 361 dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value); 362 } 363 364 void dce112_compressor_enable_fbc( 365 struct compressor *compressor, 366 uint32_t paths_num, 367 struct compr_addr_and_pitch_params *params) 368 { 369 struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor); 370 371 if (compressor->options.bits.FBC_SUPPORT && 372 (compressor->options.bits.DUMMY_BACKEND == 0) && 373 (!dce112_compressor_is_fbc_enabled_in_hw(compressor, NULL)) && 374 (!is_source_bigger_than_epanel_size( 375 cp110, 376 params->source_view_width, 377 params->source_view_height))) { 378 379 uint32_t addr; 380 uint32_t value; 381 382 /* Before enabling FBC first need to enable LPT if applicable 383 * LPT state should always be changed (enable/disable) while FBC 384 * is disabled */ 385 if (compressor->options.bits.LPT_SUPPORT && (paths_num < 2) && 386 (params->source_view_width * 387 params->source_view_height <= 388 dce11_one_lpt_channel_max_resolution)) { 389 dce112_compressor_enable_lpt(compressor); 390 } 391 392 addr = mmFBC_CNTL; 393 value = dm_read_reg(compressor->ctx, addr); 394 set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN); 395 set_reg_field_value( 396 value, 397 params->inst, 398 FBC_CNTL, FBC_SRC_SEL); 399 dm_write_reg(compressor->ctx, addr, value); 400 401 /* Keep track of enum controller_id FBC is attached to */ 402 compressor->is_enabled = true; 403 compressor->attached_inst = params->inst; 404 cp110->offsets = reg_offsets[params->inst]; 405 406 /*Toggle it as there is bug in HW */ 407 set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN); 408 dm_write_reg(compressor->ctx, addr, value); 409 set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN); 410 dm_write_reg(compressor->ctx, addr, value); 411 412 wait_for_fbc_state_changed(cp110, true); 413 } 414 } 415 416 void dce112_compressor_disable_fbc(struct compressor *compressor) 417 { 418 struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor); 419 420 if (compressor->options.bits.FBC_SUPPORT && 421 dce112_compressor_is_fbc_enabled_in_hw(compressor, NULL)) { 422 uint32_t reg_data; 423 /* Turn off compression */ 424 reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL); 425 set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN); 426 dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data); 427 428 /* Reset enum controller_id to undefined */ 429 compressor->attached_inst = 0; 430 compressor->is_enabled = false; 431 432 /* Whenever disabling FBC make sure LPT is disabled if LPT 433 * supported */ 434 if (compressor->options.bits.LPT_SUPPORT) 435 dce112_compressor_disable_lpt(compressor); 436 437 wait_for_fbc_state_changed(cp110, false); 438 } 439 } 440 441 bool dce112_compressor_is_fbc_enabled_in_hw( 442 struct compressor *compressor, 443 uint32_t *inst) 444 { 445 /* Check the hardware register */ 446 uint32_t value; 447 448 value = dm_read_reg(compressor->ctx, mmFBC_STATUS); 449 if (get_reg_field_value(value, FBC_STATUS, FBC_ENABLE_STATUS)) { 450 if (inst != NULL) 451 *inst = compressor->attached_inst; 452 return true; 453 } 454 455 value = dm_read_reg(compressor->ctx, mmFBC_MISC); 456 if (get_reg_field_value(value, FBC_MISC, FBC_STOP_ON_HFLIP_EVENT)) { 457 value = dm_read_reg(compressor->ctx, mmFBC_CNTL); 458 459 if (get_reg_field_value(value, FBC_CNTL, FBC_GRPH_COMP_EN)) { 460 if (inst != NULL) 461 *inst = 462 compressor->attached_inst; 463 return true; 464 } 465 } 466 return false; 467 } 468 469 bool dce112_compressor_is_lpt_enabled_in_hw(struct compressor *compressor) 470 { 471 /* Check the hardware register */ 472 uint32_t value = dm_read_reg(compressor->ctx, 473 mmLOW_POWER_TILING_CONTROL); 474 475 return get_reg_field_value( 476 value, 477 LOW_POWER_TILING_CONTROL, 478 LOW_POWER_TILING_ENABLE); 479 } 480 481 void dce112_compressor_program_compressed_surface_address_and_pitch( 482 struct compressor *compressor, 483 struct compr_addr_and_pitch_params *params) 484 { 485 struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor); 486 uint32_t value = 0; 487 uint32_t fbc_pitch = 0; 488 uint32_t compressed_surf_address_low_part = 489 compressor->compr_surface_address.addr.low_part; 490 491 /* Clear content first. */ 492 dm_write_reg( 493 compressor->ctx, 494 DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH), 495 0); 496 dm_write_reg(compressor->ctx, 497 DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS), 0); 498 499 if (compressor->options.bits.LPT_SUPPORT) { 500 uint32_t lpt_alignment = lpt_size_alignment(cp110); 501 502 if (lpt_alignment != 0) { 503 compressed_surf_address_low_part = 504 ((compressed_surf_address_low_part 505 + (lpt_alignment - 1)) / lpt_alignment) 506 * lpt_alignment; 507 } 508 } 509 510 /* Write address, HIGH has to be first. */ 511 dm_write_reg(compressor->ctx, 512 DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH), 513 compressor->compr_surface_address.addr.high_part); 514 dm_write_reg(compressor->ctx, 515 DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS), 516 compressed_surf_address_low_part); 517 518 fbc_pitch = align_to_chunks_number_per_line( 519 cp110, 520 params->source_view_width); 521 522 if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1) 523 fbc_pitch = fbc_pitch / 8; 524 else 525 DC_LOG_WARNING( 526 "%s: Unexpected DCE11 compression ratio", 527 __func__); 528 529 /* Clear content first. */ 530 dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), 0); 531 532 /* Write FBC Pitch. */ 533 set_reg_field_value( 534 value, 535 fbc_pitch, 536 GRPH_COMPRESS_PITCH, 537 GRPH_COMPRESS_PITCH); 538 dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), value); 539 540 } 541 542 void dce112_compressor_disable_lpt(struct compressor *compressor) 543 { 544 struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor); 545 uint32_t value; 546 uint32_t addr; 547 uint32_t inx; 548 549 /* Disable all pipes LPT Stutter */ 550 for (inx = 0; inx < 3; inx++) { 551 value = 552 dm_read_reg( 553 compressor->ctx, 554 DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH)); 555 set_reg_field_value( 556 value, 557 0, 558 DPG_PIPE_STUTTER_CONTROL_NONLPTCH, 559 STUTTER_ENABLE_NONLPTCH); 560 dm_write_reg( 561 compressor->ctx, 562 DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH), 563 value); 564 } 565 /* Disable Underlay pipe LPT Stutter */ 566 addr = mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH; 567 value = dm_read_reg(compressor->ctx, addr); 568 set_reg_field_value( 569 value, 570 0, 571 DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH, 572 STUTTER_ENABLE_NONLPTCH); 573 dm_write_reg(compressor->ctx, addr, value); 574 575 /* Disable LPT */ 576 addr = mmLOW_POWER_TILING_CONTROL; 577 value = dm_read_reg(compressor->ctx, addr); 578 set_reg_field_value( 579 value, 580 0, 581 LOW_POWER_TILING_CONTROL, 582 LOW_POWER_TILING_ENABLE); 583 dm_write_reg(compressor->ctx, addr, value); 584 585 /* Clear selection of Channel(s) containing Compressed Surface */ 586 addr = mmGMCON_LPT_TARGET; 587 value = dm_read_reg(compressor->ctx, addr); 588 set_reg_field_value( 589 value, 590 0xFFFFFFFF, 591 GMCON_LPT_TARGET, 592 STCTRL_LPT_TARGET); 593 dm_write_reg(compressor->ctx, mmGMCON_LPT_TARGET, value); 594 } 595 596 void dce112_compressor_enable_lpt(struct compressor *compressor) 597 { 598 struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor); 599 uint32_t value; 600 uint32_t addr; 601 uint32_t value_control; 602 uint32_t channels; 603 604 /* Enable LPT Stutter from Display pipe */ 605 value = dm_read_reg(compressor->ctx, 606 DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH)); 607 set_reg_field_value( 608 value, 609 1, 610 DPG_PIPE_STUTTER_CONTROL_NONLPTCH, 611 STUTTER_ENABLE_NONLPTCH); 612 dm_write_reg(compressor->ctx, 613 DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH), value); 614 615 /* Enable Underlay pipe LPT Stutter */ 616 addr = mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH; 617 value = dm_read_reg(compressor->ctx, addr); 618 set_reg_field_value( 619 value, 620 1, 621 DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH, 622 STUTTER_ENABLE_NONLPTCH); 623 dm_write_reg(compressor->ctx, addr, value); 624 625 /* Selection of Channel(s) containing Compressed Surface: 0xfffffff 626 * will disable LPT. 627 * STCTRL_LPT_TARGETn corresponds to channel n. */ 628 addr = mmLOW_POWER_TILING_CONTROL; 629 value_control = dm_read_reg(compressor->ctx, addr); 630 channels = get_reg_field_value(value_control, 631 LOW_POWER_TILING_CONTROL, 632 LOW_POWER_TILING_MODE); 633 634 addr = mmGMCON_LPT_TARGET; 635 value = dm_read_reg(compressor->ctx, addr); 636 set_reg_field_value( 637 value, 638 channels + 1, /* not mentioned in programming guide, 639 but follow DCE8.1 */ 640 GMCON_LPT_TARGET, 641 STCTRL_LPT_TARGET); 642 dm_write_reg(compressor->ctx, addr, value); 643 644 /* Enable LPT */ 645 addr = mmLOW_POWER_TILING_CONTROL; 646 value = dm_read_reg(compressor->ctx, addr); 647 set_reg_field_value( 648 value, 649 1, 650 LOW_POWER_TILING_CONTROL, 651 LOW_POWER_TILING_ENABLE); 652 dm_write_reg(compressor->ctx, addr, value); 653 } 654 655 void dce112_compressor_program_lpt_control( 656 struct compressor *compressor, 657 struct compr_addr_and_pitch_params *params) 658 { 659 struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor); 660 uint32_t rows_per_channel; 661 uint32_t lpt_alignment; 662 uint32_t source_view_width; 663 uint32_t source_view_height; 664 uint32_t lpt_control = 0; 665 666 if (!compressor->options.bits.LPT_SUPPORT) 667 return; 668 669 lpt_control = dm_read_reg(compressor->ctx, 670 mmLOW_POWER_TILING_CONTROL); 671 672 /* POSSIBLE VALUES for Low Power Tiling Mode: 673 * 00 - Use channel 0 674 * 01 - Use Channel 0 and 1 675 * 02 - Use Channel 0,1,2,3 676 * 03 - reserved */ 677 switch (compressor->lpt_channels_num) { 678 /* case 2: 679 * Use Channel 0 & 1 / Not used for DCE 11 */ 680 case 1: 681 /*Use Channel 0 for LPT for DCE 11 */ 682 set_reg_field_value( 683 lpt_control, 684 0, 685 LOW_POWER_TILING_CONTROL, 686 LOW_POWER_TILING_MODE); 687 break; 688 default: 689 DC_LOG_WARNING( 690 "%s: Invalid selected DRAM channels for LPT!!!", 691 __func__); 692 break; 693 } 694 695 lpt_control = lpt_memory_control_config(cp110, lpt_control); 696 697 /* Program LOW_POWER_TILING_ROWS_PER_CHAN field which depends on 698 * FBC compressed surface pitch. 699 * LOW_POWER_TILING_ROWS_PER_CHAN = Roundup ((Surface Height * 700 * Surface Pitch) / (Row Size * Number of Channels * 701 * Number of Banks)). */ 702 rows_per_channel = 0; 703 lpt_alignment = lpt_size_alignment(cp110); 704 source_view_width = 705 align_to_chunks_number_per_line( 706 cp110, 707 params->source_view_width); 708 source_view_height = (params->source_view_height + 1) & (~0x1); 709 710 if (lpt_alignment != 0) { 711 rows_per_channel = source_view_width * source_view_height * 4; 712 rows_per_channel = 713 (rows_per_channel % lpt_alignment) ? 714 (rows_per_channel / lpt_alignment + 1) : 715 rows_per_channel / lpt_alignment; 716 } 717 718 set_reg_field_value( 719 lpt_control, 720 rows_per_channel, 721 LOW_POWER_TILING_CONTROL, 722 LOW_POWER_TILING_ROWS_PER_CHAN); 723 724 dm_write_reg(compressor->ctx, 725 mmLOW_POWER_TILING_CONTROL, lpt_control); 726 } 727 728 /* 729 * DCE 11 Frame Buffer Compression Implementation 730 */ 731 732 void dce112_compressor_set_fbc_invalidation_triggers( 733 struct compressor *compressor, 734 uint32_t fbc_trigger) 735 { 736 /* Disable region hit event, FBC_MEMORY_REGION_MASK = 0 (bits 16-19) 737 * for DCE 11 regions cannot be used - does not work with S/G 738 */ 739 uint32_t addr = mmFBC_CLIENT_REGION_MASK; 740 uint32_t value = dm_read_reg(compressor->ctx, addr); 741 742 set_reg_field_value( 743 value, 744 0, 745 FBC_CLIENT_REGION_MASK, 746 FBC_MEMORY_REGION_MASK); 747 dm_write_reg(compressor->ctx, addr, value); 748 749 /* Setup events when to clear all CSM entries (effectively marking 750 * current compressed data invalid) 751 * For DCE 11 CSM metadata 11111 means - "Not Compressed" 752 * Used as the initial value of the metadata sent to the compressor 753 * after invalidation, to indicate that the compressor should attempt 754 * to compress all chunks on the current pass. Also used when the chunk 755 * is not successfully written to memory. 756 * When this CSM value is detected, FBC reads from the uncompressed 757 * buffer. Set events according to passed in value, these events are 758 * valid for DCE11: 759 * - bit 0 - display register updated 760 * - bit 28 - memory write from any client except from MCIF 761 * - bit 29 - CG static screen signal is inactive 762 * In addition, DCE11.1 also needs to set new DCE11.1 specific events 763 * that are used to trigger invalidation on certain register changes, 764 * for example enabling of Alpha Compression may trigger invalidation of 765 * FBC once bit is set. These events are as follows: 766 * - Bit 2 - FBC_GRPH_COMP_EN register updated 767 * - Bit 3 - FBC_SRC_SEL register updated 768 * - Bit 4 - FBC_MIN_COMPRESSION register updated 769 * - Bit 5 - FBC_ALPHA_COMP_EN register updated 770 * - Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated 771 * - Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated 772 */ 773 addr = mmFBC_IDLE_FORCE_CLEAR_MASK; 774 value = dm_read_reg(compressor->ctx, addr); 775 set_reg_field_value( 776 value, 777 fbc_trigger | 778 FBC_IDLE_FORCE_GRPH_COMP_EN | 779 FBC_IDLE_FORCE_SRC_SEL_CHANGE | 780 FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE | 781 FBC_IDLE_FORCE_ALPHA_COMP_EN | 782 FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN | 783 FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF, 784 FBC_IDLE_FORCE_CLEAR_MASK, 785 FBC_IDLE_FORCE_CLEAR_MASK); 786 dm_write_reg(compressor->ctx, addr, value); 787 } 788 789 void dce112_compressor_construct(struct dce112_compressor *compressor, 790 struct dc_context *ctx) 791 { 792 struct dc_bios *bp = ctx->dc_bios; 793 struct embedded_panel_info panel_info; 794 795 compressor->base.options.raw = 0; 796 compressor->base.options.bits.FBC_SUPPORT = true; 797 compressor->base.options.bits.LPT_SUPPORT = true; 798 /* For DCE 11 always use one DRAM channel for LPT */ 799 compressor->base.lpt_channels_num = 1; 800 compressor->base.options.bits.DUMMY_BACKEND = false; 801 802 /* Check if this system has more than 1 DRAM channel; if only 1 then LPT 803 * should not be supported */ 804 if (compressor->base.memory_bus_width == 64) 805 compressor->base.options.bits.LPT_SUPPORT = false; 806 807 compressor->base.options.bits.CLK_GATING_DISABLED = false; 808 809 compressor->base.ctx = ctx; 810 compressor->base.embedded_panel_h_size = 0; 811 compressor->base.embedded_panel_v_size = 0; 812 compressor->base.memory_bus_width = ctx->asic_id.vram_width; 813 compressor->base.allocated_size = 0; 814 compressor->base.preferred_requested_size = 0; 815 compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID; 816 compressor->base.banks_num = 0; 817 compressor->base.raw_size = 0; 818 compressor->base.channel_interleave_size = 0; 819 compressor->base.dram_channels_num = 0; 820 compressor->base.lpt_channels_num = 0; 821 compressor->base.attached_inst = 0; 822 compressor->base.is_enabled = false; 823 824 if (BP_RESULT_OK == 825 bp->funcs->get_embedded_panel_info(bp, &panel_info)) { 826 compressor->base.embedded_panel_h_size = 827 panel_info.lcd_timing.horizontal_addressable; 828 compressor->base.embedded_panel_v_size = 829 panel_info.lcd_timing.vertical_addressable; 830 } 831 } 832 833 struct compressor *dce112_compressor_create(struct dc_context *ctx) 834 { 835 struct dce112_compressor *cp110 = 836 kzalloc(sizeof(struct dce112_compressor), GFP_KERNEL); 837 838 if (!cp110) 839 return NULL; 840 841 dce112_compressor_construct(cp110, ctx); 842 return &cp110->base; 843 } 844 845 void dce112_compressor_destroy(struct compressor **compressor) 846 { 847 kfree(TO_DCE112_COMPRESSOR(*compressor)); 848 *compressor = NULL; 849 } 850