14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2012-15 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 254562236bSHarry Wentland 264562236bSHarry Wentland #include "dm_services.h" 274562236bSHarry Wentland 284562236bSHarry Wentland #include "dce/dce_11_2_d.h" 294562236bSHarry Wentland #include "dce/dce_11_2_sh_mask.h" 304562236bSHarry Wentland #include "gmc/gmc_8_1_sh_mask.h" 314562236bSHarry Wentland #include "gmc/gmc_8_1_d.h" 324562236bSHarry Wentland 334562236bSHarry Wentland #include "include/logger_interface.h" 344562236bSHarry Wentland 354562236bSHarry Wentland #include "dce112_compressor.h" 364562236bSHarry Wentland 374562236bSHarry Wentland #define DCP_REG(reg)\ 384562236bSHarry Wentland (reg + cp110->offsets.dcp_offset) 394562236bSHarry Wentland #define DMIF_REG(reg)\ 404562236bSHarry Wentland (reg + cp110->offsets.dmif_offset) 414562236bSHarry Wentland 424562236bSHarry Wentland static const struct dce112_compressor_reg_offsets reg_offsets[] = { 434562236bSHarry Wentland { 444562236bSHarry Wentland .dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 454562236bSHarry Wentland .dmif_offset = 464562236bSHarry Wentland (mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 474562236bSHarry Wentland - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL), 484562236bSHarry Wentland }, 494562236bSHarry Wentland { 504562236bSHarry Wentland .dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 514562236bSHarry Wentland .dmif_offset = 524562236bSHarry Wentland (mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 534562236bSHarry Wentland - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL), 544562236bSHarry Wentland }, 554562236bSHarry Wentland { 564562236bSHarry Wentland .dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 574562236bSHarry Wentland .dmif_offset = 584562236bSHarry Wentland (mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 594562236bSHarry Wentland - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL), 604562236bSHarry Wentland } 614562236bSHarry Wentland }; 624562236bSHarry Wentland 634562236bSHarry Wentland static const uint32_t dce11_one_lpt_channel_max_resolution = 2560 * 1600; 644562236bSHarry Wentland 654562236bSHarry Wentland enum fbc_idle_force { 664562236bSHarry Wentland /* Bit 0 - Display registers updated */ 674562236bSHarry Wentland FBC_IDLE_FORCE_DISPLAY_REGISTER_UPDATE = 0x00000001, 684562236bSHarry Wentland 694562236bSHarry Wentland /* Bit 2 - FBC_GRPH_COMP_EN register updated */ 704562236bSHarry Wentland FBC_IDLE_FORCE_GRPH_COMP_EN = 0x00000002, 714562236bSHarry Wentland /* Bit 3 - FBC_SRC_SEL register updated */ 724562236bSHarry Wentland FBC_IDLE_FORCE_SRC_SEL_CHANGE = 0x00000004, 734562236bSHarry Wentland /* Bit 4 - FBC_MIN_COMPRESSION register updated */ 744562236bSHarry Wentland FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE = 0x00000008, 754562236bSHarry Wentland /* Bit 5 - FBC_ALPHA_COMP_EN register updated */ 764562236bSHarry Wentland FBC_IDLE_FORCE_ALPHA_COMP_EN = 0x00000010, 774562236bSHarry Wentland /* Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated */ 784562236bSHarry Wentland FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN = 0x00000020, 794562236bSHarry Wentland /* Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated */ 804562236bSHarry Wentland FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF = 0x00000040, 814562236bSHarry Wentland 824562236bSHarry Wentland /* Bit 24 - Memory write to region 0 defined by MC registers. */ 834562236bSHarry Wentland FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION0 = 0x01000000, 844562236bSHarry Wentland /* Bit 25 - Memory write to region 1 defined by MC registers */ 854562236bSHarry Wentland FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION1 = 0x02000000, 864562236bSHarry Wentland /* Bit 26 - Memory write to region 2 defined by MC registers */ 874562236bSHarry Wentland FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION2 = 0x04000000, 884562236bSHarry Wentland /* Bit 27 - Memory write to region 3 defined by MC registers. */ 894562236bSHarry Wentland FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION3 = 0x08000000, 904562236bSHarry Wentland 914562236bSHarry Wentland /* Bit 28 - Memory write from any client other than MCIF */ 924562236bSHarry Wentland FBC_IDLE_FORCE_MEMORY_WRITE_OTHER_THAN_MCIF = 0x10000000, 934562236bSHarry Wentland /* Bit 29 - CG statics screen signal is inactive */ 944562236bSHarry Wentland FBC_IDLE_FORCE_CG_STATIC_SCREEN_IS_INACTIVE = 0x20000000, 954562236bSHarry Wentland }; 964562236bSHarry Wentland 974562236bSHarry Wentland static uint32_t lpt_size_alignment(struct dce112_compressor *cp110) 984562236bSHarry Wentland { 994562236bSHarry Wentland /*LPT_ALIGNMENT (in bytes) = ROW_SIZE * #BANKS * # DRAM CHANNELS. */ 1004562236bSHarry Wentland return cp110->base.raw_size * cp110->base.banks_num * 1014562236bSHarry Wentland cp110->base.dram_channels_num; 1024562236bSHarry Wentland } 1034562236bSHarry Wentland 1044562236bSHarry Wentland static uint32_t lpt_memory_control_config(struct dce112_compressor *cp110, 1054562236bSHarry Wentland uint32_t lpt_control) 1064562236bSHarry Wentland { 1074562236bSHarry Wentland /*LPT MC Config */ 1084562236bSHarry Wentland if (cp110->base.options.bits.LPT_MC_CONFIG == 1) { 1094562236bSHarry Wentland /* POSSIBLE VALUES for LPT NUM_PIPES (DRAM CHANNELS): 1104562236bSHarry Wentland * 00 - 1 CHANNEL 1114562236bSHarry Wentland * 01 - 2 CHANNELS 1124562236bSHarry Wentland * 02 - 4 OR 6 CHANNELS 1134562236bSHarry Wentland * (Only for discrete GPU, N/A for CZ) 1144562236bSHarry Wentland * 03 - 8 OR 12 CHANNELS 1154562236bSHarry Wentland * (Only for discrete GPU, N/A for CZ) */ 1164562236bSHarry Wentland switch (cp110->base.dram_channels_num) { 1174562236bSHarry Wentland case 2: 1184562236bSHarry Wentland set_reg_field_value( 1194562236bSHarry Wentland lpt_control, 1204562236bSHarry Wentland 1, 1214562236bSHarry Wentland LOW_POWER_TILING_CONTROL, 1224562236bSHarry Wentland LOW_POWER_TILING_NUM_PIPES); 1234562236bSHarry Wentland break; 1244562236bSHarry Wentland case 1: 1254562236bSHarry Wentland set_reg_field_value( 1264562236bSHarry Wentland lpt_control, 1274562236bSHarry Wentland 0, 1284562236bSHarry Wentland LOW_POWER_TILING_CONTROL, 1294562236bSHarry Wentland LOW_POWER_TILING_NUM_PIPES); 1304562236bSHarry Wentland break; 1314562236bSHarry Wentland default: 1324562236bSHarry Wentland dm_logger_write( 1334562236bSHarry Wentland cp110->base.ctx->logger, LOG_WARNING, 1344562236bSHarry Wentland "%s: Invalid LPT NUM_PIPES!!!", 1354562236bSHarry Wentland __func__); 1364562236bSHarry Wentland break; 1374562236bSHarry Wentland } 1384562236bSHarry Wentland 1394562236bSHarry Wentland /* The mapping for LPT NUM_BANKS is in 1404562236bSHarry Wentland * GRPH_CONTROL.GRPH_NUM_BANKS register field 1414562236bSHarry Wentland * Specifies the number of memory banks for tiling 1424562236bSHarry Wentland * purposes. Only applies to 2D and 3D tiling modes. 1434562236bSHarry Wentland * POSSIBLE VALUES: 1444562236bSHarry Wentland * 00 - DCP_GRPH_NUM_BANKS_2BANK: ADDR_SURF_2_BANK 1454562236bSHarry Wentland * 01 - DCP_GRPH_NUM_BANKS_4BANK: ADDR_SURF_4_BANK 1464562236bSHarry Wentland * 02 - DCP_GRPH_NUM_BANKS_8BANK: ADDR_SURF_8_BANK 1474562236bSHarry Wentland * 03 - DCP_GRPH_NUM_BANKS_16BANK: ADDR_SURF_16_BANK */ 1484562236bSHarry Wentland switch (cp110->base.banks_num) { 1494562236bSHarry Wentland case 16: 1504562236bSHarry Wentland set_reg_field_value( 1514562236bSHarry Wentland lpt_control, 1524562236bSHarry Wentland 3, 1534562236bSHarry Wentland LOW_POWER_TILING_CONTROL, 1544562236bSHarry Wentland LOW_POWER_TILING_NUM_BANKS); 1554562236bSHarry Wentland break; 1564562236bSHarry Wentland case 8: 1574562236bSHarry Wentland set_reg_field_value( 1584562236bSHarry Wentland lpt_control, 1594562236bSHarry Wentland 2, 1604562236bSHarry Wentland LOW_POWER_TILING_CONTROL, 1614562236bSHarry Wentland LOW_POWER_TILING_NUM_BANKS); 1624562236bSHarry Wentland break; 1634562236bSHarry Wentland case 4: 1644562236bSHarry Wentland set_reg_field_value( 1654562236bSHarry Wentland lpt_control, 1664562236bSHarry Wentland 1, 1674562236bSHarry Wentland LOW_POWER_TILING_CONTROL, 1684562236bSHarry Wentland LOW_POWER_TILING_NUM_BANKS); 1694562236bSHarry Wentland break; 1704562236bSHarry Wentland case 2: 1714562236bSHarry Wentland set_reg_field_value( 1724562236bSHarry Wentland lpt_control, 1734562236bSHarry Wentland 0, 1744562236bSHarry Wentland LOW_POWER_TILING_CONTROL, 1754562236bSHarry Wentland LOW_POWER_TILING_NUM_BANKS); 1764562236bSHarry Wentland break; 1774562236bSHarry Wentland default: 1784562236bSHarry Wentland dm_logger_write( 1794562236bSHarry Wentland cp110->base.ctx->logger, LOG_WARNING, 1804562236bSHarry Wentland "%s: Invalid LPT NUM_BANKS!!!", 1814562236bSHarry Wentland __func__); 1824562236bSHarry Wentland break; 1834562236bSHarry Wentland } 1844562236bSHarry Wentland 1854562236bSHarry Wentland /* The mapping is in DMIF_ADDR_CALC. 1864562236bSHarry Wentland * ADDR_CONFIG_PIPE_INTERLEAVE_SIZE register field for 1874562236bSHarry Wentland * Carrizo specifies the memory interleave per pipe. 1884562236bSHarry Wentland * It effectively specifies the location of pipe bits in 1894562236bSHarry Wentland * the memory address. 1904562236bSHarry Wentland * POSSIBLE VALUES: 1914562236bSHarry Wentland * 00 - ADDR_CONFIG_PIPE_INTERLEAVE_256B: 256 byte 1924562236bSHarry Wentland * interleave 1934562236bSHarry Wentland * 01 - ADDR_CONFIG_PIPE_INTERLEAVE_512B: 512 byte 1944562236bSHarry Wentland * interleave 1954562236bSHarry Wentland */ 1964562236bSHarry Wentland switch (cp110->base.channel_interleave_size) { 1974562236bSHarry Wentland case 256: /*256B */ 1984562236bSHarry Wentland set_reg_field_value( 1994562236bSHarry Wentland lpt_control, 2004562236bSHarry Wentland 0, 2014562236bSHarry Wentland LOW_POWER_TILING_CONTROL, 2024562236bSHarry Wentland LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE); 2034562236bSHarry Wentland break; 2044562236bSHarry Wentland case 512: /*512B */ 2054562236bSHarry Wentland set_reg_field_value( 2064562236bSHarry Wentland lpt_control, 2074562236bSHarry Wentland 1, 2084562236bSHarry Wentland LOW_POWER_TILING_CONTROL, 2094562236bSHarry Wentland LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE); 2104562236bSHarry Wentland break; 2114562236bSHarry Wentland default: 2124562236bSHarry Wentland dm_logger_write( 2134562236bSHarry Wentland cp110->base.ctx->logger, LOG_WARNING, 2144562236bSHarry Wentland "%s: Invalid LPT INTERLEAVE_SIZE!!!", 2154562236bSHarry Wentland __func__); 2164562236bSHarry Wentland break; 2174562236bSHarry Wentland } 2184562236bSHarry Wentland 2194562236bSHarry Wentland /* The mapping for LOW_POWER_TILING_ROW_SIZE is in 2204562236bSHarry Wentland * DMIF_ADDR_CALC.ADDR_CONFIG_ROW_SIZE register field 2214562236bSHarry Wentland * for Carrizo. Specifies the size of dram row in bytes. 2224562236bSHarry Wentland * This should match up with NOOFCOLS field in 2234562236bSHarry Wentland * MC_ARB_RAMCFG (ROW_SIZE = 4 * 2 ^^ columns). 2244562236bSHarry Wentland * This register DMIF_ADDR_CALC is not used by the 2254562236bSHarry Wentland * hardware as it is only used for addrlib assertions. 2264562236bSHarry Wentland * POSSIBLE VALUES: 2274562236bSHarry Wentland * 00 - ADDR_CONFIG_1KB_ROW: Treat 1KB as DRAM row 2284562236bSHarry Wentland * boundary 2294562236bSHarry Wentland * 01 - ADDR_CONFIG_2KB_ROW: Treat 2KB as DRAM row 2304562236bSHarry Wentland * boundary 2314562236bSHarry Wentland * 02 - ADDR_CONFIG_4KB_ROW: Treat 4KB as DRAM row 2324562236bSHarry Wentland * boundary */ 2334562236bSHarry Wentland switch (cp110->base.raw_size) { 2344562236bSHarry Wentland case 4096: /*4 KB */ 2354562236bSHarry Wentland set_reg_field_value( 2364562236bSHarry Wentland lpt_control, 2374562236bSHarry Wentland 2, 2384562236bSHarry Wentland LOW_POWER_TILING_CONTROL, 2394562236bSHarry Wentland LOW_POWER_TILING_ROW_SIZE); 2404562236bSHarry Wentland break; 2414562236bSHarry Wentland case 2048: 2424562236bSHarry Wentland set_reg_field_value( 2434562236bSHarry Wentland lpt_control, 2444562236bSHarry Wentland 1, 2454562236bSHarry Wentland LOW_POWER_TILING_CONTROL, 2464562236bSHarry Wentland LOW_POWER_TILING_ROW_SIZE); 2474562236bSHarry Wentland break; 2484562236bSHarry Wentland case 1024: 2494562236bSHarry Wentland set_reg_field_value( 2504562236bSHarry Wentland lpt_control, 2514562236bSHarry Wentland 0, 2524562236bSHarry Wentland LOW_POWER_TILING_CONTROL, 2534562236bSHarry Wentland LOW_POWER_TILING_ROW_SIZE); 2544562236bSHarry Wentland break; 2554562236bSHarry Wentland default: 2564562236bSHarry Wentland dm_logger_write( 2574562236bSHarry Wentland cp110->base.ctx->logger, LOG_WARNING, 2584562236bSHarry Wentland "%s: Invalid LPT ROW_SIZE!!!", 2594562236bSHarry Wentland __func__); 2604562236bSHarry Wentland break; 2614562236bSHarry Wentland } 2624562236bSHarry Wentland } else { 2634562236bSHarry Wentland dm_logger_write( 2644562236bSHarry Wentland cp110->base.ctx->logger, LOG_WARNING, 2654562236bSHarry Wentland "%s: LPT MC Configuration is not provided", 2664562236bSHarry Wentland __func__); 2674562236bSHarry Wentland } 2684562236bSHarry Wentland 2694562236bSHarry Wentland return lpt_control; 2704562236bSHarry Wentland } 2714562236bSHarry Wentland 2724562236bSHarry Wentland static bool is_source_bigger_than_epanel_size( 2734562236bSHarry Wentland struct dce112_compressor *cp110, 2744562236bSHarry Wentland uint32_t source_view_width, 2754562236bSHarry Wentland uint32_t source_view_height) 2764562236bSHarry Wentland { 2774562236bSHarry Wentland if (cp110->base.embedded_panel_h_size != 0 && 2784562236bSHarry Wentland cp110->base.embedded_panel_v_size != 0 && 2794562236bSHarry Wentland ((source_view_width * source_view_height) > 2804562236bSHarry Wentland (cp110->base.embedded_panel_h_size * 2814562236bSHarry Wentland cp110->base.embedded_panel_v_size))) 2824562236bSHarry Wentland return true; 2834562236bSHarry Wentland 2844562236bSHarry Wentland return false; 2854562236bSHarry Wentland } 2864562236bSHarry Wentland 2874562236bSHarry Wentland static uint32_t align_to_chunks_number_per_line( 2884562236bSHarry Wentland struct dce112_compressor *cp110, 2894562236bSHarry Wentland uint32_t pixels) 2904562236bSHarry Wentland { 2914562236bSHarry Wentland return 256 * ((pixels + 255) / 256); 2924562236bSHarry Wentland } 2934562236bSHarry Wentland 2944562236bSHarry Wentland static void wait_for_fbc_state_changed( 2954562236bSHarry Wentland struct dce112_compressor *cp110, 2964562236bSHarry Wentland bool enabled) 2974562236bSHarry Wentland { 2984562236bSHarry Wentland uint8_t counter = 0; 2994562236bSHarry Wentland uint32_t addr = mmFBC_STATUS; 3004562236bSHarry Wentland uint32_t value; 3014562236bSHarry Wentland 3024562236bSHarry Wentland while (counter < 10) { 3034562236bSHarry Wentland value = dm_read_reg(cp110->base.ctx, addr); 3044562236bSHarry Wentland if (get_reg_field_value( 3054562236bSHarry Wentland value, 3064562236bSHarry Wentland FBC_STATUS, 3074562236bSHarry Wentland FBC_ENABLE_STATUS) == enabled) 3084562236bSHarry Wentland break; 3094562236bSHarry Wentland udelay(10); 3104562236bSHarry Wentland counter++; 3114562236bSHarry Wentland } 3124562236bSHarry Wentland 3134562236bSHarry Wentland if (counter == 10) { 3144562236bSHarry Wentland dm_logger_write( 3154562236bSHarry Wentland cp110->base.ctx->logger, LOG_WARNING, 3164562236bSHarry Wentland "%s: wait counter exceeded, changes to HW not applied", 3174562236bSHarry Wentland __func__); 3184562236bSHarry Wentland } 3194562236bSHarry Wentland } 3204562236bSHarry Wentland 3214562236bSHarry Wentland void dce112_compressor_power_up_fbc(struct compressor *compressor) 3224562236bSHarry Wentland { 3234562236bSHarry Wentland uint32_t value; 3244562236bSHarry Wentland uint32_t addr; 3254562236bSHarry Wentland 3264562236bSHarry Wentland addr = mmFBC_CNTL; 3274562236bSHarry Wentland value = dm_read_reg(compressor->ctx, addr); 3284562236bSHarry Wentland set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN); 3294562236bSHarry Wentland set_reg_field_value(value, 1, FBC_CNTL, FBC_EN); 3304562236bSHarry Wentland set_reg_field_value(value, 2, FBC_CNTL, FBC_COHERENCY_MODE); 3314562236bSHarry Wentland if (compressor->options.bits.CLK_GATING_DISABLED == 1) { 3324562236bSHarry Wentland /* HW needs to do power measurement comparison. */ 3334562236bSHarry Wentland set_reg_field_value( 3344562236bSHarry Wentland value, 3354562236bSHarry Wentland 0, 3364562236bSHarry Wentland FBC_CNTL, 3374562236bSHarry Wentland FBC_COMP_CLK_GATE_EN); 3384562236bSHarry Wentland } 3394562236bSHarry Wentland dm_write_reg(compressor->ctx, addr, value); 3404562236bSHarry Wentland 3414562236bSHarry Wentland addr = mmFBC_COMP_MODE; 3424562236bSHarry Wentland value = dm_read_reg(compressor->ctx, addr); 3434562236bSHarry Wentland set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_RLE_EN); 3444562236bSHarry Wentland set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_DPCM4_RGB_EN); 3454562236bSHarry Wentland set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_IND_EN); 3464562236bSHarry Wentland dm_write_reg(compressor->ctx, addr, value); 3474562236bSHarry Wentland 3484562236bSHarry Wentland addr = mmFBC_COMP_CNTL; 3494562236bSHarry Wentland value = dm_read_reg(compressor->ctx, addr); 3504562236bSHarry Wentland set_reg_field_value(value, 1, FBC_COMP_CNTL, FBC_DEPTH_RGB08_EN); 3514562236bSHarry Wentland dm_write_reg(compressor->ctx, addr, value); 3524562236bSHarry Wentland /*FBC_MIN_COMPRESSION 0 ==> 2:1 */ 3534562236bSHarry Wentland /* 1 ==> 4:1 */ 3544562236bSHarry Wentland /* 2 ==> 8:1 */ 3554562236bSHarry Wentland /* 0xF ==> 1:1 */ 3564562236bSHarry Wentland set_reg_field_value(value, 0xF, FBC_COMP_CNTL, FBC_MIN_COMPRESSION); 3574562236bSHarry Wentland dm_write_reg(compressor->ctx, addr, value); 3584562236bSHarry Wentland compressor->min_compress_ratio = FBC_COMPRESS_RATIO_1TO1; 3594562236bSHarry Wentland 3604562236bSHarry Wentland value = 0; 3614562236bSHarry Wentland dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value); 3624562236bSHarry Wentland 3634562236bSHarry Wentland value = 0xFFFFFF; 3644562236bSHarry Wentland dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value); 3654562236bSHarry Wentland } 3664562236bSHarry Wentland 3674562236bSHarry Wentland void dce112_compressor_enable_fbc( 3684562236bSHarry Wentland struct compressor *compressor, 3694562236bSHarry Wentland uint32_t paths_num, 3704562236bSHarry Wentland struct compr_addr_and_pitch_params *params) 3714562236bSHarry Wentland { 3724562236bSHarry Wentland struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor); 3734562236bSHarry Wentland 3744562236bSHarry Wentland if (compressor->options.bits.FBC_SUPPORT && 3754562236bSHarry Wentland (compressor->options.bits.DUMMY_BACKEND == 0) && 3764562236bSHarry Wentland (!dce112_compressor_is_fbc_enabled_in_hw(compressor, NULL)) && 3774562236bSHarry Wentland (!is_source_bigger_than_epanel_size( 3784562236bSHarry Wentland cp110, 3794562236bSHarry Wentland params->source_view_width, 3804562236bSHarry Wentland params->source_view_height))) { 3814562236bSHarry Wentland 3824562236bSHarry Wentland uint32_t addr; 3834562236bSHarry Wentland uint32_t value; 3844562236bSHarry Wentland 3854562236bSHarry Wentland /* Before enabling FBC first need to enable LPT if applicable 3864562236bSHarry Wentland * LPT state should always be changed (enable/disable) while FBC 3874562236bSHarry Wentland * is disabled */ 3884562236bSHarry Wentland if (compressor->options.bits.LPT_SUPPORT && (paths_num < 2) && 3894562236bSHarry Wentland (params->source_view_width * 3904562236bSHarry Wentland params->source_view_height <= 3914562236bSHarry Wentland dce11_one_lpt_channel_max_resolution)) { 3924562236bSHarry Wentland dce112_compressor_enable_lpt(compressor); 3934562236bSHarry Wentland } 3944562236bSHarry Wentland 3954562236bSHarry Wentland addr = mmFBC_CNTL; 3964562236bSHarry Wentland value = dm_read_reg(compressor->ctx, addr); 3974562236bSHarry Wentland set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN); 3984562236bSHarry Wentland set_reg_field_value( 3994562236bSHarry Wentland value, 4004562236bSHarry Wentland params->inst, 4014562236bSHarry Wentland FBC_CNTL, FBC_SRC_SEL); 4024562236bSHarry Wentland dm_write_reg(compressor->ctx, addr, value); 4034562236bSHarry Wentland 4044562236bSHarry Wentland /* Keep track of enum controller_id FBC is attached to */ 4054562236bSHarry Wentland compressor->is_enabled = true; 4064562236bSHarry Wentland compressor->attached_inst = params->inst; 40772f0281dSRoman Li cp110->offsets = reg_offsets[params->inst]; 4084562236bSHarry Wentland 4094562236bSHarry Wentland /*Toggle it as there is bug in HW */ 4104562236bSHarry Wentland set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN); 4114562236bSHarry Wentland dm_write_reg(compressor->ctx, addr, value); 4124562236bSHarry Wentland set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN); 4134562236bSHarry Wentland dm_write_reg(compressor->ctx, addr, value); 4144562236bSHarry Wentland 4154562236bSHarry Wentland wait_for_fbc_state_changed(cp110, true); 4164562236bSHarry Wentland } 4174562236bSHarry Wentland } 4184562236bSHarry Wentland 4194562236bSHarry Wentland void dce112_compressor_disable_fbc(struct compressor *compressor) 4204562236bSHarry Wentland { 4214562236bSHarry Wentland struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor); 4224562236bSHarry Wentland 4234562236bSHarry Wentland if (compressor->options.bits.FBC_SUPPORT && 4244562236bSHarry Wentland dce112_compressor_is_fbc_enabled_in_hw(compressor, NULL)) { 4254562236bSHarry Wentland uint32_t reg_data; 4264562236bSHarry Wentland /* Turn off compression */ 4274562236bSHarry Wentland reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL); 4284562236bSHarry Wentland set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN); 4294562236bSHarry Wentland dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data); 4304562236bSHarry Wentland 4314562236bSHarry Wentland /* Reset enum controller_id to undefined */ 4324562236bSHarry Wentland compressor->attached_inst = 0; 4334562236bSHarry Wentland compressor->is_enabled = false; 4344562236bSHarry Wentland 4354562236bSHarry Wentland /* Whenever disabling FBC make sure LPT is disabled if LPT 4364562236bSHarry Wentland * supported */ 4374562236bSHarry Wentland if (compressor->options.bits.LPT_SUPPORT) 4384562236bSHarry Wentland dce112_compressor_disable_lpt(compressor); 4394562236bSHarry Wentland 4404562236bSHarry Wentland wait_for_fbc_state_changed(cp110, false); 4414562236bSHarry Wentland } 4424562236bSHarry Wentland } 4434562236bSHarry Wentland 4444562236bSHarry Wentland bool dce112_compressor_is_fbc_enabled_in_hw( 4454562236bSHarry Wentland struct compressor *compressor, 4464562236bSHarry Wentland uint32_t *inst) 4474562236bSHarry Wentland { 4484562236bSHarry Wentland /* Check the hardware register */ 4494562236bSHarry Wentland uint32_t value; 4504562236bSHarry Wentland 4514562236bSHarry Wentland value = dm_read_reg(compressor->ctx, mmFBC_STATUS); 4524562236bSHarry Wentland if (get_reg_field_value(value, FBC_STATUS, FBC_ENABLE_STATUS)) { 4534562236bSHarry Wentland if (inst != NULL) 4544562236bSHarry Wentland *inst = compressor->attached_inst; 4554562236bSHarry Wentland return true; 4564562236bSHarry Wentland } 4574562236bSHarry Wentland 4584562236bSHarry Wentland value = dm_read_reg(compressor->ctx, mmFBC_MISC); 4594562236bSHarry Wentland if (get_reg_field_value(value, FBC_MISC, FBC_STOP_ON_HFLIP_EVENT)) { 4604562236bSHarry Wentland value = dm_read_reg(compressor->ctx, mmFBC_CNTL); 4614562236bSHarry Wentland 4624562236bSHarry Wentland if (get_reg_field_value(value, FBC_CNTL, FBC_GRPH_COMP_EN)) { 4634562236bSHarry Wentland if (inst != NULL) 4644562236bSHarry Wentland *inst = 4654562236bSHarry Wentland compressor->attached_inst; 4664562236bSHarry Wentland return true; 4674562236bSHarry Wentland } 4684562236bSHarry Wentland } 4694562236bSHarry Wentland return false; 4704562236bSHarry Wentland } 4714562236bSHarry Wentland 4724562236bSHarry Wentland bool dce112_compressor_is_lpt_enabled_in_hw(struct compressor *compressor) 4734562236bSHarry Wentland { 4744562236bSHarry Wentland /* Check the hardware register */ 4754562236bSHarry Wentland uint32_t value = dm_read_reg(compressor->ctx, 4764562236bSHarry Wentland mmLOW_POWER_TILING_CONTROL); 4774562236bSHarry Wentland 4784562236bSHarry Wentland return get_reg_field_value( 4794562236bSHarry Wentland value, 4804562236bSHarry Wentland LOW_POWER_TILING_CONTROL, 4814562236bSHarry Wentland LOW_POWER_TILING_ENABLE); 4824562236bSHarry Wentland } 4834562236bSHarry Wentland 4844562236bSHarry Wentland void dce112_compressor_program_compressed_surface_address_and_pitch( 4854562236bSHarry Wentland struct compressor *compressor, 4864562236bSHarry Wentland struct compr_addr_and_pitch_params *params) 4874562236bSHarry Wentland { 4884562236bSHarry Wentland struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor); 4894562236bSHarry Wentland uint32_t value = 0; 4904562236bSHarry Wentland uint32_t fbc_pitch = 0; 4914562236bSHarry Wentland uint32_t compressed_surf_address_low_part = 4924562236bSHarry Wentland compressor->compr_surface_address.addr.low_part; 4934562236bSHarry Wentland 4944562236bSHarry Wentland /* Clear content first. */ 4954562236bSHarry Wentland dm_write_reg( 4964562236bSHarry Wentland compressor->ctx, 4974562236bSHarry Wentland DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH), 4984562236bSHarry Wentland 0); 4994562236bSHarry Wentland dm_write_reg(compressor->ctx, 5004562236bSHarry Wentland DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS), 0); 5014562236bSHarry Wentland 5024562236bSHarry Wentland if (compressor->options.bits.LPT_SUPPORT) { 5034562236bSHarry Wentland uint32_t lpt_alignment = lpt_size_alignment(cp110); 5044562236bSHarry Wentland 5054562236bSHarry Wentland if (lpt_alignment != 0) { 5064562236bSHarry Wentland compressed_surf_address_low_part = 5074562236bSHarry Wentland ((compressed_surf_address_low_part 5084562236bSHarry Wentland + (lpt_alignment - 1)) / lpt_alignment) 5094562236bSHarry Wentland * lpt_alignment; 5104562236bSHarry Wentland } 5114562236bSHarry Wentland } 5124562236bSHarry Wentland 5134562236bSHarry Wentland /* Write address, HIGH has to be first. */ 5144562236bSHarry Wentland dm_write_reg(compressor->ctx, 5154562236bSHarry Wentland DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH), 5164562236bSHarry Wentland compressor->compr_surface_address.addr.high_part); 5174562236bSHarry Wentland dm_write_reg(compressor->ctx, 5184562236bSHarry Wentland DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS), 5194562236bSHarry Wentland compressed_surf_address_low_part); 5204562236bSHarry Wentland 5214562236bSHarry Wentland fbc_pitch = align_to_chunks_number_per_line( 5224562236bSHarry Wentland cp110, 5234562236bSHarry Wentland params->source_view_width); 5244562236bSHarry Wentland 5254562236bSHarry Wentland if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1) 5264562236bSHarry Wentland fbc_pitch = fbc_pitch / 8; 5274562236bSHarry Wentland else 5284562236bSHarry Wentland dm_logger_write( 5294562236bSHarry Wentland compressor->ctx->logger, LOG_WARNING, 5304562236bSHarry Wentland "%s: Unexpected DCE11 compression ratio", 5314562236bSHarry Wentland __func__); 5324562236bSHarry Wentland 5334562236bSHarry Wentland /* Clear content first. */ 5344562236bSHarry Wentland dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), 0); 5354562236bSHarry Wentland 5364562236bSHarry Wentland /* Write FBC Pitch. */ 5374562236bSHarry Wentland set_reg_field_value( 5384562236bSHarry Wentland value, 5394562236bSHarry Wentland fbc_pitch, 5404562236bSHarry Wentland GRPH_COMPRESS_PITCH, 5414562236bSHarry Wentland GRPH_COMPRESS_PITCH); 5424562236bSHarry Wentland dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), value); 5434562236bSHarry Wentland 5444562236bSHarry Wentland } 5454562236bSHarry Wentland 5464562236bSHarry Wentland void dce112_compressor_disable_lpt(struct compressor *compressor) 5474562236bSHarry Wentland { 5484562236bSHarry Wentland struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor); 5494562236bSHarry Wentland uint32_t value; 5504562236bSHarry Wentland uint32_t addr; 5514562236bSHarry Wentland uint32_t inx; 5524562236bSHarry Wentland 5534562236bSHarry Wentland /* Disable all pipes LPT Stutter */ 5544562236bSHarry Wentland for (inx = 0; inx < 3; inx++) { 5554562236bSHarry Wentland value = 5564562236bSHarry Wentland dm_read_reg( 5574562236bSHarry Wentland compressor->ctx, 5584562236bSHarry Wentland DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH)); 5594562236bSHarry Wentland set_reg_field_value( 5604562236bSHarry Wentland value, 5614562236bSHarry Wentland 0, 5624562236bSHarry Wentland DPG_PIPE_STUTTER_CONTROL_NONLPTCH, 5634562236bSHarry Wentland STUTTER_ENABLE_NONLPTCH); 5644562236bSHarry Wentland dm_write_reg( 5654562236bSHarry Wentland compressor->ctx, 5664562236bSHarry Wentland DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH), 5674562236bSHarry Wentland value); 5684562236bSHarry Wentland } 5694562236bSHarry Wentland /* Disable Underlay pipe LPT Stutter */ 5704562236bSHarry Wentland addr = mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH; 5714562236bSHarry Wentland value = dm_read_reg(compressor->ctx, addr); 5724562236bSHarry Wentland set_reg_field_value( 5734562236bSHarry Wentland value, 5744562236bSHarry Wentland 0, 5754562236bSHarry Wentland DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH, 5764562236bSHarry Wentland STUTTER_ENABLE_NONLPTCH); 5774562236bSHarry Wentland dm_write_reg(compressor->ctx, addr, value); 5784562236bSHarry Wentland 5794562236bSHarry Wentland /* Disable LPT */ 5804562236bSHarry Wentland addr = mmLOW_POWER_TILING_CONTROL; 5814562236bSHarry Wentland value = dm_read_reg(compressor->ctx, addr); 5824562236bSHarry Wentland set_reg_field_value( 5834562236bSHarry Wentland value, 5844562236bSHarry Wentland 0, 5854562236bSHarry Wentland LOW_POWER_TILING_CONTROL, 5864562236bSHarry Wentland LOW_POWER_TILING_ENABLE); 5874562236bSHarry Wentland dm_write_reg(compressor->ctx, addr, value); 5884562236bSHarry Wentland 5894562236bSHarry Wentland /* Clear selection of Channel(s) containing Compressed Surface */ 5904562236bSHarry Wentland addr = mmGMCON_LPT_TARGET; 5914562236bSHarry Wentland value = dm_read_reg(compressor->ctx, addr); 5924562236bSHarry Wentland set_reg_field_value( 5934562236bSHarry Wentland value, 5944562236bSHarry Wentland 0xFFFFFFFF, 5954562236bSHarry Wentland GMCON_LPT_TARGET, 5964562236bSHarry Wentland STCTRL_LPT_TARGET); 5974562236bSHarry Wentland dm_write_reg(compressor->ctx, mmGMCON_LPT_TARGET, value); 5984562236bSHarry Wentland } 5994562236bSHarry Wentland 6004562236bSHarry Wentland void dce112_compressor_enable_lpt(struct compressor *compressor) 6014562236bSHarry Wentland { 6024562236bSHarry Wentland struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor); 6034562236bSHarry Wentland uint32_t value; 6044562236bSHarry Wentland uint32_t addr; 6054562236bSHarry Wentland uint32_t value_control; 6064562236bSHarry Wentland uint32_t channels; 6074562236bSHarry Wentland 6084562236bSHarry Wentland /* Enable LPT Stutter from Display pipe */ 6094562236bSHarry Wentland value = dm_read_reg(compressor->ctx, 6104562236bSHarry Wentland DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH)); 6114562236bSHarry Wentland set_reg_field_value( 6124562236bSHarry Wentland value, 6134562236bSHarry Wentland 1, 6144562236bSHarry Wentland DPG_PIPE_STUTTER_CONTROL_NONLPTCH, 6154562236bSHarry Wentland STUTTER_ENABLE_NONLPTCH); 6164562236bSHarry Wentland dm_write_reg(compressor->ctx, 6174562236bSHarry Wentland DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH), value); 6184562236bSHarry Wentland 6194562236bSHarry Wentland /* Enable Underlay pipe LPT Stutter */ 6204562236bSHarry Wentland addr = mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH; 6214562236bSHarry Wentland value = dm_read_reg(compressor->ctx, addr); 6224562236bSHarry Wentland set_reg_field_value( 6234562236bSHarry Wentland value, 6244562236bSHarry Wentland 1, 6254562236bSHarry Wentland DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH, 6264562236bSHarry Wentland STUTTER_ENABLE_NONLPTCH); 6274562236bSHarry Wentland dm_write_reg(compressor->ctx, addr, value); 6284562236bSHarry Wentland 6294562236bSHarry Wentland /* Selection of Channel(s) containing Compressed Surface: 0xfffffff 6304562236bSHarry Wentland * will disable LPT. 6314562236bSHarry Wentland * STCTRL_LPT_TARGETn corresponds to channel n. */ 6324562236bSHarry Wentland addr = mmLOW_POWER_TILING_CONTROL; 6334562236bSHarry Wentland value_control = dm_read_reg(compressor->ctx, addr); 6344562236bSHarry Wentland channels = get_reg_field_value(value_control, 6354562236bSHarry Wentland LOW_POWER_TILING_CONTROL, 6364562236bSHarry Wentland LOW_POWER_TILING_MODE); 6374562236bSHarry Wentland 6384562236bSHarry Wentland addr = mmGMCON_LPT_TARGET; 6394562236bSHarry Wentland value = dm_read_reg(compressor->ctx, addr); 6404562236bSHarry Wentland set_reg_field_value( 6414562236bSHarry Wentland value, 6424562236bSHarry Wentland channels + 1, /* not mentioned in programming guide, 6434562236bSHarry Wentland but follow DCE8.1 */ 6444562236bSHarry Wentland GMCON_LPT_TARGET, 6454562236bSHarry Wentland STCTRL_LPT_TARGET); 6464562236bSHarry Wentland dm_write_reg(compressor->ctx, addr, value); 6474562236bSHarry Wentland 6484562236bSHarry Wentland /* Enable LPT */ 6494562236bSHarry Wentland addr = mmLOW_POWER_TILING_CONTROL; 6504562236bSHarry Wentland value = dm_read_reg(compressor->ctx, addr); 6514562236bSHarry Wentland set_reg_field_value( 6524562236bSHarry Wentland value, 6534562236bSHarry Wentland 1, 6544562236bSHarry Wentland LOW_POWER_TILING_CONTROL, 6554562236bSHarry Wentland LOW_POWER_TILING_ENABLE); 6564562236bSHarry Wentland dm_write_reg(compressor->ctx, addr, value); 6574562236bSHarry Wentland } 6584562236bSHarry Wentland 6594562236bSHarry Wentland void dce112_compressor_program_lpt_control( 6604562236bSHarry Wentland struct compressor *compressor, 6614562236bSHarry Wentland struct compr_addr_and_pitch_params *params) 6624562236bSHarry Wentland { 6634562236bSHarry Wentland struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor); 6644562236bSHarry Wentland uint32_t rows_per_channel; 6654562236bSHarry Wentland uint32_t lpt_alignment; 6664562236bSHarry Wentland uint32_t source_view_width; 6674562236bSHarry Wentland uint32_t source_view_height; 6684562236bSHarry Wentland uint32_t lpt_control = 0; 6694562236bSHarry Wentland 6704562236bSHarry Wentland if (!compressor->options.bits.LPT_SUPPORT) 6714562236bSHarry Wentland return; 6724562236bSHarry Wentland 6734562236bSHarry Wentland lpt_control = dm_read_reg(compressor->ctx, 6744562236bSHarry Wentland mmLOW_POWER_TILING_CONTROL); 6754562236bSHarry Wentland 6764562236bSHarry Wentland /* POSSIBLE VALUES for Low Power Tiling Mode: 6774562236bSHarry Wentland * 00 - Use channel 0 6784562236bSHarry Wentland * 01 - Use Channel 0 and 1 6794562236bSHarry Wentland * 02 - Use Channel 0,1,2,3 6804562236bSHarry Wentland * 03 - reserved */ 6814562236bSHarry Wentland switch (compressor->lpt_channels_num) { 6824562236bSHarry Wentland /* case 2: 6834562236bSHarry Wentland * Use Channel 0 & 1 / Not used for DCE 11 */ 6844562236bSHarry Wentland case 1: 6854562236bSHarry Wentland /*Use Channel 0 for LPT for DCE 11 */ 6864562236bSHarry Wentland set_reg_field_value( 6874562236bSHarry Wentland lpt_control, 6884562236bSHarry Wentland 0, 6894562236bSHarry Wentland LOW_POWER_TILING_CONTROL, 6904562236bSHarry Wentland LOW_POWER_TILING_MODE); 6914562236bSHarry Wentland break; 6924562236bSHarry Wentland default: 6934562236bSHarry Wentland dm_logger_write( 6944562236bSHarry Wentland compressor->ctx->logger, LOG_WARNING, 6954562236bSHarry Wentland "%s: Invalid selected DRAM channels for LPT!!!", 6964562236bSHarry Wentland __func__); 6974562236bSHarry Wentland break; 6984562236bSHarry Wentland } 6994562236bSHarry Wentland 7004562236bSHarry Wentland lpt_control = lpt_memory_control_config(cp110, lpt_control); 7014562236bSHarry Wentland 7024562236bSHarry Wentland /* Program LOW_POWER_TILING_ROWS_PER_CHAN field which depends on 7034562236bSHarry Wentland * FBC compressed surface pitch. 7044562236bSHarry Wentland * LOW_POWER_TILING_ROWS_PER_CHAN = Roundup ((Surface Height * 7054562236bSHarry Wentland * Surface Pitch) / (Row Size * Number of Channels * 7064562236bSHarry Wentland * Number of Banks)). */ 7074562236bSHarry Wentland rows_per_channel = 0; 7084562236bSHarry Wentland lpt_alignment = lpt_size_alignment(cp110); 7094562236bSHarry Wentland source_view_width = 7104562236bSHarry Wentland align_to_chunks_number_per_line( 7114562236bSHarry Wentland cp110, 7124562236bSHarry Wentland params->source_view_width); 7134562236bSHarry Wentland source_view_height = (params->source_view_height + 1) & (~0x1); 7144562236bSHarry Wentland 7154562236bSHarry Wentland if (lpt_alignment != 0) { 7164562236bSHarry Wentland rows_per_channel = source_view_width * source_view_height * 4; 7174562236bSHarry Wentland rows_per_channel = 7184562236bSHarry Wentland (rows_per_channel % lpt_alignment) ? 7194562236bSHarry Wentland (rows_per_channel / lpt_alignment + 1) : 7204562236bSHarry Wentland rows_per_channel / lpt_alignment; 7214562236bSHarry Wentland } 7224562236bSHarry Wentland 7234562236bSHarry Wentland set_reg_field_value( 7244562236bSHarry Wentland lpt_control, 7254562236bSHarry Wentland rows_per_channel, 7264562236bSHarry Wentland LOW_POWER_TILING_CONTROL, 7274562236bSHarry Wentland LOW_POWER_TILING_ROWS_PER_CHAN); 7284562236bSHarry Wentland 7294562236bSHarry Wentland dm_write_reg(compressor->ctx, 7304562236bSHarry Wentland mmLOW_POWER_TILING_CONTROL, lpt_control); 7314562236bSHarry Wentland } 7324562236bSHarry Wentland 7334562236bSHarry Wentland /* 7344562236bSHarry Wentland * DCE 11 Frame Buffer Compression Implementation 7354562236bSHarry Wentland */ 7364562236bSHarry Wentland 7374562236bSHarry Wentland void dce112_compressor_set_fbc_invalidation_triggers( 7384562236bSHarry Wentland struct compressor *compressor, 7394562236bSHarry Wentland uint32_t fbc_trigger) 7404562236bSHarry Wentland { 7414562236bSHarry Wentland /* Disable region hit event, FBC_MEMORY_REGION_MASK = 0 (bits 16-19) 7424562236bSHarry Wentland * for DCE 11 regions cannot be used - does not work with S/G 7434562236bSHarry Wentland */ 7444562236bSHarry Wentland uint32_t addr = mmFBC_CLIENT_REGION_MASK; 7454562236bSHarry Wentland uint32_t value = dm_read_reg(compressor->ctx, addr); 7464562236bSHarry Wentland 7474562236bSHarry Wentland set_reg_field_value( 7484562236bSHarry Wentland value, 7494562236bSHarry Wentland 0, 7504562236bSHarry Wentland FBC_CLIENT_REGION_MASK, 7514562236bSHarry Wentland FBC_MEMORY_REGION_MASK); 7524562236bSHarry Wentland dm_write_reg(compressor->ctx, addr, value); 7534562236bSHarry Wentland 7544562236bSHarry Wentland /* Setup events when to clear all CSM entries (effectively marking 7554562236bSHarry Wentland * current compressed data invalid) 7564562236bSHarry Wentland * For DCE 11 CSM metadata 11111 means - "Not Compressed" 7574562236bSHarry Wentland * Used as the initial value of the metadata sent to the compressor 7584562236bSHarry Wentland * after invalidation, to indicate that the compressor should attempt 7594562236bSHarry Wentland * to compress all chunks on the current pass. Also used when the chunk 7604562236bSHarry Wentland * is not successfully written to memory. 7614562236bSHarry Wentland * When this CSM value is detected, FBC reads from the uncompressed 7624562236bSHarry Wentland * buffer. Set events according to passed in value, these events are 7634562236bSHarry Wentland * valid for DCE11: 7644562236bSHarry Wentland * - bit 0 - display register updated 7654562236bSHarry Wentland * - bit 28 - memory write from any client except from MCIF 7664562236bSHarry Wentland * - bit 29 - CG static screen signal is inactive 7674562236bSHarry Wentland * In addition, DCE11.1 also needs to set new DCE11.1 specific events 7684562236bSHarry Wentland * that are used to trigger invalidation on certain register changes, 7694562236bSHarry Wentland * for example enabling of Alpha Compression may trigger invalidation of 7704562236bSHarry Wentland * FBC once bit is set. These events are as follows: 7714562236bSHarry Wentland * - Bit 2 - FBC_GRPH_COMP_EN register updated 7724562236bSHarry Wentland * - Bit 3 - FBC_SRC_SEL register updated 7734562236bSHarry Wentland * - Bit 4 - FBC_MIN_COMPRESSION register updated 7744562236bSHarry Wentland * - Bit 5 - FBC_ALPHA_COMP_EN register updated 7754562236bSHarry Wentland * - Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated 7764562236bSHarry Wentland * - Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated 7774562236bSHarry Wentland */ 7784562236bSHarry Wentland addr = mmFBC_IDLE_FORCE_CLEAR_MASK; 7794562236bSHarry Wentland value = dm_read_reg(compressor->ctx, addr); 7804562236bSHarry Wentland set_reg_field_value( 7814562236bSHarry Wentland value, 7824562236bSHarry Wentland fbc_trigger | 7834562236bSHarry Wentland FBC_IDLE_FORCE_GRPH_COMP_EN | 7844562236bSHarry Wentland FBC_IDLE_FORCE_SRC_SEL_CHANGE | 7854562236bSHarry Wentland FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE | 7864562236bSHarry Wentland FBC_IDLE_FORCE_ALPHA_COMP_EN | 7874562236bSHarry Wentland FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN | 7884562236bSHarry Wentland FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF, 7894562236bSHarry Wentland FBC_IDLE_FORCE_CLEAR_MASK, 7904562236bSHarry Wentland FBC_IDLE_FORCE_CLEAR_MASK); 7914562236bSHarry Wentland dm_write_reg(compressor->ctx, addr, value); 7924562236bSHarry Wentland } 7934562236bSHarry Wentland 7944562236bSHarry Wentland bool dce112_compressor_construct(struct dce112_compressor *compressor, 7954562236bSHarry Wentland struct dc_context *ctx) 7964562236bSHarry Wentland { 7974562236bSHarry Wentland struct dc_bios *bp = ctx->dc_bios; 7984562236bSHarry Wentland struct embedded_panel_info panel_info; 7994562236bSHarry Wentland 80072f0281dSRoman Li compressor->base.options.raw = 0; 8014562236bSHarry Wentland compressor->base.options.bits.FBC_SUPPORT = true; 8024562236bSHarry Wentland compressor->base.options.bits.LPT_SUPPORT = true; 8034562236bSHarry Wentland /* For DCE 11 always use one DRAM channel for LPT */ 8044562236bSHarry Wentland compressor->base.lpt_channels_num = 1; 8054562236bSHarry Wentland compressor->base.options.bits.DUMMY_BACKEND = false; 8064562236bSHarry Wentland 8074562236bSHarry Wentland /* Check if this system has more than 1 DRAM channel; if only 1 then LPT 8084562236bSHarry Wentland * should not be supported */ 8094562236bSHarry Wentland if (compressor->base.memory_bus_width == 64) 8104562236bSHarry Wentland compressor->base.options.bits.LPT_SUPPORT = false; 8114562236bSHarry Wentland 8124562236bSHarry Wentland compressor->base.options.bits.CLK_GATING_DISABLED = false; 8134562236bSHarry Wentland 8144562236bSHarry Wentland compressor->base.ctx = ctx; 8154562236bSHarry Wentland compressor->base.embedded_panel_h_size = 0; 8164562236bSHarry Wentland compressor->base.embedded_panel_v_size = 0; 8174562236bSHarry Wentland compressor->base.memory_bus_width = ctx->asic_id.vram_width; 8184562236bSHarry Wentland compressor->base.allocated_size = 0; 8194562236bSHarry Wentland compressor->base.preferred_requested_size = 0; 8204562236bSHarry Wentland compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID; 8214562236bSHarry Wentland compressor->base.banks_num = 0; 8224562236bSHarry Wentland compressor->base.raw_size = 0; 8234562236bSHarry Wentland compressor->base.channel_interleave_size = 0; 8244562236bSHarry Wentland compressor->base.dram_channels_num = 0; 8254562236bSHarry Wentland compressor->base.lpt_channels_num = 0; 8264562236bSHarry Wentland compressor->base.attached_inst = 0; 8274562236bSHarry Wentland compressor->base.is_enabled = false; 8284562236bSHarry Wentland 8294562236bSHarry Wentland if (BP_RESULT_OK == 8304562236bSHarry Wentland bp->funcs->get_embedded_panel_info(bp, &panel_info)) { 8314562236bSHarry Wentland compressor->base.embedded_panel_h_size = 8324562236bSHarry Wentland panel_info.lcd_timing.horizontal_addressable; 8334562236bSHarry Wentland compressor->base.embedded_panel_v_size = 8344562236bSHarry Wentland panel_info.lcd_timing.vertical_addressable; 8354562236bSHarry Wentland } 8364562236bSHarry Wentland return true; 8374562236bSHarry Wentland } 8384562236bSHarry Wentland 8394562236bSHarry Wentland struct compressor *dce112_compressor_create(struct dc_context *ctx) 8404562236bSHarry Wentland { 8414562236bSHarry Wentland struct dce112_compressor *cp110 = 8424562236bSHarry Wentland dm_alloc(sizeof(struct dce112_compressor)); 8434562236bSHarry Wentland 8444562236bSHarry Wentland if (!cp110) 8454562236bSHarry Wentland return NULL; 8464562236bSHarry Wentland 8474562236bSHarry Wentland if (dce112_compressor_construct(cp110, ctx)) 8484562236bSHarry Wentland return &cp110->base; 8494562236bSHarry Wentland 8504562236bSHarry Wentland BREAK_TO_DEBUGGER(); 8514562236bSHarry Wentland dm_free(cp110); 8524562236bSHarry Wentland return NULL; 8534562236bSHarry Wentland } 8544562236bSHarry Wentland 8554562236bSHarry Wentland void dce112_compressor_destroy(struct compressor **compressor) 8564562236bSHarry Wentland { 8574562236bSHarry Wentland dm_free(TO_DCE112_COMPRESSOR(*compressor)); 8584562236bSHarry Wentland *compressor = NULL; 8594562236bSHarry Wentland } 860