1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "link_encoder.h" 29 #include "stream_encoder.h" 30 31 #include "resource.h" 32 #include "dce110/dce110_resource.h" 33 34 #include "include/irq_service_interface.h" 35 #include "dce/dce_audio.h" 36 #include "dce110/dce110_timing_generator.h" 37 #include "irq/dce110/irq_service_dce110.h" 38 #include "dce110/dce110_timing_generator_v.h" 39 #include "dce/dce_link_encoder.h" 40 #include "dce/dce_stream_encoder.h" 41 #include "dce/dce_mem_input.h" 42 #include "dce110/dce110_mem_input_v.h" 43 #include "dce/dce_ipp.h" 44 #include "dce/dce_transform.h" 45 #include "dce110/dce110_transform_v.h" 46 #include "dce/dce_opp.h" 47 #include "dce110/dce110_opp_v.h" 48 #include "dce/dce_clocks.h" 49 #include "dce/dce_clock_source.h" 50 #include "dce/dce_hwseq.h" 51 #include "dce110/dce110_hw_sequencer.h" 52 #include "dce/dce_aux.h" 53 #include "dce/dce_abm.h" 54 #include "dce/dce_dmcu.h" 55 #include "dce/dce_i2c.h" 56 57 #define DC_LOGGER \ 58 dc->ctx->logger 59 60 #include "dce110/dce110_compressor.h" 61 62 #include "reg_helper.h" 63 64 #include "dce/dce_11_0_d.h" 65 #include "dce/dce_11_0_sh_mask.h" 66 67 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 68 #include "gmc/gmc_8_2_d.h" 69 #include "gmc/gmc_8_2_sh_mask.h" 70 #endif 71 72 #ifndef mmDP_DPHY_INTERNAL_CTRL 73 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 74 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 75 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 76 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 77 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 78 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 79 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 80 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 81 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 82 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 83 #endif 84 85 #ifndef mmBIOS_SCRATCH_2 86 #define mmBIOS_SCRATCH_2 0x05CB 87 #define mmBIOS_SCRATCH_6 0x05CF 88 #endif 89 90 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 91 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 92 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 93 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 94 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 95 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 96 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 97 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 98 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 99 #endif 100 101 #ifndef mmDP_DPHY_FAST_TRAINING 102 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 103 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 104 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 105 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 106 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 107 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 108 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 109 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 110 #endif 111 112 #ifndef DPHY_RX_FAST_TRAINING_CAPABLE 113 #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1 114 #endif 115 116 static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = { 117 { 118 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 119 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 120 }, 121 { 122 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 123 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 124 }, 125 { 126 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 127 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 128 }, 129 { 130 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 131 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 132 }, 133 { 134 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 135 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 136 }, 137 { 138 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 139 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 140 } 141 }; 142 143 /* set register offset */ 144 #define SR(reg_name)\ 145 .reg_name = mm ## reg_name 146 147 /* set register offset with instance */ 148 #define SRI(reg_name, block, id)\ 149 .reg_name = mm ## block ## id ## _ ## reg_name 150 151 static const struct dccg_registers disp_clk_regs = { 152 CLK_COMMON_REG_LIST_DCE_BASE() 153 }; 154 155 static const struct dccg_shift disp_clk_shift = { 156 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 157 }; 158 159 static const struct dccg_mask disp_clk_mask = { 160 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 161 }; 162 163 static const struct dce_dmcu_registers dmcu_regs = { 164 DMCU_DCE110_COMMON_REG_LIST() 165 }; 166 167 static const struct dce_dmcu_shift dmcu_shift = { 168 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 169 }; 170 171 static const struct dce_dmcu_mask dmcu_mask = { 172 DMCU_MASK_SH_LIST_DCE110(_MASK) 173 }; 174 175 static const struct dce_abm_registers abm_regs = { 176 ABM_DCE110_COMMON_REG_LIST() 177 }; 178 179 static const struct dce_abm_shift abm_shift = { 180 ABM_MASK_SH_LIST_DCE110(__SHIFT) 181 }; 182 183 static const struct dce_abm_mask abm_mask = { 184 ABM_MASK_SH_LIST_DCE110(_MASK) 185 }; 186 187 #define ipp_regs(id)\ 188 [id] = {\ 189 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 190 } 191 192 static const struct dce_ipp_registers ipp_regs[] = { 193 ipp_regs(0), 194 ipp_regs(1), 195 ipp_regs(2) 196 }; 197 198 static const struct dce_ipp_shift ipp_shift = { 199 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 200 }; 201 202 static const struct dce_ipp_mask ipp_mask = { 203 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 204 }; 205 206 #define transform_regs(id)\ 207 [id] = {\ 208 XFM_COMMON_REG_LIST_DCE110(id)\ 209 } 210 211 static const struct dce_transform_registers xfm_regs[] = { 212 transform_regs(0), 213 transform_regs(1), 214 transform_regs(2) 215 }; 216 217 static const struct dce_transform_shift xfm_shift = { 218 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 219 }; 220 221 static const struct dce_transform_mask xfm_mask = { 222 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 223 }; 224 225 #define aux_regs(id)\ 226 [id] = {\ 227 AUX_REG_LIST(id)\ 228 } 229 230 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 231 aux_regs(0), 232 aux_regs(1), 233 aux_regs(2), 234 aux_regs(3), 235 aux_regs(4), 236 aux_regs(5) 237 }; 238 239 #define hpd_regs(id)\ 240 [id] = {\ 241 HPD_REG_LIST(id)\ 242 } 243 244 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 245 hpd_regs(0), 246 hpd_regs(1), 247 hpd_regs(2), 248 hpd_regs(3), 249 hpd_regs(4), 250 hpd_regs(5) 251 }; 252 253 254 #define link_regs(id)\ 255 [id] = {\ 256 LE_DCE110_REG_LIST(id)\ 257 } 258 259 static const struct dce110_link_enc_registers link_enc_regs[] = { 260 link_regs(0), 261 link_regs(1), 262 link_regs(2), 263 link_regs(3), 264 link_regs(4), 265 link_regs(5), 266 link_regs(6), 267 }; 268 269 #define stream_enc_regs(id)\ 270 [id] = {\ 271 SE_COMMON_REG_LIST(id),\ 272 .TMDS_CNTL = 0,\ 273 } 274 275 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 276 stream_enc_regs(0), 277 stream_enc_regs(1), 278 stream_enc_regs(2) 279 }; 280 281 static const struct dce_stream_encoder_shift se_shift = { 282 SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 283 }; 284 285 static const struct dce_stream_encoder_mask se_mask = { 286 SE_COMMON_MASK_SH_LIST_DCE110(_MASK) 287 }; 288 289 #define opp_regs(id)\ 290 [id] = {\ 291 OPP_DCE_110_REG_LIST(id),\ 292 } 293 294 static const struct dce_opp_registers opp_regs[] = { 295 opp_regs(0), 296 opp_regs(1), 297 opp_regs(2), 298 opp_regs(3), 299 opp_regs(4), 300 opp_regs(5) 301 }; 302 303 static const struct dce_opp_shift opp_shift = { 304 OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT) 305 }; 306 307 static const struct dce_opp_mask opp_mask = { 308 OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK) 309 }; 310 311 #define aux_engine_regs(id)\ 312 [id] = {\ 313 AUX_COMMON_REG_LIST(id), \ 314 .AUX_RESET_MASK = 0 \ 315 } 316 317 static const struct dce110_aux_registers aux_engine_regs[] = { 318 aux_engine_regs(0), 319 aux_engine_regs(1), 320 aux_engine_regs(2), 321 aux_engine_regs(3), 322 aux_engine_regs(4), 323 aux_engine_regs(5) 324 }; 325 326 #define audio_regs(id)\ 327 [id] = {\ 328 AUD_COMMON_REG_LIST(id)\ 329 } 330 331 static const struct dce_audio_registers audio_regs[] = { 332 audio_regs(0), 333 audio_regs(1), 334 audio_regs(2), 335 audio_regs(3), 336 audio_regs(4), 337 audio_regs(5), 338 audio_regs(6), 339 }; 340 341 static const struct dce_audio_shift audio_shift = { 342 AUD_COMMON_MASK_SH_LIST(__SHIFT) 343 }; 344 345 static const struct dce_aduio_mask audio_mask = { 346 AUD_COMMON_MASK_SH_LIST(_MASK) 347 }; 348 349 /* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */ 350 351 352 #define clk_src_regs(id)\ 353 [id] = {\ 354 CS_COMMON_REG_LIST_DCE_100_110(id),\ 355 } 356 357 static const struct dce110_clk_src_regs clk_src_regs[] = { 358 clk_src_regs(0), 359 clk_src_regs(1), 360 clk_src_regs(2) 361 }; 362 363 static const struct dce110_clk_src_shift cs_shift = { 364 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 365 }; 366 367 static const struct dce110_clk_src_mask cs_mask = { 368 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 369 }; 370 371 static const struct bios_registers bios_regs = { 372 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 373 }; 374 375 static const struct resource_caps carrizo_resource_cap = { 376 .num_timing_generator = 3, 377 .num_video_plane = 1, 378 .num_audio = 3, 379 .num_stream_encoder = 3, 380 .num_pll = 2, 381 .num_ddc = 3, 382 }; 383 384 static const struct resource_caps stoney_resource_cap = { 385 .num_timing_generator = 2, 386 .num_video_plane = 1, 387 .num_audio = 3, 388 .num_stream_encoder = 3, 389 .num_pll = 2, 390 .num_ddc = 3, 391 }; 392 393 #define CTX ctx 394 #define REG(reg) mm ## reg 395 396 #ifndef mmCC_DC_HDMI_STRAPS 397 #define mmCC_DC_HDMI_STRAPS 0x4819 398 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 399 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 400 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 401 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 402 #endif 403 404 static void read_dce_straps( 405 struct dc_context *ctx, 406 struct resource_straps *straps) 407 { 408 REG_GET_2(CC_DC_HDMI_STRAPS, 409 HDMI_DISABLE, &straps->hdmi_disable, 410 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 411 412 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 413 } 414 415 static struct audio *create_audio( 416 struct dc_context *ctx, unsigned int inst) 417 { 418 return dce_audio_create(ctx, inst, 419 &audio_regs[inst], &audio_shift, &audio_mask); 420 } 421 422 static struct timing_generator *dce110_timing_generator_create( 423 struct dc_context *ctx, 424 uint32_t instance, 425 const struct dce110_timing_generator_offsets *offsets) 426 { 427 struct dce110_timing_generator *tg110 = 428 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 429 430 if (!tg110) 431 return NULL; 432 433 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 434 return &tg110->base; 435 } 436 437 static struct stream_encoder *dce110_stream_encoder_create( 438 enum engine_id eng_id, 439 struct dc_context *ctx) 440 { 441 struct dce110_stream_encoder *enc110 = 442 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 443 444 if (!enc110) 445 return NULL; 446 447 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 448 &stream_enc_regs[eng_id], 449 &se_shift, &se_mask); 450 return &enc110->base; 451 } 452 453 #define SRII(reg_name, block, id)\ 454 .reg_name[id] = mm ## block ## id ## _ ## reg_name 455 456 static const struct dce_hwseq_registers hwseq_stoney_reg = { 457 HWSEQ_ST_REG_LIST() 458 }; 459 460 static const struct dce_hwseq_registers hwseq_cz_reg = { 461 HWSEQ_CZ_REG_LIST() 462 }; 463 464 static const struct dce_hwseq_shift hwseq_shift = { 465 HWSEQ_DCE11_MASK_SH_LIST(__SHIFT), 466 }; 467 468 static const struct dce_hwseq_mask hwseq_mask = { 469 HWSEQ_DCE11_MASK_SH_LIST(_MASK), 470 }; 471 472 static struct dce_hwseq *dce110_hwseq_create( 473 struct dc_context *ctx) 474 { 475 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 476 477 if (hws) { 478 hws->ctx = ctx; 479 hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ? 480 &hwseq_stoney_reg : &hwseq_cz_reg; 481 hws->shifts = &hwseq_shift; 482 hws->masks = &hwseq_mask; 483 hws->wa.blnd_crtc_trigger = true; 484 } 485 return hws; 486 } 487 488 static const struct resource_create_funcs res_create_funcs = { 489 .read_dce_straps = read_dce_straps, 490 .create_audio = create_audio, 491 .create_stream_encoder = dce110_stream_encoder_create, 492 .create_hwseq = dce110_hwseq_create, 493 }; 494 495 #define mi_inst_regs(id) { \ 496 MI_DCE11_REG_LIST(id), \ 497 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 498 } 499 static const struct dce_mem_input_registers mi_regs[] = { 500 mi_inst_regs(0), 501 mi_inst_regs(1), 502 mi_inst_regs(2), 503 }; 504 505 static const struct dce_mem_input_shift mi_shifts = { 506 MI_DCE11_MASK_SH_LIST(__SHIFT), 507 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 508 }; 509 510 static const struct dce_mem_input_mask mi_masks = { 511 MI_DCE11_MASK_SH_LIST(_MASK), 512 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 513 }; 514 515 516 static struct mem_input *dce110_mem_input_create( 517 struct dc_context *ctx, 518 uint32_t inst) 519 { 520 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 521 GFP_KERNEL); 522 523 if (!dce_mi) { 524 BREAK_TO_DEBUGGER(); 525 return NULL; 526 } 527 528 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 529 dce_mi->wa.single_head_rdreq_dmif_limit = 3; 530 return &dce_mi->base; 531 } 532 533 static void dce110_transform_destroy(struct transform **xfm) 534 { 535 kfree(TO_DCE_TRANSFORM(*xfm)); 536 *xfm = NULL; 537 } 538 539 static struct transform *dce110_transform_create( 540 struct dc_context *ctx, 541 uint32_t inst) 542 { 543 struct dce_transform *transform = 544 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 545 546 if (!transform) 547 return NULL; 548 549 dce_transform_construct(transform, ctx, inst, 550 &xfm_regs[inst], &xfm_shift, &xfm_mask); 551 return &transform->base; 552 } 553 554 static struct input_pixel_processor *dce110_ipp_create( 555 struct dc_context *ctx, uint32_t inst) 556 { 557 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 558 559 if (!ipp) { 560 BREAK_TO_DEBUGGER(); 561 return NULL; 562 } 563 564 dce_ipp_construct(ipp, ctx, inst, 565 &ipp_regs[inst], &ipp_shift, &ipp_mask); 566 return &ipp->base; 567 } 568 569 static const struct encoder_feature_support link_enc_feature = { 570 .max_hdmi_deep_color = COLOR_DEPTH_121212, 571 .max_hdmi_pixel_clock = 594000, 572 .flags.bits.IS_HBR2_CAPABLE = true, 573 .flags.bits.IS_TPS3_CAPABLE = true, 574 .flags.bits.IS_YCBCR_CAPABLE = true 575 }; 576 577 static struct link_encoder *dce110_link_encoder_create( 578 const struct encoder_init_data *enc_init_data) 579 { 580 struct dce110_link_encoder *enc110 = 581 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 582 583 if (!enc110) 584 return NULL; 585 586 dce110_link_encoder_construct(enc110, 587 enc_init_data, 588 &link_enc_feature, 589 &link_enc_regs[enc_init_data->transmitter], 590 &link_enc_aux_regs[enc_init_data->channel - 1], 591 &link_enc_hpd_regs[enc_init_data->hpd_source]); 592 return &enc110->base; 593 } 594 595 static struct output_pixel_processor *dce110_opp_create( 596 struct dc_context *ctx, 597 uint32_t inst) 598 { 599 struct dce110_opp *opp = 600 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 601 602 if (!opp) 603 return NULL; 604 605 dce110_opp_construct(opp, 606 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 607 return &opp->base; 608 } 609 610 struct aux_engine *dce110_aux_engine_create( 611 struct dc_context *ctx, 612 uint32_t inst) 613 { 614 struct aux_engine_dce110 *aux_engine = 615 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 616 617 if (!aux_engine) 618 return NULL; 619 620 dce110_aux_engine_construct(aux_engine, ctx, inst, 621 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 622 &aux_engine_regs[inst]); 623 624 return &aux_engine->base; 625 } 626 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 627 628 static const struct dce_i2c_registers i2c_hw_regs[] = { 629 i2c_inst_regs(1), 630 i2c_inst_regs(2), 631 i2c_inst_regs(3), 632 i2c_inst_regs(4), 633 i2c_inst_regs(5), 634 i2c_inst_regs(6), 635 }; 636 637 static const struct dce_i2c_shift i2c_shifts = { 638 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 639 }; 640 641 static const struct dce_i2c_mask i2c_masks = { 642 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 643 }; 644 645 struct dce_i2c_hw *dce110_i2c_hw_create( 646 struct dc_context *ctx, 647 uint32_t inst) 648 { 649 struct dce_i2c_hw *dce_i2c_hw = 650 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 651 652 if (!dce_i2c_hw) 653 return NULL; 654 655 dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst, 656 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 657 658 return dce_i2c_hw; 659 } 660 struct clock_source *dce110_clock_source_create( 661 struct dc_context *ctx, 662 struct dc_bios *bios, 663 enum clock_source_id id, 664 const struct dce110_clk_src_regs *regs, 665 bool dp_clk_src) 666 { 667 struct dce110_clk_src *clk_src = 668 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 669 670 if (!clk_src) 671 return NULL; 672 673 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 674 regs, &cs_shift, &cs_mask)) { 675 clk_src->base.dp_clk_src = dp_clk_src; 676 return &clk_src->base; 677 } 678 679 BREAK_TO_DEBUGGER(); 680 return NULL; 681 } 682 683 void dce110_clock_source_destroy(struct clock_source **clk_src) 684 { 685 struct dce110_clk_src *dce110_clk_src; 686 687 if (!clk_src) 688 return; 689 690 dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src); 691 692 kfree(dce110_clk_src->dp_ss_params); 693 kfree(dce110_clk_src->hdmi_ss_params); 694 kfree(dce110_clk_src->dvi_ss_params); 695 696 kfree(dce110_clk_src); 697 *clk_src = NULL; 698 } 699 700 static void destruct(struct dce110_resource_pool *pool) 701 { 702 unsigned int i; 703 704 for (i = 0; i < pool->base.pipe_count; i++) { 705 if (pool->base.opps[i] != NULL) 706 dce110_opp_destroy(&pool->base.opps[i]); 707 708 if (pool->base.transforms[i] != NULL) 709 dce110_transform_destroy(&pool->base.transforms[i]); 710 711 if (pool->base.ipps[i] != NULL) 712 dce_ipp_destroy(&pool->base.ipps[i]); 713 714 if (pool->base.mis[i] != NULL) { 715 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 716 pool->base.mis[i] = NULL; 717 } 718 719 if (pool->base.timing_generators[i] != NULL) { 720 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 721 pool->base.timing_generators[i] = NULL; 722 } 723 724 if (pool->base.engines[i] != NULL) 725 dce110_engine_destroy(&pool->base.engines[i]); 726 if (pool->base.hw_i2cs[i] != NULL) { 727 kfree(pool->base.hw_i2cs[i]); 728 pool->base.hw_i2cs[i] = NULL; 729 } 730 if (pool->base.sw_i2cs[i] != NULL) { 731 kfree(pool->base.sw_i2cs[i]); 732 pool->base.sw_i2cs[i] = NULL; 733 } 734 } 735 736 for (i = 0; i < pool->base.stream_enc_count; i++) { 737 if (pool->base.stream_enc[i] != NULL) 738 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 739 } 740 741 for (i = 0; i < pool->base.clk_src_count; i++) { 742 if (pool->base.clock_sources[i] != NULL) { 743 dce110_clock_source_destroy(&pool->base.clock_sources[i]); 744 } 745 } 746 747 if (pool->base.dp_clock_source != NULL) 748 dce110_clock_source_destroy(&pool->base.dp_clock_source); 749 750 for (i = 0; i < pool->base.audio_count; i++) { 751 if (pool->base.audios[i] != NULL) { 752 dce_aud_destroy(&pool->base.audios[i]); 753 } 754 } 755 756 if (pool->base.abm != NULL) 757 dce_abm_destroy(&pool->base.abm); 758 759 if (pool->base.dmcu != NULL) 760 dce_dmcu_destroy(&pool->base.dmcu); 761 762 if (pool->base.dccg != NULL) 763 dce_dccg_destroy(&pool->base.dccg); 764 765 if (pool->base.irqs != NULL) { 766 dal_irq_service_destroy(&pool->base.irqs); 767 } 768 } 769 770 771 static void get_pixel_clock_parameters( 772 const struct pipe_ctx *pipe_ctx, 773 struct pixel_clk_params *pixel_clk_params) 774 { 775 const struct dc_stream_state *stream = pipe_ctx->stream; 776 777 /*TODO: is this halved for YCbCr 420? in that case we might want to move 778 * the pixel clock normalization for hdmi up to here instead of doing it 779 * in pll_adjust_pix_clk 780 */ 781 pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz; 782 pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id; 783 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 784 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 785 /* TODO: un-hardcode*/ 786 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 787 LINK_RATE_REF_FREQ_IN_KHZ; 788 pixel_clk_params->flags.ENABLE_SS = 0; 789 pixel_clk_params->color_depth = 790 stream->timing.display_color_depth; 791 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 792 pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding == 793 PIXEL_ENCODING_YCBCR420); 794 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 795 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) { 796 pixel_clk_params->color_depth = COLOR_DEPTH_888; 797 } 798 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 799 pixel_clk_params->requested_pix_clk = pixel_clk_params->requested_pix_clk / 2; 800 } 801 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 802 pixel_clk_params->requested_pix_clk *= 2; 803 804 } 805 806 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 807 { 808 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 809 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 810 pipe_ctx->clock_source, 811 &pipe_ctx->stream_res.pix_clk_params, 812 &pipe_ctx->pll_settings); 813 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 814 &pipe_ctx->stream->bit_depth_params); 815 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 816 } 817 818 static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx) 819 { 820 if (pipe_ctx->pipe_idx != underlay_idx) 821 return true; 822 if (!pipe_ctx->plane_state) 823 return false; 824 if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 825 return false; 826 return true; 827 } 828 829 static enum dc_status build_mapped_resource( 830 const struct dc *dc, 831 struct dc_state *context, 832 struct dc_stream_state *stream) 833 { 834 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 835 836 if (!pipe_ctx) 837 return DC_ERROR_UNEXPECTED; 838 839 if (!is_surface_pixel_format_supported(pipe_ctx, 840 dc->res_pool->underlay_pipe_index)) 841 return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; 842 843 dce110_resource_build_pipe_hw_param(pipe_ctx); 844 845 /* TODO: validate audio ASIC caps, encoder */ 846 847 resource_build_info_frame(pipe_ctx); 848 849 return DC_OK; 850 } 851 852 static bool dce110_validate_bandwidth( 853 struct dc *dc, 854 struct dc_state *context) 855 { 856 bool result = false; 857 858 DC_LOG_BANDWIDTH_CALCS( 859 "%s: start", 860 __func__); 861 862 if (bw_calcs( 863 dc->ctx, 864 dc->bw_dceip, 865 dc->bw_vbios, 866 context->res_ctx.pipe_ctx, 867 dc->res_pool->pipe_count, 868 &context->bw.dce)) 869 result = true; 870 871 if (!result) 872 DC_LOG_BANDWIDTH_VALIDATION("%s: %dx%d@%d Bandwidth validation failed!\n", 873 __func__, 874 context->streams[0]->timing.h_addressable, 875 context->streams[0]->timing.v_addressable, 876 context->streams[0]->timing.pix_clk_khz); 877 878 if (memcmp(&dc->current_state->bw.dce, 879 &context->bw.dce, sizeof(context->bw.dce))) { 880 881 DC_LOG_BANDWIDTH_CALCS( 882 "%s: finish,\n" 883 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 884 "stutMark_b: %d stutMark_a: %d\n" 885 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 886 "stutMark_b: %d stutMark_a: %d\n" 887 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 888 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n" 889 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" 890 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n" 891 , 892 __func__, 893 context->bw.dce.nbp_state_change_wm_ns[0].b_mark, 894 context->bw.dce.nbp_state_change_wm_ns[0].a_mark, 895 context->bw.dce.urgent_wm_ns[0].b_mark, 896 context->bw.dce.urgent_wm_ns[0].a_mark, 897 context->bw.dce.stutter_exit_wm_ns[0].b_mark, 898 context->bw.dce.stutter_exit_wm_ns[0].a_mark, 899 context->bw.dce.nbp_state_change_wm_ns[1].b_mark, 900 context->bw.dce.nbp_state_change_wm_ns[1].a_mark, 901 context->bw.dce.urgent_wm_ns[1].b_mark, 902 context->bw.dce.urgent_wm_ns[1].a_mark, 903 context->bw.dce.stutter_exit_wm_ns[1].b_mark, 904 context->bw.dce.stutter_exit_wm_ns[1].a_mark, 905 context->bw.dce.nbp_state_change_wm_ns[2].b_mark, 906 context->bw.dce.nbp_state_change_wm_ns[2].a_mark, 907 context->bw.dce.urgent_wm_ns[2].b_mark, 908 context->bw.dce.urgent_wm_ns[2].a_mark, 909 context->bw.dce.stutter_exit_wm_ns[2].b_mark, 910 context->bw.dce.stutter_exit_wm_ns[2].a_mark, 911 context->bw.dce.stutter_mode_enable, 912 context->bw.dce.cpuc_state_change_enable, 913 context->bw.dce.cpup_state_change_enable, 914 context->bw.dce.nbp_state_change_enable, 915 context->bw.dce.all_displays_in_sync, 916 context->bw.dce.dispclk_khz, 917 context->bw.dce.sclk_khz, 918 context->bw.dce.sclk_deep_sleep_khz, 919 context->bw.dce.yclk_khz, 920 context->bw.dce.blackout_recovery_time_us); 921 } 922 return result; 923 } 924 925 enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state, 926 struct dc_caps *caps) 927 { 928 if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) || 929 ((plane_state->dst_rect.height * 2) < plane_state->src_rect.height)) 930 return DC_FAIL_SURFACE_VALIDATE; 931 932 return DC_OK; 933 } 934 935 static bool dce110_validate_surface_sets( 936 struct dc_state *context) 937 { 938 int i, j; 939 940 for (i = 0; i < context->stream_count; i++) { 941 if (context->stream_status[i].plane_count == 0) 942 continue; 943 944 if (context->stream_status[i].plane_count > 2) 945 return false; 946 947 for (j = 0; j < context->stream_status[i].plane_count; j++) { 948 struct dc_plane_state *plane = 949 context->stream_status[i].plane_states[j]; 950 951 /* underlay validation */ 952 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 953 954 if ((plane->src_rect.width > 1920 || 955 plane->src_rect.height > 1080)) 956 return false; 957 958 /* we don't have the logic to support underlay 959 * only yet so block the use case where we get 960 * NV12 plane as top layer 961 */ 962 if (j == 0) 963 return false; 964 965 /* irrespective of plane format, 966 * stream should be RGB encoded 967 */ 968 if (context->streams[i]->timing.pixel_encoding 969 != PIXEL_ENCODING_RGB) 970 return false; 971 972 } 973 974 } 975 } 976 977 return true; 978 } 979 980 enum dc_status dce110_validate_global( 981 struct dc *dc, 982 struct dc_state *context) 983 { 984 if (!dce110_validate_surface_sets(context)) 985 return DC_FAIL_SURFACE_VALIDATE; 986 987 return DC_OK; 988 } 989 990 static enum dc_status dce110_add_stream_to_ctx( 991 struct dc *dc, 992 struct dc_state *new_ctx, 993 struct dc_stream_state *dc_stream) 994 { 995 enum dc_status result = DC_ERROR_UNEXPECTED; 996 997 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 998 999 if (result == DC_OK) 1000 result = resource_map_clock_resources(dc, new_ctx, dc_stream); 1001 1002 1003 if (result == DC_OK) 1004 result = build_mapped_resource(dc, new_ctx, dc_stream); 1005 1006 return result; 1007 } 1008 1009 static struct pipe_ctx *dce110_acquire_underlay( 1010 struct dc_state *context, 1011 const struct resource_pool *pool, 1012 struct dc_stream_state *stream) 1013 { 1014 struct dc *dc = stream->ctx->dc; 1015 struct resource_context *res_ctx = &context->res_ctx; 1016 unsigned int underlay_idx = pool->underlay_pipe_index; 1017 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; 1018 1019 if (res_ctx->pipe_ctx[underlay_idx].stream) 1020 return NULL; 1021 1022 pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx]; 1023 pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; 1024 /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/ 1025 pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; 1026 pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; 1027 pipe_ctx->pipe_idx = underlay_idx; 1028 1029 pipe_ctx->stream = stream; 1030 1031 if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) { 1032 struct tg_color black_color = {0}; 1033 struct dc_bios *dcb = dc->ctx->dc_bios; 1034 1035 dc->hwss.enable_display_power_gating( 1036 dc, 1037 pipe_ctx->stream_res.tg->inst, 1038 dcb, PIPE_GATING_CONTROL_DISABLE); 1039 1040 /* 1041 * This is for powering on underlay, so crtc does not 1042 * need to be enabled 1043 */ 1044 1045 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg, 1046 &stream->timing, 1047 false); 1048 1049 pipe_ctx->stream_res.tg->funcs->enable_advanced_request( 1050 pipe_ctx->stream_res.tg, 1051 true, 1052 &stream->timing); 1053 1054 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi, 1055 stream->timing.h_total, 1056 stream->timing.v_total, 1057 stream->timing.pix_clk_khz, 1058 context->stream_count); 1059 1060 color_space_to_black_color(dc, 1061 COLOR_SPACE_YCBCR601, &black_color); 1062 pipe_ctx->stream_res.tg->funcs->set_blank_color( 1063 pipe_ctx->stream_res.tg, 1064 &black_color); 1065 } 1066 1067 return pipe_ctx; 1068 } 1069 1070 static void dce110_destroy_resource_pool(struct resource_pool **pool) 1071 { 1072 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 1073 1074 destruct(dce110_pool); 1075 kfree(dce110_pool); 1076 *pool = NULL; 1077 } 1078 1079 1080 static const struct resource_funcs dce110_res_pool_funcs = { 1081 .destroy = dce110_destroy_resource_pool, 1082 .link_enc_create = dce110_link_encoder_create, 1083 .validate_bandwidth = dce110_validate_bandwidth, 1084 .validate_plane = dce110_validate_plane, 1085 .acquire_idle_pipe_for_layer = dce110_acquire_underlay, 1086 .add_stream_to_ctx = dce110_add_stream_to_ctx, 1087 .validate_global = dce110_validate_global 1088 }; 1089 1090 static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) 1091 { 1092 struct dce110_timing_generator *dce110_tgv = kzalloc(sizeof(*dce110_tgv), 1093 GFP_KERNEL); 1094 struct dce_transform *dce110_xfmv = kzalloc(sizeof(*dce110_xfmv), 1095 GFP_KERNEL); 1096 struct dce_mem_input *dce110_miv = kzalloc(sizeof(*dce110_miv), 1097 GFP_KERNEL); 1098 struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv), 1099 GFP_KERNEL); 1100 1101 if (!dce110_tgv || !dce110_xfmv || !dce110_miv || !dce110_oppv) { 1102 kfree(dce110_tgv); 1103 kfree(dce110_xfmv); 1104 kfree(dce110_miv); 1105 kfree(dce110_oppv); 1106 return false; 1107 } 1108 1109 dce110_opp_v_construct(dce110_oppv, ctx); 1110 1111 dce110_timing_generator_v_construct(dce110_tgv, ctx); 1112 dce110_mem_input_v_construct(dce110_miv, ctx); 1113 dce110_transform_v_construct(dce110_xfmv, ctx); 1114 1115 pool->opps[pool->pipe_count] = &dce110_oppv->base; 1116 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; 1117 pool->mis[pool->pipe_count] = &dce110_miv->base; 1118 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; 1119 pool->pipe_count++; 1120 1121 /* update the public caps to indicate an underlay is available */ 1122 ctx->dc->caps.max_slave_planes = 1; 1123 ctx->dc->caps.max_slave_planes = 1; 1124 1125 return true; 1126 } 1127 1128 static void bw_calcs_data_update_from_pplib(struct dc *dc) 1129 { 1130 struct dm_pp_clock_levels clks = {0}; 1131 1132 /*do system clock*/ 1133 dm_pp_get_clock_levels_by_type( 1134 dc->ctx, 1135 DM_PP_CLOCK_TYPE_ENGINE_CLK, 1136 &clks); 1137 /* convert all the clock fro kHz to fix point mHz */ 1138 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 1139 clks.clocks_in_khz[clks.num_levels-1], 1000); 1140 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 1141 clks.clocks_in_khz[clks.num_levels/8], 1000); 1142 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 1143 clks.clocks_in_khz[clks.num_levels*2/8], 1000); 1144 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 1145 clks.clocks_in_khz[clks.num_levels*3/8], 1000); 1146 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 1147 clks.clocks_in_khz[clks.num_levels*4/8], 1000); 1148 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 1149 clks.clocks_in_khz[clks.num_levels*5/8], 1000); 1150 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1151 clks.clocks_in_khz[clks.num_levels*6/8], 1000); 1152 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1153 clks.clocks_in_khz[0], 1000); 1154 dc->sclk_lvls = clks; 1155 1156 /*do display clock*/ 1157 dm_pp_get_clock_levels_by_type( 1158 dc->ctx, 1159 DM_PP_CLOCK_TYPE_DISPLAY_CLK, 1160 &clks); 1161 dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed( 1162 clks.clocks_in_khz[clks.num_levels-1], 1000); 1163 dc->bw_vbios->mid_voltage_max_dispclk = bw_frc_to_fixed( 1164 clks.clocks_in_khz[clks.num_levels>>1], 1000); 1165 dc->bw_vbios->low_voltage_max_dispclk = bw_frc_to_fixed( 1166 clks.clocks_in_khz[0], 1000); 1167 1168 /*do memory clock*/ 1169 dm_pp_get_clock_levels_by_type( 1170 dc->ctx, 1171 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1172 &clks); 1173 1174 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1175 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000); 1176 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1177 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER, 1178 1000); 1179 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1180 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER, 1181 1000); 1182 } 1183 1184 const struct resource_caps *dce110_resource_cap( 1185 struct hw_asic_id *asic_id) 1186 { 1187 if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev)) 1188 return &stoney_resource_cap; 1189 else 1190 return &carrizo_resource_cap; 1191 } 1192 1193 static bool construct( 1194 uint8_t num_virtual_links, 1195 struct dc *dc, 1196 struct dce110_resource_pool *pool, 1197 struct hw_asic_id asic_id) 1198 { 1199 unsigned int i; 1200 struct dc_context *ctx = dc->ctx; 1201 struct dc_firmware_info info; 1202 struct dc_bios *bp; 1203 struct dm_pp_static_clock_info static_clk_info = {0}; 1204 1205 ctx->dc_bios->regs = &bios_regs; 1206 1207 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); 1208 pool->base.funcs = &dce110_res_pool_funcs; 1209 1210 /************************************************* 1211 * Resource + asic cap harcoding * 1212 *************************************************/ 1213 1214 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1215 pool->base.underlay_pipe_index = pool->base.pipe_count; 1216 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1217 dc->caps.max_downscale_ratio = 150; 1218 dc->caps.i2c_speed_in_khz = 100; 1219 dc->caps.max_cursor_size = 128; 1220 dc->caps.is_apu = true; 1221 1222 /************************************************* 1223 * Create resources * 1224 *************************************************/ 1225 1226 bp = ctx->dc_bios; 1227 1228 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1229 info.external_clock_source_frequency_for_dp != 0) { 1230 pool->base.dp_clock_source = 1231 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1232 1233 pool->base.clock_sources[0] = 1234 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, 1235 &clk_src_regs[0], false); 1236 pool->base.clock_sources[1] = 1237 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, 1238 &clk_src_regs[1], false); 1239 1240 pool->base.clk_src_count = 2; 1241 1242 /* TODO: find out if CZ support 3 PLLs */ 1243 } 1244 1245 if (pool->base.dp_clock_source == NULL) { 1246 dm_error("DC: failed to create dp clock source!\n"); 1247 BREAK_TO_DEBUGGER(); 1248 goto res_create_fail; 1249 } 1250 1251 for (i = 0; i < pool->base.clk_src_count; i++) { 1252 if (pool->base.clock_sources[i] == NULL) { 1253 dm_error("DC: failed to create clock sources!\n"); 1254 BREAK_TO_DEBUGGER(); 1255 goto res_create_fail; 1256 } 1257 } 1258 1259 pool->base.dccg = dce110_dccg_create(ctx, 1260 &disp_clk_regs, 1261 &disp_clk_shift, 1262 &disp_clk_mask); 1263 if (pool->base.dccg == NULL) { 1264 dm_error("DC: failed to create display clock!\n"); 1265 BREAK_TO_DEBUGGER(); 1266 goto res_create_fail; 1267 } 1268 1269 pool->base.dmcu = dce_dmcu_create(ctx, 1270 &dmcu_regs, 1271 &dmcu_shift, 1272 &dmcu_mask); 1273 if (pool->base.dmcu == NULL) { 1274 dm_error("DC: failed to create dmcu!\n"); 1275 BREAK_TO_DEBUGGER(); 1276 goto res_create_fail; 1277 } 1278 1279 pool->base.abm = dce_abm_create(ctx, 1280 &abm_regs, 1281 &abm_shift, 1282 &abm_mask); 1283 if (pool->base.abm == NULL) { 1284 dm_error("DC: failed to create abm!\n"); 1285 BREAK_TO_DEBUGGER(); 1286 goto res_create_fail; 1287 } 1288 1289 /* get static clock information for PPLIB or firmware, save 1290 * max_clock_state 1291 */ 1292 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 1293 pool->base.dccg->max_clks_state = 1294 static_clk_info.max_clocks_state; 1295 1296 { 1297 struct irq_service_init_data init_data; 1298 init_data.ctx = dc->ctx; 1299 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 1300 if (!pool->base.irqs) 1301 goto res_create_fail; 1302 } 1303 1304 for (i = 0; i < pool->base.pipe_count; i++) { 1305 pool->base.timing_generators[i] = dce110_timing_generator_create( 1306 ctx, i, &dce110_tg_offsets[i]); 1307 if (pool->base.timing_generators[i] == NULL) { 1308 BREAK_TO_DEBUGGER(); 1309 dm_error("DC: failed to create tg!\n"); 1310 goto res_create_fail; 1311 } 1312 1313 pool->base.mis[i] = dce110_mem_input_create(ctx, i); 1314 if (pool->base.mis[i] == NULL) { 1315 BREAK_TO_DEBUGGER(); 1316 dm_error( 1317 "DC: failed to create memory input!\n"); 1318 goto res_create_fail; 1319 } 1320 1321 pool->base.ipps[i] = dce110_ipp_create(ctx, i); 1322 if (pool->base.ipps[i] == NULL) { 1323 BREAK_TO_DEBUGGER(); 1324 dm_error( 1325 "DC: failed to create input pixel processor!\n"); 1326 goto res_create_fail; 1327 } 1328 1329 pool->base.transforms[i] = dce110_transform_create(ctx, i); 1330 if (pool->base.transforms[i] == NULL) { 1331 BREAK_TO_DEBUGGER(); 1332 dm_error( 1333 "DC: failed to create transform!\n"); 1334 goto res_create_fail; 1335 } 1336 1337 pool->base.opps[i] = dce110_opp_create(ctx, i); 1338 if (pool->base.opps[i] == NULL) { 1339 BREAK_TO_DEBUGGER(); 1340 dm_error( 1341 "DC: failed to create output pixel processor!\n"); 1342 goto res_create_fail; 1343 } 1344 } 1345 1346 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1347 pool->base.engines[i] = dce110_aux_engine_create(ctx, i); 1348 if (pool->base.engines[i] == NULL) { 1349 BREAK_TO_DEBUGGER(); 1350 dm_error( 1351 "DC:failed to create aux engine!!\n"); 1352 goto res_create_fail; 1353 } 1354 pool->base.hw_i2cs[i] = dce110_i2c_hw_create(ctx, i); 1355 if (pool->base.hw_i2cs[i] == NULL) { 1356 BREAK_TO_DEBUGGER(); 1357 dm_error( 1358 "DC:failed to create i2c engine!!\n"); 1359 goto res_create_fail; 1360 } 1361 pool->base.sw_i2cs[i] = NULL; 1362 } 1363 1364 dc->fbc_compressor = dce110_compressor_create(ctx); 1365 1366 if (!underlay_create(ctx, &pool->base)) 1367 goto res_create_fail; 1368 1369 if (!resource_construct(num_virtual_links, dc, &pool->base, 1370 &res_create_funcs)) 1371 goto res_create_fail; 1372 1373 /* Create hardware sequencer */ 1374 dce110_hw_sequencer_construct(dc); 1375 1376 dc->caps.max_planes = pool->base.pipe_count; 1377 1378 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1379 1380 bw_calcs_data_update_from_pplib(dc); 1381 1382 return true; 1383 1384 res_create_fail: 1385 destruct(pool); 1386 return false; 1387 } 1388 1389 struct resource_pool *dce110_create_resource_pool( 1390 uint8_t num_virtual_links, 1391 struct dc *dc, 1392 struct hw_asic_id asic_id) 1393 { 1394 struct dce110_resource_pool *pool = 1395 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1396 1397 if (!pool) 1398 return NULL; 1399 1400 if (construct(num_virtual_links, dc, pool, asic_id)) 1401 return &pool->base; 1402 1403 BREAK_TO_DEBUGGER(); 1404 return NULL; 1405 } 1406