1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "link_encoder.h" 29 #include "stream_encoder.h" 30 31 #include "resource.h" 32 #include "dce110/dce110_resource.h" 33 34 #include "dce/dce_clk_mgr.h" 35 #include "include/irq_service_interface.h" 36 #include "dce/dce_audio.h" 37 #include "dce110/dce110_timing_generator.h" 38 #include "irq/dce110/irq_service_dce110.h" 39 #include "dce110/dce110_timing_generator_v.h" 40 #include "dce/dce_link_encoder.h" 41 #include "dce/dce_stream_encoder.h" 42 #include "dce/dce_mem_input.h" 43 #include "dce110/dce110_mem_input_v.h" 44 #include "dce/dce_ipp.h" 45 #include "dce/dce_transform.h" 46 #include "dce110/dce110_transform_v.h" 47 #include "dce/dce_opp.h" 48 #include "dce110/dce110_opp_v.h" 49 #include "dce/dce_clock_source.h" 50 #include "dce/dce_hwseq.h" 51 #include "dce110/dce110_hw_sequencer.h" 52 #include "dce/dce_aux.h" 53 #include "dce/dce_abm.h" 54 #include "dce/dce_dmcu.h" 55 #include "dce/dce_i2c.h" 56 57 #define DC_LOGGER \ 58 dc->ctx->logger 59 60 #include "dce110/dce110_compressor.h" 61 62 #include "reg_helper.h" 63 64 #include "dce/dce_11_0_d.h" 65 #include "dce/dce_11_0_sh_mask.h" 66 67 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 68 #include "gmc/gmc_8_2_d.h" 69 #include "gmc/gmc_8_2_sh_mask.h" 70 #endif 71 72 #ifndef mmDP_DPHY_INTERNAL_CTRL 73 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 74 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 75 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 76 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 77 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 78 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 79 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 80 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 81 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 82 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 83 #endif 84 85 #ifndef mmBIOS_SCRATCH_2 86 #define mmBIOS_SCRATCH_2 0x05CB 87 #define mmBIOS_SCRATCH_3 0x05CC 88 #define mmBIOS_SCRATCH_6 0x05CF 89 #endif 90 91 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 92 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 93 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 94 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 95 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 96 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 97 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 98 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 99 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 100 #endif 101 102 #ifndef mmDP_DPHY_FAST_TRAINING 103 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 104 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 105 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 106 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 107 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 108 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 109 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 110 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 111 #endif 112 113 #ifndef DPHY_RX_FAST_TRAINING_CAPABLE 114 #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1 115 #endif 116 117 static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = { 118 { 119 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 120 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 121 }, 122 { 123 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 124 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 125 }, 126 { 127 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 128 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 129 }, 130 { 131 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 132 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 133 }, 134 { 135 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 136 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 137 }, 138 { 139 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 140 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 141 } 142 }; 143 144 /* set register offset */ 145 #define SR(reg_name)\ 146 .reg_name = mm ## reg_name 147 148 /* set register offset with instance */ 149 #define SRI(reg_name, block, id)\ 150 .reg_name = mm ## block ## id ## _ ## reg_name 151 152 static const struct clk_mgr_registers disp_clk_regs = { 153 CLK_COMMON_REG_LIST_DCE_BASE() 154 }; 155 156 static const struct clk_mgr_shift disp_clk_shift = { 157 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 158 }; 159 160 static const struct clk_mgr_mask disp_clk_mask = { 161 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 162 }; 163 164 static const struct dce_dmcu_registers dmcu_regs = { 165 DMCU_DCE110_COMMON_REG_LIST() 166 }; 167 168 static const struct dce_dmcu_shift dmcu_shift = { 169 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 170 }; 171 172 static const struct dce_dmcu_mask dmcu_mask = { 173 DMCU_MASK_SH_LIST_DCE110(_MASK) 174 }; 175 176 static const struct dce_abm_registers abm_regs = { 177 ABM_DCE110_COMMON_REG_LIST() 178 }; 179 180 static const struct dce_abm_shift abm_shift = { 181 ABM_MASK_SH_LIST_DCE110(__SHIFT) 182 }; 183 184 static const struct dce_abm_mask abm_mask = { 185 ABM_MASK_SH_LIST_DCE110(_MASK) 186 }; 187 188 #define ipp_regs(id)\ 189 [id] = {\ 190 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 191 } 192 193 static const struct dce_ipp_registers ipp_regs[] = { 194 ipp_regs(0), 195 ipp_regs(1), 196 ipp_regs(2) 197 }; 198 199 static const struct dce_ipp_shift ipp_shift = { 200 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 201 }; 202 203 static const struct dce_ipp_mask ipp_mask = { 204 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 205 }; 206 207 #define transform_regs(id)\ 208 [id] = {\ 209 XFM_COMMON_REG_LIST_DCE110(id)\ 210 } 211 212 static const struct dce_transform_registers xfm_regs[] = { 213 transform_regs(0), 214 transform_regs(1), 215 transform_regs(2) 216 }; 217 218 static const struct dce_transform_shift xfm_shift = { 219 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 220 }; 221 222 static const struct dce_transform_mask xfm_mask = { 223 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 224 }; 225 226 #define aux_regs(id)\ 227 [id] = {\ 228 AUX_REG_LIST(id)\ 229 } 230 231 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 232 aux_regs(0), 233 aux_regs(1), 234 aux_regs(2), 235 aux_regs(3), 236 aux_regs(4), 237 aux_regs(5) 238 }; 239 240 #define hpd_regs(id)\ 241 [id] = {\ 242 HPD_REG_LIST(id)\ 243 } 244 245 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 246 hpd_regs(0), 247 hpd_regs(1), 248 hpd_regs(2), 249 hpd_regs(3), 250 hpd_regs(4), 251 hpd_regs(5) 252 }; 253 254 255 #define link_regs(id)\ 256 [id] = {\ 257 LE_DCE110_REG_LIST(id)\ 258 } 259 260 static const struct dce110_link_enc_registers link_enc_regs[] = { 261 link_regs(0), 262 link_regs(1), 263 link_regs(2), 264 link_regs(3), 265 link_regs(4), 266 link_regs(5), 267 link_regs(6), 268 }; 269 270 #define stream_enc_regs(id)\ 271 [id] = {\ 272 SE_COMMON_REG_LIST(id),\ 273 .TMDS_CNTL = 0,\ 274 } 275 276 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 277 stream_enc_regs(0), 278 stream_enc_regs(1), 279 stream_enc_regs(2) 280 }; 281 282 static const struct dce_stream_encoder_shift se_shift = { 283 SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 284 }; 285 286 static const struct dce_stream_encoder_mask se_mask = { 287 SE_COMMON_MASK_SH_LIST_DCE110(_MASK) 288 }; 289 290 #define opp_regs(id)\ 291 [id] = {\ 292 OPP_DCE_110_REG_LIST(id),\ 293 } 294 295 static const struct dce_opp_registers opp_regs[] = { 296 opp_regs(0), 297 opp_regs(1), 298 opp_regs(2), 299 opp_regs(3), 300 opp_regs(4), 301 opp_regs(5) 302 }; 303 304 static const struct dce_opp_shift opp_shift = { 305 OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT) 306 }; 307 308 static const struct dce_opp_mask opp_mask = { 309 OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK) 310 }; 311 312 #define aux_engine_regs(id)\ 313 [id] = {\ 314 AUX_COMMON_REG_LIST(id), \ 315 .AUX_RESET_MASK = 0 \ 316 } 317 318 static const struct dce110_aux_registers aux_engine_regs[] = { 319 aux_engine_regs(0), 320 aux_engine_regs(1), 321 aux_engine_regs(2), 322 aux_engine_regs(3), 323 aux_engine_regs(4), 324 aux_engine_regs(5) 325 }; 326 327 #define audio_regs(id)\ 328 [id] = {\ 329 AUD_COMMON_REG_LIST(id)\ 330 } 331 332 static const struct dce_audio_registers audio_regs[] = { 333 audio_regs(0), 334 audio_regs(1), 335 audio_regs(2), 336 audio_regs(3), 337 audio_regs(4), 338 audio_regs(5), 339 audio_regs(6), 340 }; 341 342 static const struct dce_audio_shift audio_shift = { 343 AUD_COMMON_MASK_SH_LIST(__SHIFT) 344 }; 345 346 static const struct dce_aduio_mask audio_mask = { 347 AUD_COMMON_MASK_SH_LIST(_MASK) 348 }; 349 350 /* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */ 351 352 353 #define clk_src_regs(id)\ 354 [id] = {\ 355 CS_COMMON_REG_LIST_DCE_100_110(id),\ 356 } 357 358 static const struct dce110_clk_src_regs clk_src_regs[] = { 359 clk_src_regs(0), 360 clk_src_regs(1), 361 clk_src_regs(2) 362 }; 363 364 static const struct dce110_clk_src_shift cs_shift = { 365 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 366 }; 367 368 static const struct dce110_clk_src_mask cs_mask = { 369 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 370 }; 371 372 static const struct bios_registers bios_regs = { 373 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 374 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 375 }; 376 377 static const struct resource_caps carrizo_resource_cap = { 378 .num_timing_generator = 3, 379 .num_video_plane = 1, 380 .num_audio = 3, 381 .num_stream_encoder = 3, 382 .num_pll = 2, 383 .num_ddc = 3, 384 }; 385 386 static const struct resource_caps stoney_resource_cap = { 387 .num_timing_generator = 2, 388 .num_video_plane = 1, 389 .num_audio = 3, 390 .num_stream_encoder = 3, 391 .num_pll = 2, 392 .num_ddc = 3, 393 }; 394 395 static const struct dc_plane_cap plane_cap = { 396 .type = DC_PLANE_TYPE_DCE_RGB, 397 .blends_with_below = true, 398 .blends_with_above = true, 399 .per_pixel_alpha = 1, 400 .supports_argb8888 = true, 401 }; 402 403 static const struct dc_plane_cap underlay_plane_cap = { 404 .type = DC_PLANE_TYPE_DCE_UNDERLAY, 405 .blends_with_above = true, 406 .per_pixel_alpha = 1, 407 .supports_nv12 = true 408 }; 409 410 #define CTX ctx 411 #define REG(reg) mm ## reg 412 413 #ifndef mmCC_DC_HDMI_STRAPS 414 #define mmCC_DC_HDMI_STRAPS 0x4819 415 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 416 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 417 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 418 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 419 #endif 420 421 static void read_dce_straps( 422 struct dc_context *ctx, 423 struct resource_straps *straps) 424 { 425 REG_GET_2(CC_DC_HDMI_STRAPS, 426 HDMI_DISABLE, &straps->hdmi_disable, 427 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 428 429 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 430 } 431 432 static struct audio *create_audio( 433 struct dc_context *ctx, unsigned int inst) 434 { 435 return dce_audio_create(ctx, inst, 436 &audio_regs[inst], &audio_shift, &audio_mask); 437 } 438 439 static struct timing_generator *dce110_timing_generator_create( 440 struct dc_context *ctx, 441 uint32_t instance, 442 const struct dce110_timing_generator_offsets *offsets) 443 { 444 struct dce110_timing_generator *tg110 = 445 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 446 447 if (!tg110) 448 return NULL; 449 450 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 451 return &tg110->base; 452 } 453 454 static struct stream_encoder *dce110_stream_encoder_create( 455 enum engine_id eng_id, 456 struct dc_context *ctx) 457 { 458 struct dce110_stream_encoder *enc110 = 459 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 460 461 if (!enc110) 462 return NULL; 463 464 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 465 &stream_enc_regs[eng_id], 466 &se_shift, &se_mask); 467 return &enc110->base; 468 } 469 470 #define SRII(reg_name, block, id)\ 471 .reg_name[id] = mm ## block ## id ## _ ## reg_name 472 473 static const struct dce_hwseq_registers hwseq_stoney_reg = { 474 HWSEQ_ST_REG_LIST() 475 }; 476 477 static const struct dce_hwseq_registers hwseq_cz_reg = { 478 HWSEQ_CZ_REG_LIST() 479 }; 480 481 static const struct dce_hwseq_shift hwseq_shift = { 482 HWSEQ_DCE11_MASK_SH_LIST(__SHIFT), 483 }; 484 485 static const struct dce_hwseq_mask hwseq_mask = { 486 HWSEQ_DCE11_MASK_SH_LIST(_MASK), 487 }; 488 489 static struct dce_hwseq *dce110_hwseq_create( 490 struct dc_context *ctx) 491 { 492 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 493 494 if (hws) { 495 hws->ctx = ctx; 496 hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ? 497 &hwseq_stoney_reg : &hwseq_cz_reg; 498 hws->shifts = &hwseq_shift; 499 hws->masks = &hwseq_mask; 500 hws->wa.blnd_crtc_trigger = true; 501 } 502 return hws; 503 } 504 505 static const struct resource_create_funcs res_create_funcs = { 506 .read_dce_straps = read_dce_straps, 507 .create_audio = create_audio, 508 .create_stream_encoder = dce110_stream_encoder_create, 509 .create_hwseq = dce110_hwseq_create, 510 }; 511 512 #define mi_inst_regs(id) { \ 513 MI_DCE11_REG_LIST(id), \ 514 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 515 } 516 static const struct dce_mem_input_registers mi_regs[] = { 517 mi_inst_regs(0), 518 mi_inst_regs(1), 519 mi_inst_regs(2), 520 }; 521 522 static const struct dce_mem_input_shift mi_shifts = { 523 MI_DCE11_MASK_SH_LIST(__SHIFT), 524 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 525 }; 526 527 static const struct dce_mem_input_mask mi_masks = { 528 MI_DCE11_MASK_SH_LIST(_MASK), 529 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 530 }; 531 532 533 static struct mem_input *dce110_mem_input_create( 534 struct dc_context *ctx, 535 uint32_t inst) 536 { 537 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 538 GFP_KERNEL); 539 540 if (!dce_mi) { 541 BREAK_TO_DEBUGGER(); 542 return NULL; 543 } 544 545 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 546 dce_mi->wa.single_head_rdreq_dmif_limit = 3; 547 return &dce_mi->base; 548 } 549 550 static void dce110_transform_destroy(struct transform **xfm) 551 { 552 kfree(TO_DCE_TRANSFORM(*xfm)); 553 *xfm = NULL; 554 } 555 556 static struct transform *dce110_transform_create( 557 struct dc_context *ctx, 558 uint32_t inst) 559 { 560 struct dce_transform *transform = 561 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 562 563 if (!transform) 564 return NULL; 565 566 dce_transform_construct(transform, ctx, inst, 567 &xfm_regs[inst], &xfm_shift, &xfm_mask); 568 return &transform->base; 569 } 570 571 static struct input_pixel_processor *dce110_ipp_create( 572 struct dc_context *ctx, uint32_t inst) 573 { 574 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 575 576 if (!ipp) { 577 BREAK_TO_DEBUGGER(); 578 return NULL; 579 } 580 581 dce_ipp_construct(ipp, ctx, inst, 582 &ipp_regs[inst], &ipp_shift, &ipp_mask); 583 return &ipp->base; 584 } 585 586 static const struct encoder_feature_support link_enc_feature = { 587 .max_hdmi_deep_color = COLOR_DEPTH_121212, 588 .max_hdmi_pixel_clock = 300000, 589 .flags.bits.IS_HBR2_CAPABLE = true, 590 .flags.bits.IS_TPS3_CAPABLE = true 591 }; 592 593 static struct link_encoder *dce110_link_encoder_create( 594 const struct encoder_init_data *enc_init_data) 595 { 596 struct dce110_link_encoder *enc110 = 597 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 598 599 if (!enc110) 600 return NULL; 601 602 dce110_link_encoder_construct(enc110, 603 enc_init_data, 604 &link_enc_feature, 605 &link_enc_regs[enc_init_data->transmitter], 606 &link_enc_aux_regs[enc_init_data->channel - 1], 607 &link_enc_hpd_regs[enc_init_data->hpd_source]); 608 return &enc110->base; 609 } 610 611 static struct output_pixel_processor *dce110_opp_create( 612 struct dc_context *ctx, 613 uint32_t inst) 614 { 615 struct dce110_opp *opp = 616 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 617 618 if (!opp) 619 return NULL; 620 621 dce110_opp_construct(opp, 622 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 623 return &opp->base; 624 } 625 626 struct dce_aux *dce110_aux_engine_create( 627 struct dc_context *ctx, 628 uint32_t inst) 629 { 630 struct aux_engine_dce110 *aux_engine = 631 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 632 633 if (!aux_engine) 634 return NULL; 635 636 dce110_aux_engine_construct(aux_engine, ctx, inst, 637 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 638 &aux_engine_regs[inst]); 639 640 return &aux_engine->base; 641 } 642 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 643 644 static const struct dce_i2c_registers i2c_hw_regs[] = { 645 i2c_inst_regs(1), 646 i2c_inst_regs(2), 647 i2c_inst_regs(3), 648 i2c_inst_regs(4), 649 i2c_inst_regs(5), 650 i2c_inst_regs(6), 651 }; 652 653 static const struct dce_i2c_shift i2c_shifts = { 654 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 655 }; 656 657 static const struct dce_i2c_mask i2c_masks = { 658 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 659 }; 660 661 struct dce_i2c_hw *dce110_i2c_hw_create( 662 struct dc_context *ctx, 663 uint32_t inst) 664 { 665 struct dce_i2c_hw *dce_i2c_hw = 666 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 667 668 if (!dce_i2c_hw) 669 return NULL; 670 671 dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst, 672 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 673 674 return dce_i2c_hw; 675 } 676 struct clock_source *dce110_clock_source_create( 677 struct dc_context *ctx, 678 struct dc_bios *bios, 679 enum clock_source_id id, 680 const struct dce110_clk_src_regs *regs, 681 bool dp_clk_src) 682 { 683 struct dce110_clk_src *clk_src = 684 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 685 686 if (!clk_src) 687 return NULL; 688 689 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 690 regs, &cs_shift, &cs_mask)) { 691 clk_src->base.dp_clk_src = dp_clk_src; 692 return &clk_src->base; 693 } 694 695 BREAK_TO_DEBUGGER(); 696 return NULL; 697 } 698 699 void dce110_clock_source_destroy(struct clock_source **clk_src) 700 { 701 struct dce110_clk_src *dce110_clk_src; 702 703 if (!clk_src) 704 return; 705 706 dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src); 707 708 kfree(dce110_clk_src->dp_ss_params); 709 kfree(dce110_clk_src->hdmi_ss_params); 710 kfree(dce110_clk_src->dvi_ss_params); 711 712 kfree(dce110_clk_src); 713 *clk_src = NULL; 714 } 715 716 static void destruct(struct dce110_resource_pool *pool) 717 { 718 unsigned int i; 719 720 for (i = 0; i < pool->base.pipe_count; i++) { 721 if (pool->base.opps[i] != NULL) 722 dce110_opp_destroy(&pool->base.opps[i]); 723 724 if (pool->base.transforms[i] != NULL) 725 dce110_transform_destroy(&pool->base.transforms[i]); 726 727 if (pool->base.ipps[i] != NULL) 728 dce_ipp_destroy(&pool->base.ipps[i]); 729 730 if (pool->base.mis[i] != NULL) { 731 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 732 pool->base.mis[i] = NULL; 733 } 734 735 if (pool->base.timing_generators[i] != NULL) { 736 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 737 pool->base.timing_generators[i] = NULL; 738 } 739 } 740 741 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 742 if (pool->base.engines[i] != NULL) 743 dce110_engine_destroy(&pool->base.engines[i]); 744 if (pool->base.hw_i2cs[i] != NULL) { 745 kfree(pool->base.hw_i2cs[i]); 746 pool->base.hw_i2cs[i] = NULL; 747 } 748 if (pool->base.sw_i2cs[i] != NULL) { 749 kfree(pool->base.sw_i2cs[i]); 750 pool->base.sw_i2cs[i] = NULL; 751 } 752 } 753 754 for (i = 0; i < pool->base.stream_enc_count; i++) { 755 if (pool->base.stream_enc[i] != NULL) 756 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 757 } 758 759 for (i = 0; i < pool->base.clk_src_count; i++) { 760 if (pool->base.clock_sources[i] != NULL) { 761 dce110_clock_source_destroy(&pool->base.clock_sources[i]); 762 } 763 } 764 765 if (pool->base.dp_clock_source != NULL) 766 dce110_clock_source_destroy(&pool->base.dp_clock_source); 767 768 for (i = 0; i < pool->base.audio_count; i++) { 769 if (pool->base.audios[i] != NULL) { 770 dce_aud_destroy(&pool->base.audios[i]); 771 } 772 } 773 774 if (pool->base.abm != NULL) 775 dce_abm_destroy(&pool->base.abm); 776 777 if (pool->base.dmcu != NULL) 778 dce_dmcu_destroy(&pool->base.dmcu); 779 780 if (pool->base.clk_mgr != NULL) 781 dce_clk_mgr_destroy(&pool->base.clk_mgr); 782 783 if (pool->base.irqs != NULL) { 784 dal_irq_service_destroy(&pool->base.irqs); 785 } 786 } 787 788 789 static void get_pixel_clock_parameters( 790 const struct pipe_ctx *pipe_ctx, 791 struct pixel_clk_params *pixel_clk_params) 792 { 793 const struct dc_stream_state *stream = pipe_ctx->stream; 794 795 /*TODO: is this halved for YCbCr 420? in that case we might want to move 796 * the pixel clock normalization for hdmi up to here instead of doing it 797 * in pll_adjust_pix_clk 798 */ 799 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 800 pixel_clk_params->encoder_object_id = stream->link->link_enc->id; 801 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 802 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 803 /* TODO: un-hardcode*/ 804 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 805 LINK_RATE_REF_FREQ_IN_KHZ; 806 pixel_clk_params->flags.ENABLE_SS = 0; 807 pixel_clk_params->color_depth = 808 stream->timing.display_color_depth; 809 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 810 pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding == 811 PIXEL_ENCODING_YCBCR420); 812 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 813 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) { 814 pixel_clk_params->color_depth = COLOR_DEPTH_888; 815 } 816 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 817 pixel_clk_params->requested_pix_clk_100hz = pixel_clk_params->requested_pix_clk_100hz / 2; 818 } 819 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 820 pixel_clk_params->requested_pix_clk_100hz *= 2; 821 822 } 823 824 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 825 { 826 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 827 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 828 pipe_ctx->clock_source, 829 &pipe_ctx->stream_res.pix_clk_params, 830 &pipe_ctx->pll_settings); 831 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 832 &pipe_ctx->stream->bit_depth_params); 833 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 834 } 835 836 static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx) 837 { 838 if (pipe_ctx->pipe_idx != underlay_idx) 839 return true; 840 if (!pipe_ctx->plane_state) 841 return false; 842 if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 843 return false; 844 return true; 845 } 846 847 static enum dc_status build_mapped_resource( 848 const struct dc *dc, 849 struct dc_state *context, 850 struct dc_stream_state *stream) 851 { 852 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 853 854 if (!pipe_ctx) 855 return DC_ERROR_UNEXPECTED; 856 857 if (!is_surface_pixel_format_supported(pipe_ctx, 858 dc->res_pool->underlay_pipe_index)) 859 return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; 860 861 dce110_resource_build_pipe_hw_param(pipe_ctx); 862 863 /* TODO: validate audio ASIC caps, encoder */ 864 865 resource_build_info_frame(pipe_ctx); 866 867 return DC_OK; 868 } 869 870 static bool dce110_validate_bandwidth( 871 struct dc *dc, 872 struct dc_state *context) 873 { 874 bool result = false; 875 876 DC_LOG_BANDWIDTH_CALCS( 877 "%s: start", 878 __func__); 879 880 if (bw_calcs( 881 dc->ctx, 882 dc->bw_dceip, 883 dc->bw_vbios, 884 context->res_ctx.pipe_ctx, 885 dc->res_pool->pipe_count, 886 &context->bw.dce)) 887 result = true; 888 889 if (!result) 890 DC_LOG_BANDWIDTH_VALIDATION("%s: %dx%d@%d Bandwidth validation failed!\n", 891 __func__, 892 context->streams[0]->timing.h_addressable, 893 context->streams[0]->timing.v_addressable, 894 context->streams[0]->timing.pix_clk_100hz / 10); 895 896 if (memcmp(&dc->current_state->bw.dce, 897 &context->bw.dce, sizeof(context->bw.dce))) { 898 899 DC_LOG_BANDWIDTH_CALCS( 900 "%s: finish,\n" 901 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 902 "stutMark_b: %d stutMark_a: %d\n" 903 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 904 "stutMark_b: %d stutMark_a: %d\n" 905 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 906 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n" 907 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" 908 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n" 909 , 910 __func__, 911 context->bw.dce.nbp_state_change_wm_ns[0].b_mark, 912 context->bw.dce.nbp_state_change_wm_ns[0].a_mark, 913 context->bw.dce.urgent_wm_ns[0].b_mark, 914 context->bw.dce.urgent_wm_ns[0].a_mark, 915 context->bw.dce.stutter_exit_wm_ns[0].b_mark, 916 context->bw.dce.stutter_exit_wm_ns[0].a_mark, 917 context->bw.dce.nbp_state_change_wm_ns[1].b_mark, 918 context->bw.dce.nbp_state_change_wm_ns[1].a_mark, 919 context->bw.dce.urgent_wm_ns[1].b_mark, 920 context->bw.dce.urgent_wm_ns[1].a_mark, 921 context->bw.dce.stutter_exit_wm_ns[1].b_mark, 922 context->bw.dce.stutter_exit_wm_ns[1].a_mark, 923 context->bw.dce.nbp_state_change_wm_ns[2].b_mark, 924 context->bw.dce.nbp_state_change_wm_ns[2].a_mark, 925 context->bw.dce.urgent_wm_ns[2].b_mark, 926 context->bw.dce.urgent_wm_ns[2].a_mark, 927 context->bw.dce.stutter_exit_wm_ns[2].b_mark, 928 context->bw.dce.stutter_exit_wm_ns[2].a_mark, 929 context->bw.dce.stutter_mode_enable, 930 context->bw.dce.cpuc_state_change_enable, 931 context->bw.dce.cpup_state_change_enable, 932 context->bw.dce.nbp_state_change_enable, 933 context->bw.dce.all_displays_in_sync, 934 context->bw.dce.dispclk_khz, 935 context->bw.dce.sclk_khz, 936 context->bw.dce.sclk_deep_sleep_khz, 937 context->bw.dce.yclk_khz, 938 context->bw.dce.blackout_recovery_time_us); 939 } 940 return result; 941 } 942 943 enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state, 944 struct dc_caps *caps) 945 { 946 if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) || 947 ((plane_state->dst_rect.height * 2) < plane_state->src_rect.height)) 948 return DC_FAIL_SURFACE_VALIDATE; 949 950 return DC_OK; 951 } 952 953 static bool dce110_validate_surface_sets( 954 struct dc_state *context) 955 { 956 int i, j; 957 958 for (i = 0; i < context->stream_count; i++) { 959 if (context->stream_status[i].plane_count == 0) 960 continue; 961 962 if (context->stream_status[i].plane_count > 2) 963 return false; 964 965 for (j = 0; j < context->stream_status[i].plane_count; j++) { 966 struct dc_plane_state *plane = 967 context->stream_status[i].plane_states[j]; 968 969 /* underlay validation */ 970 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 971 972 if ((plane->src_rect.width > 1920 || 973 plane->src_rect.height > 1080)) 974 return false; 975 976 /* we don't have the logic to support underlay 977 * only yet so block the use case where we get 978 * NV12 plane as top layer 979 */ 980 if (j == 0) 981 return false; 982 983 /* irrespective of plane format, 984 * stream should be RGB encoded 985 */ 986 if (context->streams[i]->timing.pixel_encoding 987 != PIXEL_ENCODING_RGB) 988 return false; 989 990 } 991 992 } 993 } 994 995 return true; 996 } 997 998 enum dc_status dce110_validate_global( 999 struct dc *dc, 1000 struct dc_state *context) 1001 { 1002 if (!dce110_validate_surface_sets(context)) 1003 return DC_FAIL_SURFACE_VALIDATE; 1004 1005 return DC_OK; 1006 } 1007 1008 static enum dc_status dce110_add_stream_to_ctx( 1009 struct dc *dc, 1010 struct dc_state *new_ctx, 1011 struct dc_stream_state *dc_stream) 1012 { 1013 enum dc_status result = DC_ERROR_UNEXPECTED; 1014 1015 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1016 1017 if (result == DC_OK) 1018 result = resource_map_clock_resources(dc, new_ctx, dc_stream); 1019 1020 1021 if (result == DC_OK) 1022 result = build_mapped_resource(dc, new_ctx, dc_stream); 1023 1024 return result; 1025 } 1026 1027 static struct pipe_ctx *dce110_acquire_underlay( 1028 struct dc_state *context, 1029 const struct resource_pool *pool, 1030 struct dc_stream_state *stream) 1031 { 1032 struct dc *dc = stream->ctx->dc; 1033 struct resource_context *res_ctx = &context->res_ctx; 1034 unsigned int underlay_idx = pool->underlay_pipe_index; 1035 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; 1036 1037 if (res_ctx->pipe_ctx[underlay_idx].stream) 1038 return NULL; 1039 1040 pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx]; 1041 pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; 1042 /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/ 1043 pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; 1044 pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; 1045 pipe_ctx->pipe_idx = underlay_idx; 1046 1047 pipe_ctx->stream = stream; 1048 1049 if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) { 1050 struct tg_color black_color = {0}; 1051 struct dc_bios *dcb = dc->ctx->dc_bios; 1052 1053 dc->hwss.enable_display_power_gating( 1054 dc, 1055 pipe_ctx->stream_res.tg->inst, 1056 dcb, PIPE_GATING_CONTROL_DISABLE); 1057 1058 /* 1059 * This is for powering on underlay, so crtc does not 1060 * need to be enabled 1061 */ 1062 1063 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg, 1064 &stream->timing, 1065 false); 1066 1067 pipe_ctx->stream_res.tg->funcs->enable_advanced_request( 1068 pipe_ctx->stream_res.tg, 1069 true, 1070 &stream->timing); 1071 1072 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi, 1073 stream->timing.h_total, 1074 stream->timing.v_total, 1075 stream->timing.pix_clk_100hz / 10, 1076 context->stream_count); 1077 1078 color_space_to_black_color(dc, 1079 COLOR_SPACE_YCBCR601, &black_color); 1080 pipe_ctx->stream_res.tg->funcs->set_blank_color( 1081 pipe_ctx->stream_res.tg, 1082 &black_color); 1083 } 1084 1085 return pipe_ctx; 1086 } 1087 1088 static void dce110_destroy_resource_pool(struct resource_pool **pool) 1089 { 1090 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 1091 1092 destruct(dce110_pool); 1093 kfree(dce110_pool); 1094 *pool = NULL; 1095 } 1096 1097 1098 static const struct resource_funcs dce110_res_pool_funcs = { 1099 .destroy = dce110_destroy_resource_pool, 1100 .link_enc_create = dce110_link_encoder_create, 1101 .validate_bandwidth = dce110_validate_bandwidth, 1102 .validate_plane = dce110_validate_plane, 1103 .acquire_idle_pipe_for_layer = dce110_acquire_underlay, 1104 .add_stream_to_ctx = dce110_add_stream_to_ctx, 1105 .validate_global = dce110_validate_global 1106 }; 1107 1108 static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) 1109 { 1110 struct dce110_timing_generator *dce110_tgv = kzalloc(sizeof(*dce110_tgv), 1111 GFP_KERNEL); 1112 struct dce_transform *dce110_xfmv = kzalloc(sizeof(*dce110_xfmv), 1113 GFP_KERNEL); 1114 struct dce_mem_input *dce110_miv = kzalloc(sizeof(*dce110_miv), 1115 GFP_KERNEL); 1116 struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv), 1117 GFP_KERNEL); 1118 1119 if (!dce110_tgv || !dce110_xfmv || !dce110_miv || !dce110_oppv) { 1120 kfree(dce110_tgv); 1121 kfree(dce110_xfmv); 1122 kfree(dce110_miv); 1123 kfree(dce110_oppv); 1124 return false; 1125 } 1126 1127 dce110_opp_v_construct(dce110_oppv, ctx); 1128 1129 dce110_timing_generator_v_construct(dce110_tgv, ctx); 1130 dce110_mem_input_v_construct(dce110_miv, ctx); 1131 dce110_transform_v_construct(dce110_xfmv, ctx); 1132 1133 pool->opps[pool->pipe_count] = &dce110_oppv->base; 1134 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; 1135 pool->mis[pool->pipe_count] = &dce110_miv->base; 1136 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; 1137 pool->pipe_count++; 1138 1139 /* update the public caps to indicate an underlay is available */ 1140 ctx->dc->caps.max_slave_planes = 1; 1141 ctx->dc->caps.max_slave_planes = 1; 1142 1143 return true; 1144 } 1145 1146 static void bw_calcs_data_update_from_pplib(struct dc *dc) 1147 { 1148 struct dm_pp_clock_levels clks = {0}; 1149 1150 /*do system clock*/ 1151 dm_pp_get_clock_levels_by_type( 1152 dc->ctx, 1153 DM_PP_CLOCK_TYPE_ENGINE_CLK, 1154 &clks); 1155 /* convert all the clock fro kHz to fix point mHz */ 1156 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 1157 clks.clocks_in_khz[clks.num_levels-1], 1000); 1158 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 1159 clks.clocks_in_khz[clks.num_levels/8], 1000); 1160 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 1161 clks.clocks_in_khz[clks.num_levels*2/8], 1000); 1162 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 1163 clks.clocks_in_khz[clks.num_levels*3/8], 1000); 1164 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 1165 clks.clocks_in_khz[clks.num_levels*4/8], 1000); 1166 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 1167 clks.clocks_in_khz[clks.num_levels*5/8], 1000); 1168 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1169 clks.clocks_in_khz[clks.num_levels*6/8], 1000); 1170 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1171 clks.clocks_in_khz[0], 1000); 1172 dc->sclk_lvls = clks; 1173 1174 /*do display clock*/ 1175 dm_pp_get_clock_levels_by_type( 1176 dc->ctx, 1177 DM_PP_CLOCK_TYPE_DISPLAY_CLK, 1178 &clks); 1179 dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed( 1180 clks.clocks_in_khz[clks.num_levels-1], 1000); 1181 dc->bw_vbios->mid_voltage_max_dispclk = bw_frc_to_fixed( 1182 clks.clocks_in_khz[clks.num_levels>>1], 1000); 1183 dc->bw_vbios->low_voltage_max_dispclk = bw_frc_to_fixed( 1184 clks.clocks_in_khz[0], 1000); 1185 1186 /*do memory clock*/ 1187 dm_pp_get_clock_levels_by_type( 1188 dc->ctx, 1189 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1190 &clks); 1191 1192 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1193 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER_CZ, 1000); 1194 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1195 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ, 1196 1000); 1197 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1198 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER_CZ, 1199 1000); 1200 } 1201 1202 const struct resource_caps *dce110_resource_cap( 1203 struct hw_asic_id *asic_id) 1204 { 1205 if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev)) 1206 return &stoney_resource_cap; 1207 else 1208 return &carrizo_resource_cap; 1209 } 1210 1211 static bool construct( 1212 uint8_t num_virtual_links, 1213 struct dc *dc, 1214 struct dce110_resource_pool *pool, 1215 struct hw_asic_id asic_id) 1216 { 1217 unsigned int i; 1218 struct dc_context *ctx = dc->ctx; 1219 struct dc_firmware_info info; 1220 struct dc_bios *bp; 1221 1222 ctx->dc_bios->regs = &bios_regs; 1223 1224 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); 1225 pool->base.funcs = &dce110_res_pool_funcs; 1226 1227 /************************************************* 1228 * Resource + asic cap harcoding * 1229 *************************************************/ 1230 1231 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1232 pool->base.underlay_pipe_index = pool->base.pipe_count; 1233 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1234 dc->caps.max_downscale_ratio = 150; 1235 dc->caps.i2c_speed_in_khz = 100; 1236 dc->caps.max_cursor_size = 128; 1237 dc->caps.is_apu = true; 1238 1239 /************************************************* 1240 * Create resources * 1241 *************************************************/ 1242 1243 bp = ctx->dc_bios; 1244 1245 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1246 info.external_clock_source_frequency_for_dp != 0) { 1247 pool->base.dp_clock_source = 1248 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1249 1250 pool->base.clock_sources[0] = 1251 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, 1252 &clk_src_regs[0], false); 1253 pool->base.clock_sources[1] = 1254 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, 1255 &clk_src_regs[1], false); 1256 1257 pool->base.clk_src_count = 2; 1258 1259 /* TODO: find out if CZ support 3 PLLs */ 1260 } 1261 1262 if (pool->base.dp_clock_source == NULL) { 1263 dm_error("DC: failed to create dp clock source!\n"); 1264 BREAK_TO_DEBUGGER(); 1265 goto res_create_fail; 1266 } 1267 1268 for (i = 0; i < pool->base.clk_src_count; i++) { 1269 if (pool->base.clock_sources[i] == NULL) { 1270 dm_error("DC: failed to create clock sources!\n"); 1271 BREAK_TO_DEBUGGER(); 1272 goto res_create_fail; 1273 } 1274 } 1275 1276 pool->base.clk_mgr = dce110_clk_mgr_create(ctx, 1277 &disp_clk_regs, 1278 &disp_clk_shift, 1279 &disp_clk_mask); 1280 if (pool->base.clk_mgr == NULL) { 1281 dm_error("DC: failed to create display clock!\n"); 1282 BREAK_TO_DEBUGGER(); 1283 goto res_create_fail; 1284 } 1285 1286 pool->base.dmcu = dce_dmcu_create(ctx, 1287 &dmcu_regs, 1288 &dmcu_shift, 1289 &dmcu_mask); 1290 if (pool->base.dmcu == NULL) { 1291 dm_error("DC: failed to create dmcu!\n"); 1292 BREAK_TO_DEBUGGER(); 1293 goto res_create_fail; 1294 } 1295 1296 pool->base.abm = dce_abm_create(ctx, 1297 &abm_regs, 1298 &abm_shift, 1299 &abm_mask); 1300 if (pool->base.abm == NULL) { 1301 dm_error("DC: failed to create abm!\n"); 1302 BREAK_TO_DEBUGGER(); 1303 goto res_create_fail; 1304 } 1305 1306 { 1307 struct irq_service_init_data init_data; 1308 init_data.ctx = dc->ctx; 1309 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 1310 if (!pool->base.irqs) 1311 goto res_create_fail; 1312 } 1313 1314 for (i = 0; i < pool->base.pipe_count; i++) { 1315 pool->base.timing_generators[i] = dce110_timing_generator_create( 1316 ctx, i, &dce110_tg_offsets[i]); 1317 if (pool->base.timing_generators[i] == NULL) { 1318 BREAK_TO_DEBUGGER(); 1319 dm_error("DC: failed to create tg!\n"); 1320 goto res_create_fail; 1321 } 1322 1323 pool->base.mis[i] = dce110_mem_input_create(ctx, i); 1324 if (pool->base.mis[i] == NULL) { 1325 BREAK_TO_DEBUGGER(); 1326 dm_error( 1327 "DC: failed to create memory input!\n"); 1328 goto res_create_fail; 1329 } 1330 1331 pool->base.ipps[i] = dce110_ipp_create(ctx, i); 1332 if (pool->base.ipps[i] == NULL) { 1333 BREAK_TO_DEBUGGER(); 1334 dm_error( 1335 "DC: failed to create input pixel processor!\n"); 1336 goto res_create_fail; 1337 } 1338 1339 pool->base.transforms[i] = dce110_transform_create(ctx, i); 1340 if (pool->base.transforms[i] == NULL) { 1341 BREAK_TO_DEBUGGER(); 1342 dm_error( 1343 "DC: failed to create transform!\n"); 1344 goto res_create_fail; 1345 } 1346 1347 pool->base.opps[i] = dce110_opp_create(ctx, i); 1348 if (pool->base.opps[i] == NULL) { 1349 BREAK_TO_DEBUGGER(); 1350 dm_error( 1351 "DC: failed to create output pixel processor!\n"); 1352 goto res_create_fail; 1353 } 1354 } 1355 1356 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1357 pool->base.engines[i] = dce110_aux_engine_create(ctx, i); 1358 if (pool->base.engines[i] == NULL) { 1359 BREAK_TO_DEBUGGER(); 1360 dm_error( 1361 "DC:failed to create aux engine!!\n"); 1362 goto res_create_fail; 1363 } 1364 pool->base.hw_i2cs[i] = dce110_i2c_hw_create(ctx, i); 1365 if (pool->base.hw_i2cs[i] == NULL) { 1366 BREAK_TO_DEBUGGER(); 1367 dm_error( 1368 "DC:failed to create i2c engine!!\n"); 1369 goto res_create_fail; 1370 } 1371 pool->base.sw_i2cs[i] = NULL; 1372 } 1373 1374 if (dc->config.fbc_support) 1375 dc->fbc_compressor = dce110_compressor_create(ctx); 1376 1377 if (!underlay_create(ctx, &pool->base)) 1378 goto res_create_fail; 1379 1380 if (!resource_construct(num_virtual_links, dc, &pool->base, 1381 &res_create_funcs)) 1382 goto res_create_fail; 1383 1384 /* Create hardware sequencer */ 1385 dce110_hw_sequencer_construct(dc); 1386 1387 dc->caps.max_planes = pool->base.pipe_count; 1388 1389 for (i = 0; i < pool->base.underlay_pipe_index; ++i) 1390 dc->caps.planes[i] = plane_cap; 1391 1392 dc->caps.planes[pool->base.underlay_pipe_index] = underlay_plane_cap; 1393 1394 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1395 1396 bw_calcs_data_update_from_pplib(dc); 1397 1398 return true; 1399 1400 res_create_fail: 1401 destruct(pool); 1402 return false; 1403 } 1404 1405 struct resource_pool *dce110_create_resource_pool( 1406 uint8_t num_virtual_links, 1407 struct dc *dc, 1408 struct hw_asic_id asic_id) 1409 { 1410 struct dce110_resource_pool *pool = 1411 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1412 1413 if (!pool) 1414 return NULL; 1415 1416 if (construct(num_virtual_links, dc, pool, asic_id)) 1417 return &pool->base; 1418 1419 BREAK_TO_DEBUGGER(); 1420 return NULL; 1421 } 1422