1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "link_encoder.h" 29 #include "stream_encoder.h" 30 31 #include "resource.h" 32 #include "dce110/dce110_resource.h" 33 34 #include "dce/dce_clk_mgr.h" 35 #include "include/irq_service_interface.h" 36 #include "dce/dce_audio.h" 37 #include "dce110/dce110_timing_generator.h" 38 #include "irq/dce110/irq_service_dce110.h" 39 #include "dce110/dce110_timing_generator_v.h" 40 #include "dce/dce_link_encoder.h" 41 #include "dce/dce_stream_encoder.h" 42 #include "dce/dce_mem_input.h" 43 #include "dce110/dce110_mem_input_v.h" 44 #include "dce/dce_ipp.h" 45 #include "dce/dce_transform.h" 46 #include "dce110/dce110_transform_v.h" 47 #include "dce/dce_opp.h" 48 #include "dce110/dce110_opp_v.h" 49 #include "dce/dce_clock_source.h" 50 #include "dce/dce_hwseq.h" 51 #include "dce110/dce110_hw_sequencer.h" 52 #include "dce/dce_aux.h" 53 #include "dce/dce_abm.h" 54 #include "dce/dce_dmcu.h" 55 #include "dce/dce_i2c.h" 56 57 #define DC_LOGGER \ 58 dc->ctx->logger 59 60 #include "dce110/dce110_compressor.h" 61 62 #include "reg_helper.h" 63 64 #include "dce/dce_11_0_d.h" 65 #include "dce/dce_11_0_sh_mask.h" 66 67 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 68 #include "gmc/gmc_8_2_d.h" 69 #include "gmc/gmc_8_2_sh_mask.h" 70 #endif 71 72 #ifndef mmDP_DPHY_INTERNAL_CTRL 73 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 74 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 75 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 76 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 77 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 78 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 79 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 80 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 81 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 82 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 83 #endif 84 85 #ifndef mmBIOS_SCRATCH_2 86 #define mmBIOS_SCRATCH_2 0x05CB 87 #define mmBIOS_SCRATCH_3 0x05CC 88 #define mmBIOS_SCRATCH_6 0x05CF 89 #endif 90 91 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 92 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 93 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 94 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 95 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 96 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 97 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 98 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 99 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 100 #endif 101 102 #ifndef mmDP_DPHY_FAST_TRAINING 103 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 104 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 105 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 106 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 107 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 108 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 109 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 110 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 111 #endif 112 113 #ifndef DPHY_RX_FAST_TRAINING_CAPABLE 114 #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1 115 #endif 116 117 static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = { 118 { 119 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 120 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 121 }, 122 { 123 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 124 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 125 }, 126 { 127 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 128 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 129 }, 130 { 131 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 132 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 133 }, 134 { 135 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 136 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 137 }, 138 { 139 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 140 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 141 } 142 }; 143 144 /* set register offset */ 145 #define SR(reg_name)\ 146 .reg_name = mm ## reg_name 147 148 /* set register offset with instance */ 149 #define SRI(reg_name, block, id)\ 150 .reg_name = mm ## block ## id ## _ ## reg_name 151 152 static const struct clk_mgr_registers disp_clk_regs = { 153 CLK_COMMON_REG_LIST_DCE_BASE() 154 }; 155 156 static const struct clk_mgr_shift disp_clk_shift = { 157 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 158 }; 159 160 static const struct clk_mgr_mask disp_clk_mask = { 161 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 162 }; 163 164 static const struct dce_dmcu_registers dmcu_regs = { 165 DMCU_DCE110_COMMON_REG_LIST() 166 }; 167 168 static const struct dce_dmcu_shift dmcu_shift = { 169 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 170 }; 171 172 static const struct dce_dmcu_mask dmcu_mask = { 173 DMCU_MASK_SH_LIST_DCE110(_MASK) 174 }; 175 176 static const struct dce_abm_registers abm_regs = { 177 ABM_DCE110_COMMON_REG_LIST() 178 }; 179 180 static const struct dce_abm_shift abm_shift = { 181 ABM_MASK_SH_LIST_DCE110(__SHIFT) 182 }; 183 184 static const struct dce_abm_mask abm_mask = { 185 ABM_MASK_SH_LIST_DCE110(_MASK) 186 }; 187 188 #define ipp_regs(id)\ 189 [id] = {\ 190 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 191 } 192 193 static const struct dce_ipp_registers ipp_regs[] = { 194 ipp_regs(0), 195 ipp_regs(1), 196 ipp_regs(2) 197 }; 198 199 static const struct dce_ipp_shift ipp_shift = { 200 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 201 }; 202 203 static const struct dce_ipp_mask ipp_mask = { 204 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 205 }; 206 207 #define transform_regs(id)\ 208 [id] = {\ 209 XFM_COMMON_REG_LIST_DCE110(id)\ 210 } 211 212 static const struct dce_transform_registers xfm_regs[] = { 213 transform_regs(0), 214 transform_regs(1), 215 transform_regs(2) 216 }; 217 218 static const struct dce_transform_shift xfm_shift = { 219 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 220 }; 221 222 static const struct dce_transform_mask xfm_mask = { 223 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 224 }; 225 226 #define aux_regs(id)\ 227 [id] = {\ 228 AUX_REG_LIST(id)\ 229 } 230 231 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 232 aux_regs(0), 233 aux_regs(1), 234 aux_regs(2), 235 aux_regs(3), 236 aux_regs(4), 237 aux_regs(5) 238 }; 239 240 #define hpd_regs(id)\ 241 [id] = {\ 242 HPD_REG_LIST(id)\ 243 } 244 245 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 246 hpd_regs(0), 247 hpd_regs(1), 248 hpd_regs(2), 249 hpd_regs(3), 250 hpd_regs(4), 251 hpd_regs(5) 252 }; 253 254 255 #define link_regs(id)\ 256 [id] = {\ 257 LE_DCE110_REG_LIST(id)\ 258 } 259 260 static const struct dce110_link_enc_registers link_enc_regs[] = { 261 link_regs(0), 262 link_regs(1), 263 link_regs(2), 264 link_regs(3), 265 link_regs(4), 266 link_regs(5), 267 link_regs(6), 268 }; 269 270 #define stream_enc_regs(id)\ 271 [id] = {\ 272 SE_COMMON_REG_LIST(id),\ 273 .TMDS_CNTL = 0,\ 274 } 275 276 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 277 stream_enc_regs(0), 278 stream_enc_regs(1), 279 stream_enc_regs(2) 280 }; 281 282 static const struct dce_stream_encoder_shift se_shift = { 283 SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 284 }; 285 286 static const struct dce_stream_encoder_mask se_mask = { 287 SE_COMMON_MASK_SH_LIST_DCE110(_MASK) 288 }; 289 290 #define opp_regs(id)\ 291 [id] = {\ 292 OPP_DCE_110_REG_LIST(id),\ 293 } 294 295 static const struct dce_opp_registers opp_regs[] = { 296 opp_regs(0), 297 opp_regs(1), 298 opp_regs(2), 299 opp_regs(3), 300 opp_regs(4), 301 opp_regs(5) 302 }; 303 304 static const struct dce_opp_shift opp_shift = { 305 OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT) 306 }; 307 308 static const struct dce_opp_mask opp_mask = { 309 OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK) 310 }; 311 312 #define aux_engine_regs(id)\ 313 [id] = {\ 314 AUX_COMMON_REG_LIST(id), \ 315 .AUX_RESET_MASK = 0 \ 316 } 317 318 static const struct dce110_aux_registers aux_engine_regs[] = { 319 aux_engine_regs(0), 320 aux_engine_regs(1), 321 aux_engine_regs(2), 322 aux_engine_regs(3), 323 aux_engine_regs(4), 324 aux_engine_regs(5) 325 }; 326 327 #define audio_regs(id)\ 328 [id] = {\ 329 AUD_COMMON_REG_LIST(id)\ 330 } 331 332 static const struct dce_audio_registers audio_regs[] = { 333 audio_regs(0), 334 audio_regs(1), 335 audio_regs(2), 336 audio_regs(3), 337 audio_regs(4), 338 audio_regs(5), 339 audio_regs(6), 340 }; 341 342 static const struct dce_audio_shift audio_shift = { 343 AUD_COMMON_MASK_SH_LIST(__SHIFT) 344 }; 345 346 static const struct dce_aduio_mask audio_mask = { 347 AUD_COMMON_MASK_SH_LIST(_MASK) 348 }; 349 350 /* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */ 351 352 353 #define clk_src_regs(id)\ 354 [id] = {\ 355 CS_COMMON_REG_LIST_DCE_100_110(id),\ 356 } 357 358 static const struct dce110_clk_src_regs clk_src_regs[] = { 359 clk_src_regs(0), 360 clk_src_regs(1), 361 clk_src_regs(2) 362 }; 363 364 static const struct dce110_clk_src_shift cs_shift = { 365 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 366 }; 367 368 static const struct dce110_clk_src_mask cs_mask = { 369 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 370 }; 371 372 static const struct bios_registers bios_regs = { 373 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 374 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 375 }; 376 377 static const struct resource_caps carrizo_resource_cap = { 378 .num_timing_generator = 3, 379 .num_video_plane = 1, 380 .num_audio = 3, 381 .num_stream_encoder = 3, 382 .num_pll = 2, 383 .num_ddc = 3, 384 }; 385 386 static const struct resource_caps stoney_resource_cap = { 387 .num_timing_generator = 2, 388 .num_video_plane = 1, 389 .num_audio = 3, 390 .num_stream_encoder = 3, 391 .num_pll = 2, 392 .num_ddc = 3, 393 }; 394 395 #define CTX ctx 396 #define REG(reg) mm ## reg 397 398 #ifndef mmCC_DC_HDMI_STRAPS 399 #define mmCC_DC_HDMI_STRAPS 0x4819 400 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 401 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 402 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 403 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 404 #endif 405 406 static void read_dce_straps( 407 struct dc_context *ctx, 408 struct resource_straps *straps) 409 { 410 REG_GET_2(CC_DC_HDMI_STRAPS, 411 HDMI_DISABLE, &straps->hdmi_disable, 412 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 413 414 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 415 } 416 417 static struct audio *create_audio( 418 struct dc_context *ctx, unsigned int inst) 419 { 420 return dce_audio_create(ctx, inst, 421 &audio_regs[inst], &audio_shift, &audio_mask); 422 } 423 424 static struct timing_generator *dce110_timing_generator_create( 425 struct dc_context *ctx, 426 uint32_t instance, 427 const struct dce110_timing_generator_offsets *offsets) 428 { 429 struct dce110_timing_generator *tg110 = 430 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 431 432 if (!tg110) 433 return NULL; 434 435 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 436 return &tg110->base; 437 } 438 439 static struct stream_encoder *dce110_stream_encoder_create( 440 enum engine_id eng_id, 441 struct dc_context *ctx) 442 { 443 struct dce110_stream_encoder *enc110 = 444 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 445 446 if (!enc110) 447 return NULL; 448 449 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 450 &stream_enc_regs[eng_id], 451 &se_shift, &se_mask); 452 return &enc110->base; 453 } 454 455 #define SRII(reg_name, block, id)\ 456 .reg_name[id] = mm ## block ## id ## _ ## reg_name 457 458 static const struct dce_hwseq_registers hwseq_stoney_reg = { 459 HWSEQ_ST_REG_LIST() 460 }; 461 462 static const struct dce_hwseq_registers hwseq_cz_reg = { 463 HWSEQ_CZ_REG_LIST() 464 }; 465 466 static const struct dce_hwseq_shift hwseq_shift = { 467 HWSEQ_DCE11_MASK_SH_LIST(__SHIFT), 468 }; 469 470 static const struct dce_hwseq_mask hwseq_mask = { 471 HWSEQ_DCE11_MASK_SH_LIST(_MASK), 472 }; 473 474 static struct dce_hwseq *dce110_hwseq_create( 475 struct dc_context *ctx) 476 { 477 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 478 479 if (hws) { 480 hws->ctx = ctx; 481 hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ? 482 &hwseq_stoney_reg : &hwseq_cz_reg; 483 hws->shifts = &hwseq_shift; 484 hws->masks = &hwseq_mask; 485 hws->wa.blnd_crtc_trigger = true; 486 } 487 return hws; 488 } 489 490 static const struct resource_create_funcs res_create_funcs = { 491 .read_dce_straps = read_dce_straps, 492 .create_audio = create_audio, 493 .create_stream_encoder = dce110_stream_encoder_create, 494 .create_hwseq = dce110_hwseq_create, 495 }; 496 497 #define mi_inst_regs(id) { \ 498 MI_DCE11_REG_LIST(id), \ 499 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 500 } 501 static const struct dce_mem_input_registers mi_regs[] = { 502 mi_inst_regs(0), 503 mi_inst_regs(1), 504 mi_inst_regs(2), 505 }; 506 507 static const struct dce_mem_input_shift mi_shifts = { 508 MI_DCE11_MASK_SH_LIST(__SHIFT), 509 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 510 }; 511 512 static const struct dce_mem_input_mask mi_masks = { 513 MI_DCE11_MASK_SH_LIST(_MASK), 514 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 515 }; 516 517 518 static struct mem_input *dce110_mem_input_create( 519 struct dc_context *ctx, 520 uint32_t inst) 521 { 522 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 523 GFP_KERNEL); 524 525 if (!dce_mi) { 526 BREAK_TO_DEBUGGER(); 527 return NULL; 528 } 529 530 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 531 dce_mi->wa.single_head_rdreq_dmif_limit = 3; 532 return &dce_mi->base; 533 } 534 535 static void dce110_transform_destroy(struct transform **xfm) 536 { 537 kfree(TO_DCE_TRANSFORM(*xfm)); 538 *xfm = NULL; 539 } 540 541 static struct transform *dce110_transform_create( 542 struct dc_context *ctx, 543 uint32_t inst) 544 { 545 struct dce_transform *transform = 546 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 547 548 if (!transform) 549 return NULL; 550 551 dce_transform_construct(transform, ctx, inst, 552 &xfm_regs[inst], &xfm_shift, &xfm_mask); 553 return &transform->base; 554 } 555 556 static struct input_pixel_processor *dce110_ipp_create( 557 struct dc_context *ctx, uint32_t inst) 558 { 559 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 560 561 if (!ipp) { 562 BREAK_TO_DEBUGGER(); 563 return NULL; 564 } 565 566 dce_ipp_construct(ipp, ctx, inst, 567 &ipp_regs[inst], &ipp_shift, &ipp_mask); 568 return &ipp->base; 569 } 570 571 static const struct encoder_feature_support link_enc_feature = { 572 .max_hdmi_deep_color = COLOR_DEPTH_121212, 573 .max_hdmi_pixel_clock = 300000, 574 .flags.bits.IS_HBR2_CAPABLE = true, 575 .flags.bits.IS_TPS3_CAPABLE = true 576 }; 577 578 static struct link_encoder *dce110_link_encoder_create( 579 const struct encoder_init_data *enc_init_data) 580 { 581 struct dce110_link_encoder *enc110 = 582 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 583 584 if (!enc110) 585 return NULL; 586 587 dce110_link_encoder_construct(enc110, 588 enc_init_data, 589 &link_enc_feature, 590 &link_enc_regs[enc_init_data->transmitter], 591 &link_enc_aux_regs[enc_init_data->channel - 1], 592 &link_enc_hpd_regs[enc_init_data->hpd_source]); 593 return &enc110->base; 594 } 595 596 static struct output_pixel_processor *dce110_opp_create( 597 struct dc_context *ctx, 598 uint32_t inst) 599 { 600 struct dce110_opp *opp = 601 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 602 603 if (!opp) 604 return NULL; 605 606 dce110_opp_construct(opp, 607 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 608 return &opp->base; 609 } 610 611 struct dce_aux *dce110_aux_engine_create( 612 struct dc_context *ctx, 613 uint32_t inst) 614 { 615 struct aux_engine_dce110 *aux_engine = 616 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 617 618 if (!aux_engine) 619 return NULL; 620 621 dce110_aux_engine_construct(aux_engine, ctx, inst, 622 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 623 &aux_engine_regs[inst]); 624 625 return &aux_engine->base; 626 } 627 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 628 629 static const struct dce_i2c_registers i2c_hw_regs[] = { 630 i2c_inst_regs(1), 631 i2c_inst_regs(2), 632 i2c_inst_regs(3), 633 i2c_inst_regs(4), 634 i2c_inst_regs(5), 635 i2c_inst_regs(6), 636 }; 637 638 static const struct dce_i2c_shift i2c_shifts = { 639 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 640 }; 641 642 static const struct dce_i2c_mask i2c_masks = { 643 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 644 }; 645 646 struct dce_i2c_hw *dce110_i2c_hw_create( 647 struct dc_context *ctx, 648 uint32_t inst) 649 { 650 struct dce_i2c_hw *dce_i2c_hw = 651 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 652 653 if (!dce_i2c_hw) 654 return NULL; 655 656 dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst, 657 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 658 659 return dce_i2c_hw; 660 } 661 struct clock_source *dce110_clock_source_create( 662 struct dc_context *ctx, 663 struct dc_bios *bios, 664 enum clock_source_id id, 665 const struct dce110_clk_src_regs *regs, 666 bool dp_clk_src) 667 { 668 struct dce110_clk_src *clk_src = 669 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 670 671 if (!clk_src) 672 return NULL; 673 674 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 675 regs, &cs_shift, &cs_mask)) { 676 clk_src->base.dp_clk_src = dp_clk_src; 677 return &clk_src->base; 678 } 679 680 BREAK_TO_DEBUGGER(); 681 return NULL; 682 } 683 684 void dce110_clock_source_destroy(struct clock_source **clk_src) 685 { 686 struct dce110_clk_src *dce110_clk_src; 687 688 if (!clk_src) 689 return; 690 691 dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src); 692 693 kfree(dce110_clk_src->dp_ss_params); 694 kfree(dce110_clk_src->hdmi_ss_params); 695 kfree(dce110_clk_src->dvi_ss_params); 696 697 kfree(dce110_clk_src); 698 *clk_src = NULL; 699 } 700 701 static void destruct(struct dce110_resource_pool *pool) 702 { 703 unsigned int i; 704 705 for (i = 0; i < pool->base.pipe_count; i++) { 706 if (pool->base.opps[i] != NULL) 707 dce110_opp_destroy(&pool->base.opps[i]); 708 709 if (pool->base.transforms[i] != NULL) 710 dce110_transform_destroy(&pool->base.transforms[i]); 711 712 if (pool->base.ipps[i] != NULL) 713 dce_ipp_destroy(&pool->base.ipps[i]); 714 715 if (pool->base.mis[i] != NULL) { 716 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 717 pool->base.mis[i] = NULL; 718 } 719 720 if (pool->base.timing_generators[i] != NULL) { 721 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 722 pool->base.timing_generators[i] = NULL; 723 } 724 } 725 726 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 727 if (pool->base.engines[i] != NULL) 728 dce110_engine_destroy(&pool->base.engines[i]); 729 if (pool->base.hw_i2cs[i] != NULL) { 730 kfree(pool->base.hw_i2cs[i]); 731 pool->base.hw_i2cs[i] = NULL; 732 } 733 if (pool->base.sw_i2cs[i] != NULL) { 734 kfree(pool->base.sw_i2cs[i]); 735 pool->base.sw_i2cs[i] = NULL; 736 } 737 } 738 739 for (i = 0; i < pool->base.stream_enc_count; i++) { 740 if (pool->base.stream_enc[i] != NULL) 741 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 742 } 743 744 for (i = 0; i < pool->base.clk_src_count; i++) { 745 if (pool->base.clock_sources[i] != NULL) { 746 dce110_clock_source_destroy(&pool->base.clock_sources[i]); 747 } 748 } 749 750 if (pool->base.dp_clock_source != NULL) 751 dce110_clock_source_destroy(&pool->base.dp_clock_source); 752 753 for (i = 0; i < pool->base.audio_count; i++) { 754 if (pool->base.audios[i] != NULL) { 755 dce_aud_destroy(&pool->base.audios[i]); 756 } 757 } 758 759 if (pool->base.abm != NULL) 760 dce_abm_destroy(&pool->base.abm); 761 762 if (pool->base.dmcu != NULL) 763 dce_dmcu_destroy(&pool->base.dmcu); 764 765 if (pool->base.clk_mgr != NULL) 766 dce_clk_mgr_destroy(&pool->base.clk_mgr); 767 768 if (pool->base.irqs != NULL) { 769 dal_irq_service_destroy(&pool->base.irqs); 770 } 771 } 772 773 774 static void get_pixel_clock_parameters( 775 const struct pipe_ctx *pipe_ctx, 776 struct pixel_clk_params *pixel_clk_params) 777 { 778 const struct dc_stream_state *stream = pipe_ctx->stream; 779 780 /*TODO: is this halved for YCbCr 420? in that case we might want to move 781 * the pixel clock normalization for hdmi up to here instead of doing it 782 * in pll_adjust_pix_clk 783 */ 784 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 785 pixel_clk_params->encoder_object_id = stream->link->link_enc->id; 786 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 787 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 788 /* TODO: un-hardcode*/ 789 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 790 LINK_RATE_REF_FREQ_IN_KHZ; 791 pixel_clk_params->flags.ENABLE_SS = 0; 792 pixel_clk_params->color_depth = 793 stream->timing.display_color_depth; 794 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 795 pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding == 796 PIXEL_ENCODING_YCBCR420); 797 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 798 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) { 799 pixel_clk_params->color_depth = COLOR_DEPTH_888; 800 } 801 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 802 pixel_clk_params->requested_pix_clk_100hz = pixel_clk_params->requested_pix_clk_100hz / 2; 803 } 804 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 805 pixel_clk_params->requested_pix_clk_100hz *= 2; 806 807 } 808 809 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 810 { 811 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 812 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 813 pipe_ctx->clock_source, 814 &pipe_ctx->stream_res.pix_clk_params, 815 &pipe_ctx->pll_settings); 816 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 817 &pipe_ctx->stream->bit_depth_params); 818 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 819 } 820 821 static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx) 822 { 823 if (pipe_ctx->pipe_idx != underlay_idx) 824 return true; 825 if (!pipe_ctx->plane_state) 826 return false; 827 if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 828 return false; 829 return true; 830 } 831 832 static enum dc_status build_mapped_resource( 833 const struct dc *dc, 834 struct dc_state *context, 835 struct dc_stream_state *stream) 836 { 837 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 838 839 if (!pipe_ctx) 840 return DC_ERROR_UNEXPECTED; 841 842 if (!is_surface_pixel_format_supported(pipe_ctx, 843 dc->res_pool->underlay_pipe_index)) 844 return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; 845 846 dce110_resource_build_pipe_hw_param(pipe_ctx); 847 848 /* TODO: validate audio ASIC caps, encoder */ 849 850 resource_build_info_frame(pipe_ctx); 851 852 return DC_OK; 853 } 854 855 static bool dce110_validate_bandwidth( 856 struct dc *dc, 857 struct dc_state *context) 858 { 859 bool result = false; 860 861 DC_LOG_BANDWIDTH_CALCS( 862 "%s: start", 863 __func__); 864 865 if (bw_calcs( 866 dc->ctx, 867 dc->bw_dceip, 868 dc->bw_vbios, 869 context->res_ctx.pipe_ctx, 870 dc->res_pool->pipe_count, 871 &context->bw.dce)) 872 result = true; 873 874 if (!result) 875 DC_LOG_BANDWIDTH_VALIDATION("%s: %dx%d@%d Bandwidth validation failed!\n", 876 __func__, 877 context->streams[0]->timing.h_addressable, 878 context->streams[0]->timing.v_addressable, 879 context->streams[0]->timing.pix_clk_100hz / 10); 880 881 if (memcmp(&dc->current_state->bw.dce, 882 &context->bw.dce, sizeof(context->bw.dce))) { 883 884 DC_LOG_BANDWIDTH_CALCS( 885 "%s: finish,\n" 886 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 887 "stutMark_b: %d stutMark_a: %d\n" 888 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 889 "stutMark_b: %d stutMark_a: %d\n" 890 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 891 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n" 892 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" 893 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n" 894 , 895 __func__, 896 context->bw.dce.nbp_state_change_wm_ns[0].b_mark, 897 context->bw.dce.nbp_state_change_wm_ns[0].a_mark, 898 context->bw.dce.urgent_wm_ns[0].b_mark, 899 context->bw.dce.urgent_wm_ns[0].a_mark, 900 context->bw.dce.stutter_exit_wm_ns[0].b_mark, 901 context->bw.dce.stutter_exit_wm_ns[0].a_mark, 902 context->bw.dce.nbp_state_change_wm_ns[1].b_mark, 903 context->bw.dce.nbp_state_change_wm_ns[1].a_mark, 904 context->bw.dce.urgent_wm_ns[1].b_mark, 905 context->bw.dce.urgent_wm_ns[1].a_mark, 906 context->bw.dce.stutter_exit_wm_ns[1].b_mark, 907 context->bw.dce.stutter_exit_wm_ns[1].a_mark, 908 context->bw.dce.nbp_state_change_wm_ns[2].b_mark, 909 context->bw.dce.nbp_state_change_wm_ns[2].a_mark, 910 context->bw.dce.urgent_wm_ns[2].b_mark, 911 context->bw.dce.urgent_wm_ns[2].a_mark, 912 context->bw.dce.stutter_exit_wm_ns[2].b_mark, 913 context->bw.dce.stutter_exit_wm_ns[2].a_mark, 914 context->bw.dce.stutter_mode_enable, 915 context->bw.dce.cpuc_state_change_enable, 916 context->bw.dce.cpup_state_change_enable, 917 context->bw.dce.nbp_state_change_enable, 918 context->bw.dce.all_displays_in_sync, 919 context->bw.dce.dispclk_khz, 920 context->bw.dce.sclk_khz, 921 context->bw.dce.sclk_deep_sleep_khz, 922 context->bw.dce.yclk_khz, 923 context->bw.dce.blackout_recovery_time_us); 924 } 925 return result; 926 } 927 928 enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state, 929 struct dc_caps *caps) 930 { 931 if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) || 932 ((plane_state->dst_rect.height * 2) < plane_state->src_rect.height)) 933 return DC_FAIL_SURFACE_VALIDATE; 934 935 return DC_OK; 936 } 937 938 static bool dce110_validate_surface_sets( 939 struct dc_state *context) 940 { 941 int i, j; 942 943 for (i = 0; i < context->stream_count; i++) { 944 if (context->stream_status[i].plane_count == 0) 945 continue; 946 947 if (context->stream_status[i].plane_count > 2) 948 return false; 949 950 for (j = 0; j < context->stream_status[i].plane_count; j++) { 951 struct dc_plane_state *plane = 952 context->stream_status[i].plane_states[j]; 953 954 /* underlay validation */ 955 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 956 957 if ((plane->src_rect.width > 1920 || 958 plane->src_rect.height > 1080)) 959 return false; 960 961 /* we don't have the logic to support underlay 962 * only yet so block the use case where we get 963 * NV12 plane as top layer 964 */ 965 if (j == 0) 966 return false; 967 968 /* irrespective of plane format, 969 * stream should be RGB encoded 970 */ 971 if (context->streams[i]->timing.pixel_encoding 972 != PIXEL_ENCODING_RGB) 973 return false; 974 975 } 976 977 } 978 } 979 980 return true; 981 } 982 983 enum dc_status dce110_validate_global( 984 struct dc *dc, 985 struct dc_state *context) 986 { 987 if (!dce110_validate_surface_sets(context)) 988 return DC_FAIL_SURFACE_VALIDATE; 989 990 return DC_OK; 991 } 992 993 static enum dc_status dce110_add_stream_to_ctx( 994 struct dc *dc, 995 struct dc_state *new_ctx, 996 struct dc_stream_state *dc_stream) 997 { 998 enum dc_status result = DC_ERROR_UNEXPECTED; 999 1000 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1001 1002 if (result == DC_OK) 1003 result = resource_map_clock_resources(dc, new_ctx, dc_stream); 1004 1005 1006 if (result == DC_OK) 1007 result = build_mapped_resource(dc, new_ctx, dc_stream); 1008 1009 return result; 1010 } 1011 1012 static struct pipe_ctx *dce110_acquire_underlay( 1013 struct dc_state *context, 1014 const struct resource_pool *pool, 1015 struct dc_stream_state *stream) 1016 { 1017 struct dc *dc = stream->ctx->dc; 1018 struct resource_context *res_ctx = &context->res_ctx; 1019 unsigned int underlay_idx = pool->underlay_pipe_index; 1020 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; 1021 1022 if (res_ctx->pipe_ctx[underlay_idx].stream) 1023 return NULL; 1024 1025 pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx]; 1026 pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; 1027 /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/ 1028 pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; 1029 pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; 1030 pipe_ctx->pipe_idx = underlay_idx; 1031 1032 pipe_ctx->stream = stream; 1033 1034 if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) { 1035 struct tg_color black_color = {0}; 1036 struct dc_bios *dcb = dc->ctx->dc_bios; 1037 1038 dc->hwss.enable_display_power_gating( 1039 dc, 1040 pipe_ctx->stream_res.tg->inst, 1041 dcb, PIPE_GATING_CONTROL_DISABLE); 1042 1043 /* 1044 * This is for powering on underlay, so crtc does not 1045 * need to be enabled 1046 */ 1047 1048 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg, 1049 &stream->timing, 1050 false); 1051 1052 pipe_ctx->stream_res.tg->funcs->enable_advanced_request( 1053 pipe_ctx->stream_res.tg, 1054 true, 1055 &stream->timing); 1056 1057 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi, 1058 stream->timing.h_total, 1059 stream->timing.v_total, 1060 stream->timing.pix_clk_100hz / 10, 1061 context->stream_count); 1062 1063 color_space_to_black_color(dc, 1064 COLOR_SPACE_YCBCR601, &black_color); 1065 pipe_ctx->stream_res.tg->funcs->set_blank_color( 1066 pipe_ctx->stream_res.tg, 1067 &black_color); 1068 } 1069 1070 return pipe_ctx; 1071 } 1072 1073 static void dce110_destroy_resource_pool(struct resource_pool **pool) 1074 { 1075 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 1076 1077 destruct(dce110_pool); 1078 kfree(dce110_pool); 1079 *pool = NULL; 1080 } 1081 1082 1083 static const struct resource_funcs dce110_res_pool_funcs = { 1084 .destroy = dce110_destroy_resource_pool, 1085 .link_enc_create = dce110_link_encoder_create, 1086 .validate_bandwidth = dce110_validate_bandwidth, 1087 .validate_plane = dce110_validate_plane, 1088 .acquire_idle_pipe_for_layer = dce110_acquire_underlay, 1089 .add_stream_to_ctx = dce110_add_stream_to_ctx, 1090 .validate_global = dce110_validate_global 1091 }; 1092 1093 static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) 1094 { 1095 struct dce110_timing_generator *dce110_tgv = kzalloc(sizeof(*dce110_tgv), 1096 GFP_KERNEL); 1097 struct dce_transform *dce110_xfmv = kzalloc(sizeof(*dce110_xfmv), 1098 GFP_KERNEL); 1099 struct dce_mem_input *dce110_miv = kzalloc(sizeof(*dce110_miv), 1100 GFP_KERNEL); 1101 struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv), 1102 GFP_KERNEL); 1103 1104 if (!dce110_tgv || !dce110_xfmv || !dce110_miv || !dce110_oppv) { 1105 kfree(dce110_tgv); 1106 kfree(dce110_xfmv); 1107 kfree(dce110_miv); 1108 kfree(dce110_oppv); 1109 return false; 1110 } 1111 1112 dce110_opp_v_construct(dce110_oppv, ctx); 1113 1114 dce110_timing_generator_v_construct(dce110_tgv, ctx); 1115 dce110_mem_input_v_construct(dce110_miv, ctx); 1116 dce110_transform_v_construct(dce110_xfmv, ctx); 1117 1118 pool->opps[pool->pipe_count] = &dce110_oppv->base; 1119 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; 1120 pool->mis[pool->pipe_count] = &dce110_miv->base; 1121 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; 1122 pool->pipe_count++; 1123 1124 /* update the public caps to indicate an underlay is available */ 1125 ctx->dc->caps.max_slave_planes = 1; 1126 ctx->dc->caps.max_slave_planes = 1; 1127 1128 return true; 1129 } 1130 1131 static void bw_calcs_data_update_from_pplib(struct dc *dc) 1132 { 1133 struct dm_pp_clock_levels clks = {0}; 1134 1135 /*do system clock*/ 1136 dm_pp_get_clock_levels_by_type( 1137 dc->ctx, 1138 DM_PP_CLOCK_TYPE_ENGINE_CLK, 1139 &clks); 1140 /* convert all the clock fro kHz to fix point mHz */ 1141 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 1142 clks.clocks_in_khz[clks.num_levels-1], 1000); 1143 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 1144 clks.clocks_in_khz[clks.num_levels/8], 1000); 1145 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 1146 clks.clocks_in_khz[clks.num_levels*2/8], 1000); 1147 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 1148 clks.clocks_in_khz[clks.num_levels*3/8], 1000); 1149 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 1150 clks.clocks_in_khz[clks.num_levels*4/8], 1000); 1151 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 1152 clks.clocks_in_khz[clks.num_levels*5/8], 1000); 1153 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1154 clks.clocks_in_khz[clks.num_levels*6/8], 1000); 1155 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1156 clks.clocks_in_khz[0], 1000); 1157 dc->sclk_lvls = clks; 1158 1159 /*do display clock*/ 1160 dm_pp_get_clock_levels_by_type( 1161 dc->ctx, 1162 DM_PP_CLOCK_TYPE_DISPLAY_CLK, 1163 &clks); 1164 dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed( 1165 clks.clocks_in_khz[clks.num_levels-1], 1000); 1166 dc->bw_vbios->mid_voltage_max_dispclk = bw_frc_to_fixed( 1167 clks.clocks_in_khz[clks.num_levels>>1], 1000); 1168 dc->bw_vbios->low_voltage_max_dispclk = bw_frc_to_fixed( 1169 clks.clocks_in_khz[0], 1000); 1170 1171 /*do memory clock*/ 1172 dm_pp_get_clock_levels_by_type( 1173 dc->ctx, 1174 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1175 &clks); 1176 1177 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1178 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER_CZ, 1000); 1179 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1180 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ, 1181 1000); 1182 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1183 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER_CZ, 1184 1000); 1185 } 1186 1187 const struct resource_caps *dce110_resource_cap( 1188 struct hw_asic_id *asic_id) 1189 { 1190 if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev)) 1191 return &stoney_resource_cap; 1192 else 1193 return &carrizo_resource_cap; 1194 } 1195 1196 static bool construct( 1197 uint8_t num_virtual_links, 1198 struct dc *dc, 1199 struct dce110_resource_pool *pool, 1200 struct hw_asic_id asic_id) 1201 { 1202 unsigned int i; 1203 struct dc_context *ctx = dc->ctx; 1204 struct dc_firmware_info info; 1205 struct dc_bios *bp; 1206 1207 ctx->dc_bios->regs = &bios_regs; 1208 1209 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); 1210 pool->base.funcs = &dce110_res_pool_funcs; 1211 1212 /************************************************* 1213 * Resource + asic cap harcoding * 1214 *************************************************/ 1215 1216 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1217 pool->base.underlay_pipe_index = pool->base.pipe_count; 1218 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1219 dc->caps.max_downscale_ratio = 150; 1220 dc->caps.i2c_speed_in_khz = 100; 1221 dc->caps.max_cursor_size = 128; 1222 dc->caps.is_apu = true; 1223 1224 /************************************************* 1225 * Create resources * 1226 *************************************************/ 1227 1228 bp = ctx->dc_bios; 1229 1230 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1231 info.external_clock_source_frequency_for_dp != 0) { 1232 pool->base.dp_clock_source = 1233 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1234 1235 pool->base.clock_sources[0] = 1236 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, 1237 &clk_src_regs[0], false); 1238 pool->base.clock_sources[1] = 1239 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, 1240 &clk_src_regs[1], false); 1241 1242 pool->base.clk_src_count = 2; 1243 1244 /* TODO: find out if CZ support 3 PLLs */ 1245 } 1246 1247 if (pool->base.dp_clock_source == NULL) { 1248 dm_error("DC: failed to create dp clock source!\n"); 1249 BREAK_TO_DEBUGGER(); 1250 goto res_create_fail; 1251 } 1252 1253 for (i = 0; i < pool->base.clk_src_count; i++) { 1254 if (pool->base.clock_sources[i] == NULL) { 1255 dm_error("DC: failed to create clock sources!\n"); 1256 BREAK_TO_DEBUGGER(); 1257 goto res_create_fail; 1258 } 1259 } 1260 1261 pool->base.clk_mgr = dce110_clk_mgr_create(ctx, 1262 &disp_clk_regs, 1263 &disp_clk_shift, 1264 &disp_clk_mask); 1265 if (pool->base.clk_mgr == NULL) { 1266 dm_error("DC: failed to create display clock!\n"); 1267 BREAK_TO_DEBUGGER(); 1268 goto res_create_fail; 1269 } 1270 1271 pool->base.dmcu = dce_dmcu_create(ctx, 1272 &dmcu_regs, 1273 &dmcu_shift, 1274 &dmcu_mask); 1275 if (pool->base.dmcu == NULL) { 1276 dm_error("DC: failed to create dmcu!\n"); 1277 BREAK_TO_DEBUGGER(); 1278 goto res_create_fail; 1279 } 1280 1281 pool->base.abm = dce_abm_create(ctx, 1282 &abm_regs, 1283 &abm_shift, 1284 &abm_mask); 1285 if (pool->base.abm == NULL) { 1286 dm_error("DC: failed to create abm!\n"); 1287 BREAK_TO_DEBUGGER(); 1288 goto res_create_fail; 1289 } 1290 1291 { 1292 struct irq_service_init_data init_data; 1293 init_data.ctx = dc->ctx; 1294 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 1295 if (!pool->base.irqs) 1296 goto res_create_fail; 1297 } 1298 1299 for (i = 0; i < pool->base.pipe_count; i++) { 1300 pool->base.timing_generators[i] = dce110_timing_generator_create( 1301 ctx, i, &dce110_tg_offsets[i]); 1302 if (pool->base.timing_generators[i] == NULL) { 1303 BREAK_TO_DEBUGGER(); 1304 dm_error("DC: failed to create tg!\n"); 1305 goto res_create_fail; 1306 } 1307 1308 pool->base.mis[i] = dce110_mem_input_create(ctx, i); 1309 if (pool->base.mis[i] == NULL) { 1310 BREAK_TO_DEBUGGER(); 1311 dm_error( 1312 "DC: failed to create memory input!\n"); 1313 goto res_create_fail; 1314 } 1315 1316 pool->base.ipps[i] = dce110_ipp_create(ctx, i); 1317 if (pool->base.ipps[i] == NULL) { 1318 BREAK_TO_DEBUGGER(); 1319 dm_error( 1320 "DC: failed to create input pixel processor!\n"); 1321 goto res_create_fail; 1322 } 1323 1324 pool->base.transforms[i] = dce110_transform_create(ctx, i); 1325 if (pool->base.transforms[i] == NULL) { 1326 BREAK_TO_DEBUGGER(); 1327 dm_error( 1328 "DC: failed to create transform!\n"); 1329 goto res_create_fail; 1330 } 1331 1332 pool->base.opps[i] = dce110_opp_create(ctx, i); 1333 if (pool->base.opps[i] == NULL) { 1334 BREAK_TO_DEBUGGER(); 1335 dm_error( 1336 "DC: failed to create output pixel processor!\n"); 1337 goto res_create_fail; 1338 } 1339 } 1340 1341 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1342 pool->base.engines[i] = dce110_aux_engine_create(ctx, i); 1343 if (pool->base.engines[i] == NULL) { 1344 BREAK_TO_DEBUGGER(); 1345 dm_error( 1346 "DC:failed to create aux engine!!\n"); 1347 goto res_create_fail; 1348 } 1349 pool->base.hw_i2cs[i] = dce110_i2c_hw_create(ctx, i); 1350 if (pool->base.hw_i2cs[i] == NULL) { 1351 BREAK_TO_DEBUGGER(); 1352 dm_error( 1353 "DC:failed to create i2c engine!!\n"); 1354 goto res_create_fail; 1355 } 1356 pool->base.sw_i2cs[i] = NULL; 1357 } 1358 1359 if (dc->config.fbc_support) 1360 dc->fbc_compressor = dce110_compressor_create(ctx); 1361 1362 if (!underlay_create(ctx, &pool->base)) 1363 goto res_create_fail; 1364 1365 if (!resource_construct(num_virtual_links, dc, &pool->base, 1366 &res_create_funcs)) 1367 goto res_create_fail; 1368 1369 /* Create hardware sequencer */ 1370 dce110_hw_sequencer_construct(dc); 1371 1372 dc->caps.max_planes = pool->base.pipe_count; 1373 1374 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1375 1376 bw_calcs_data_update_from_pplib(dc); 1377 1378 return true; 1379 1380 res_create_fail: 1381 destruct(pool); 1382 return false; 1383 } 1384 1385 struct resource_pool *dce110_create_resource_pool( 1386 uint8_t num_virtual_links, 1387 struct dc *dc, 1388 struct hw_asic_id asic_id) 1389 { 1390 struct dce110_resource_pool *pool = 1391 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1392 1393 if (!pool) 1394 return NULL; 1395 1396 if (construct(num_virtual_links, dc, pool, asic_id)) 1397 return &pool->base; 1398 1399 BREAK_TO_DEBUGGER(); 1400 return NULL; 1401 } 1402