1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "link_encoder.h" 29 #include "stream_encoder.h" 30 31 #include "resource.h" 32 #include "dce110/dce110_resource.h" 33 34 #include "include/irq_service_interface.h" 35 #include "dce/dce_audio.h" 36 #include "dce110/dce110_timing_generator.h" 37 #include "irq/dce110/irq_service_dce110.h" 38 #include "dce110/dce110_timing_generator_v.h" 39 #include "dce/dce_link_encoder.h" 40 #include "dce/dce_stream_encoder.h" 41 #include "dce/dce_mem_input.h" 42 #include "dce110/dce110_mem_input_v.h" 43 #include "dce/dce_ipp.h" 44 #include "dce/dce_transform.h" 45 #include "dce110/dce110_transform_v.h" 46 #include "dce/dce_opp.h" 47 #include "dce110/dce110_opp_v.h" 48 #include "dce/dce_clocks.h" 49 #include "dce/dce_clock_source.h" 50 #include "dce/dce_hwseq.h" 51 #include "dce110/dce110_hw_sequencer.h" 52 #include "dce/dce_abm.h" 53 #include "dce/dce_dmcu.h" 54 55 #define DC_LOGGER \ 56 dc->ctx->logger 57 58 #include "dce110/dce110_compressor.h" 59 60 #include "reg_helper.h" 61 62 #include "dce/dce_11_0_d.h" 63 #include "dce/dce_11_0_sh_mask.h" 64 65 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 66 #include "gmc/gmc_8_2_d.h" 67 #include "gmc/gmc_8_2_sh_mask.h" 68 #endif 69 70 #ifndef mmDP_DPHY_INTERNAL_CTRL 71 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 72 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 73 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 74 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 75 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 76 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 77 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 78 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 79 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 80 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 81 #endif 82 83 #ifndef mmBIOS_SCRATCH_2 84 #define mmBIOS_SCRATCH_2 0x05CB 85 #define mmBIOS_SCRATCH_6 0x05CF 86 #endif 87 88 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 89 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 90 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 91 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 92 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 93 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 94 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 95 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 96 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 97 #endif 98 99 #ifndef mmDP_DPHY_FAST_TRAINING 100 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 101 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 102 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 103 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 104 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 105 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 106 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 107 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 108 #endif 109 110 #ifndef DPHY_RX_FAST_TRAINING_CAPABLE 111 #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1 112 #endif 113 114 static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = { 115 { 116 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 117 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 118 }, 119 { 120 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 121 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 122 }, 123 { 124 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 125 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 126 }, 127 { 128 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 129 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 130 }, 131 { 132 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 133 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 134 }, 135 { 136 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 137 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 138 } 139 }; 140 141 /* set register offset */ 142 #define SR(reg_name)\ 143 .reg_name = mm ## reg_name 144 145 /* set register offset with instance */ 146 #define SRI(reg_name, block, id)\ 147 .reg_name = mm ## block ## id ## _ ## reg_name 148 149 static const struct dccg_registers disp_clk_regs = { 150 CLK_COMMON_REG_LIST_DCE_BASE() 151 }; 152 153 static const struct dccg_shift disp_clk_shift = { 154 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 155 }; 156 157 static const struct dccg_mask disp_clk_mask = { 158 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 159 }; 160 161 static const struct dce_dmcu_registers dmcu_regs = { 162 DMCU_DCE110_COMMON_REG_LIST() 163 }; 164 165 static const struct dce_dmcu_shift dmcu_shift = { 166 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 167 }; 168 169 static const struct dce_dmcu_mask dmcu_mask = { 170 DMCU_MASK_SH_LIST_DCE110(_MASK) 171 }; 172 173 static const struct dce_abm_registers abm_regs = { 174 ABM_DCE110_COMMON_REG_LIST() 175 }; 176 177 static const struct dce_abm_shift abm_shift = { 178 ABM_MASK_SH_LIST_DCE110(__SHIFT) 179 }; 180 181 static const struct dce_abm_mask abm_mask = { 182 ABM_MASK_SH_LIST_DCE110(_MASK) 183 }; 184 185 #define ipp_regs(id)\ 186 [id] = {\ 187 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 188 } 189 190 static const struct dce_ipp_registers ipp_regs[] = { 191 ipp_regs(0), 192 ipp_regs(1), 193 ipp_regs(2) 194 }; 195 196 static const struct dce_ipp_shift ipp_shift = { 197 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 198 }; 199 200 static const struct dce_ipp_mask ipp_mask = { 201 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 202 }; 203 204 #define transform_regs(id)\ 205 [id] = {\ 206 XFM_COMMON_REG_LIST_DCE110(id)\ 207 } 208 209 static const struct dce_transform_registers xfm_regs[] = { 210 transform_regs(0), 211 transform_regs(1), 212 transform_regs(2) 213 }; 214 215 static const struct dce_transform_shift xfm_shift = { 216 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 217 }; 218 219 static const struct dce_transform_mask xfm_mask = { 220 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 221 }; 222 223 #define aux_regs(id)\ 224 [id] = {\ 225 AUX_REG_LIST(id)\ 226 } 227 228 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 229 aux_regs(0), 230 aux_regs(1), 231 aux_regs(2), 232 aux_regs(3), 233 aux_regs(4), 234 aux_regs(5) 235 }; 236 237 #define hpd_regs(id)\ 238 [id] = {\ 239 HPD_REG_LIST(id)\ 240 } 241 242 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 243 hpd_regs(0), 244 hpd_regs(1), 245 hpd_regs(2), 246 hpd_regs(3), 247 hpd_regs(4), 248 hpd_regs(5) 249 }; 250 251 252 #define link_regs(id)\ 253 [id] = {\ 254 LE_DCE110_REG_LIST(id)\ 255 } 256 257 static const struct dce110_link_enc_registers link_enc_regs[] = { 258 link_regs(0), 259 link_regs(1), 260 link_regs(2), 261 link_regs(3), 262 link_regs(4), 263 link_regs(5), 264 link_regs(6), 265 }; 266 267 #define stream_enc_regs(id)\ 268 [id] = {\ 269 SE_COMMON_REG_LIST(id),\ 270 .TMDS_CNTL = 0,\ 271 } 272 273 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 274 stream_enc_regs(0), 275 stream_enc_regs(1), 276 stream_enc_regs(2) 277 }; 278 279 static const struct dce_stream_encoder_shift se_shift = { 280 SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 281 }; 282 283 static const struct dce_stream_encoder_mask se_mask = { 284 SE_COMMON_MASK_SH_LIST_DCE110(_MASK) 285 }; 286 287 #define opp_regs(id)\ 288 [id] = {\ 289 OPP_DCE_110_REG_LIST(id),\ 290 } 291 292 static const struct dce_opp_registers opp_regs[] = { 293 opp_regs(0), 294 opp_regs(1), 295 opp_regs(2), 296 opp_regs(3), 297 opp_regs(4), 298 opp_regs(5) 299 }; 300 301 static const struct dce_opp_shift opp_shift = { 302 OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT) 303 }; 304 305 static const struct dce_opp_mask opp_mask = { 306 OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK) 307 }; 308 309 #define audio_regs(id)\ 310 [id] = {\ 311 AUD_COMMON_REG_LIST(id)\ 312 } 313 314 static const struct dce_audio_registers audio_regs[] = { 315 audio_regs(0), 316 audio_regs(1), 317 audio_regs(2), 318 audio_regs(3), 319 audio_regs(4), 320 audio_regs(5), 321 audio_regs(6), 322 }; 323 324 static const struct dce_audio_shift audio_shift = { 325 AUD_COMMON_MASK_SH_LIST(__SHIFT) 326 }; 327 328 static const struct dce_aduio_mask audio_mask = { 329 AUD_COMMON_MASK_SH_LIST(_MASK) 330 }; 331 332 /* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */ 333 334 335 #define clk_src_regs(id)\ 336 [id] = {\ 337 CS_COMMON_REG_LIST_DCE_100_110(id),\ 338 } 339 340 static const struct dce110_clk_src_regs clk_src_regs[] = { 341 clk_src_regs(0), 342 clk_src_regs(1), 343 clk_src_regs(2) 344 }; 345 346 static const struct dce110_clk_src_shift cs_shift = { 347 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 348 }; 349 350 static const struct dce110_clk_src_mask cs_mask = { 351 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 352 }; 353 354 static const struct bios_registers bios_regs = { 355 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 356 }; 357 358 static const struct resource_caps carrizo_resource_cap = { 359 .num_timing_generator = 3, 360 .num_video_plane = 1, 361 .num_audio = 3, 362 .num_stream_encoder = 3, 363 .num_pll = 2, 364 }; 365 366 static const struct resource_caps stoney_resource_cap = { 367 .num_timing_generator = 2, 368 .num_video_plane = 1, 369 .num_audio = 3, 370 .num_stream_encoder = 3, 371 .num_pll = 2, 372 }; 373 374 #define CTX ctx 375 #define REG(reg) mm ## reg 376 377 #ifndef mmCC_DC_HDMI_STRAPS 378 #define mmCC_DC_HDMI_STRAPS 0x4819 379 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 380 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 381 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 382 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 383 #endif 384 385 static void read_dce_straps( 386 struct dc_context *ctx, 387 struct resource_straps *straps) 388 { 389 REG_GET_2(CC_DC_HDMI_STRAPS, 390 HDMI_DISABLE, &straps->hdmi_disable, 391 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 392 393 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 394 } 395 396 static struct audio *create_audio( 397 struct dc_context *ctx, unsigned int inst) 398 { 399 return dce_audio_create(ctx, inst, 400 &audio_regs[inst], &audio_shift, &audio_mask); 401 } 402 403 static struct timing_generator *dce110_timing_generator_create( 404 struct dc_context *ctx, 405 uint32_t instance, 406 const struct dce110_timing_generator_offsets *offsets) 407 { 408 struct dce110_timing_generator *tg110 = 409 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 410 411 if (!tg110) 412 return NULL; 413 414 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 415 return &tg110->base; 416 } 417 418 static struct stream_encoder *dce110_stream_encoder_create( 419 enum engine_id eng_id, 420 struct dc_context *ctx) 421 { 422 struct dce110_stream_encoder *enc110 = 423 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 424 425 if (!enc110) 426 return NULL; 427 428 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 429 &stream_enc_regs[eng_id], 430 &se_shift, &se_mask); 431 return &enc110->base; 432 } 433 434 #define SRII(reg_name, block, id)\ 435 .reg_name[id] = mm ## block ## id ## _ ## reg_name 436 437 static const struct dce_hwseq_registers hwseq_stoney_reg = { 438 HWSEQ_ST_REG_LIST() 439 }; 440 441 static const struct dce_hwseq_registers hwseq_cz_reg = { 442 HWSEQ_CZ_REG_LIST() 443 }; 444 445 static const struct dce_hwseq_shift hwseq_shift = { 446 HWSEQ_DCE11_MASK_SH_LIST(__SHIFT), 447 }; 448 449 static const struct dce_hwseq_mask hwseq_mask = { 450 HWSEQ_DCE11_MASK_SH_LIST(_MASK), 451 }; 452 453 static struct dce_hwseq *dce110_hwseq_create( 454 struct dc_context *ctx) 455 { 456 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 457 458 if (hws) { 459 hws->ctx = ctx; 460 hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ? 461 &hwseq_stoney_reg : &hwseq_cz_reg; 462 hws->shifts = &hwseq_shift; 463 hws->masks = &hwseq_mask; 464 hws->wa.blnd_crtc_trigger = true; 465 } 466 return hws; 467 } 468 469 static const struct resource_create_funcs res_create_funcs = { 470 .read_dce_straps = read_dce_straps, 471 .create_audio = create_audio, 472 .create_stream_encoder = dce110_stream_encoder_create, 473 .create_hwseq = dce110_hwseq_create, 474 }; 475 476 #define mi_inst_regs(id) { \ 477 MI_DCE11_REG_LIST(id), \ 478 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 479 } 480 static const struct dce_mem_input_registers mi_regs[] = { 481 mi_inst_regs(0), 482 mi_inst_regs(1), 483 mi_inst_regs(2), 484 }; 485 486 static const struct dce_mem_input_shift mi_shifts = { 487 MI_DCE11_MASK_SH_LIST(__SHIFT), 488 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 489 }; 490 491 static const struct dce_mem_input_mask mi_masks = { 492 MI_DCE11_MASK_SH_LIST(_MASK), 493 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 494 }; 495 496 497 static struct mem_input *dce110_mem_input_create( 498 struct dc_context *ctx, 499 uint32_t inst) 500 { 501 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 502 GFP_KERNEL); 503 504 if (!dce_mi) { 505 BREAK_TO_DEBUGGER(); 506 return NULL; 507 } 508 509 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 510 dce_mi->wa.single_head_rdreq_dmif_limit = 3; 511 return &dce_mi->base; 512 } 513 514 static void dce110_transform_destroy(struct transform **xfm) 515 { 516 kfree(TO_DCE_TRANSFORM(*xfm)); 517 *xfm = NULL; 518 } 519 520 static struct transform *dce110_transform_create( 521 struct dc_context *ctx, 522 uint32_t inst) 523 { 524 struct dce_transform *transform = 525 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 526 527 if (!transform) 528 return NULL; 529 530 dce_transform_construct(transform, ctx, inst, 531 &xfm_regs[inst], &xfm_shift, &xfm_mask); 532 return &transform->base; 533 } 534 535 static struct input_pixel_processor *dce110_ipp_create( 536 struct dc_context *ctx, uint32_t inst) 537 { 538 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 539 540 if (!ipp) { 541 BREAK_TO_DEBUGGER(); 542 return NULL; 543 } 544 545 dce_ipp_construct(ipp, ctx, inst, 546 &ipp_regs[inst], &ipp_shift, &ipp_mask); 547 return &ipp->base; 548 } 549 550 static const struct encoder_feature_support link_enc_feature = { 551 .max_hdmi_deep_color = COLOR_DEPTH_121212, 552 .max_hdmi_pixel_clock = 594000, 553 .flags.bits.IS_HBR2_CAPABLE = true, 554 .flags.bits.IS_TPS3_CAPABLE = true, 555 .flags.bits.IS_YCBCR_CAPABLE = true 556 }; 557 558 static struct link_encoder *dce110_link_encoder_create( 559 const struct encoder_init_data *enc_init_data) 560 { 561 struct dce110_link_encoder *enc110 = 562 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 563 564 if (!enc110) 565 return NULL; 566 567 dce110_link_encoder_construct(enc110, 568 enc_init_data, 569 &link_enc_feature, 570 &link_enc_regs[enc_init_data->transmitter], 571 &link_enc_aux_regs[enc_init_data->channel - 1], 572 &link_enc_hpd_regs[enc_init_data->hpd_source]); 573 return &enc110->base; 574 } 575 576 static struct output_pixel_processor *dce110_opp_create( 577 struct dc_context *ctx, 578 uint32_t inst) 579 { 580 struct dce110_opp *opp = 581 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 582 583 if (!opp) 584 return NULL; 585 586 dce110_opp_construct(opp, 587 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 588 return &opp->base; 589 } 590 591 struct clock_source *dce110_clock_source_create( 592 struct dc_context *ctx, 593 struct dc_bios *bios, 594 enum clock_source_id id, 595 const struct dce110_clk_src_regs *regs, 596 bool dp_clk_src) 597 { 598 struct dce110_clk_src *clk_src = 599 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 600 601 if (!clk_src) 602 return NULL; 603 604 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 605 regs, &cs_shift, &cs_mask)) { 606 clk_src->base.dp_clk_src = dp_clk_src; 607 return &clk_src->base; 608 } 609 610 BREAK_TO_DEBUGGER(); 611 return NULL; 612 } 613 614 void dce110_clock_source_destroy(struct clock_source **clk_src) 615 { 616 struct dce110_clk_src *dce110_clk_src; 617 618 if (!clk_src) 619 return; 620 621 dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src); 622 623 kfree(dce110_clk_src->dp_ss_params); 624 kfree(dce110_clk_src->hdmi_ss_params); 625 kfree(dce110_clk_src->dvi_ss_params); 626 627 kfree(dce110_clk_src); 628 *clk_src = NULL; 629 } 630 631 static void destruct(struct dce110_resource_pool *pool) 632 { 633 unsigned int i; 634 635 for (i = 0; i < pool->base.pipe_count; i++) { 636 if (pool->base.opps[i] != NULL) 637 dce110_opp_destroy(&pool->base.opps[i]); 638 639 if (pool->base.transforms[i] != NULL) 640 dce110_transform_destroy(&pool->base.transforms[i]); 641 642 if (pool->base.ipps[i] != NULL) 643 dce_ipp_destroy(&pool->base.ipps[i]); 644 645 if (pool->base.mis[i] != NULL) { 646 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 647 pool->base.mis[i] = NULL; 648 } 649 650 if (pool->base.timing_generators[i] != NULL) { 651 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 652 pool->base.timing_generators[i] = NULL; 653 } 654 } 655 656 for (i = 0; i < pool->base.stream_enc_count; i++) { 657 if (pool->base.stream_enc[i] != NULL) 658 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 659 } 660 661 for (i = 0; i < pool->base.clk_src_count; i++) { 662 if (pool->base.clock_sources[i] != NULL) { 663 dce110_clock_source_destroy(&pool->base.clock_sources[i]); 664 } 665 } 666 667 if (pool->base.dp_clock_source != NULL) 668 dce110_clock_source_destroy(&pool->base.dp_clock_source); 669 670 for (i = 0; i < pool->base.audio_count; i++) { 671 if (pool->base.audios[i] != NULL) { 672 dce_aud_destroy(&pool->base.audios[i]); 673 } 674 } 675 676 if (pool->base.abm != NULL) 677 dce_abm_destroy(&pool->base.abm); 678 679 if (pool->base.dmcu != NULL) 680 dce_dmcu_destroy(&pool->base.dmcu); 681 682 if (pool->base.dccg != NULL) 683 dce_dccg_destroy(&pool->base.dccg); 684 685 if (pool->base.irqs != NULL) { 686 dal_irq_service_destroy(&pool->base.irqs); 687 } 688 } 689 690 691 static void get_pixel_clock_parameters( 692 const struct pipe_ctx *pipe_ctx, 693 struct pixel_clk_params *pixel_clk_params) 694 { 695 const struct dc_stream_state *stream = pipe_ctx->stream; 696 697 /*TODO: is this halved for YCbCr 420? in that case we might want to move 698 * the pixel clock normalization for hdmi up to here instead of doing it 699 * in pll_adjust_pix_clk 700 */ 701 pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz; 702 pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id; 703 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 704 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 705 /* TODO: un-hardcode*/ 706 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 707 LINK_RATE_REF_FREQ_IN_KHZ; 708 pixel_clk_params->flags.ENABLE_SS = 0; 709 pixel_clk_params->color_depth = 710 stream->timing.display_color_depth; 711 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 712 pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding == 713 PIXEL_ENCODING_YCBCR420); 714 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 715 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) { 716 pixel_clk_params->color_depth = COLOR_DEPTH_888; 717 } 718 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 719 pixel_clk_params->requested_pix_clk = pixel_clk_params->requested_pix_clk / 2; 720 } 721 } 722 723 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 724 { 725 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 726 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 727 pipe_ctx->clock_source, 728 &pipe_ctx->stream_res.pix_clk_params, 729 &pipe_ctx->pll_settings); 730 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 731 &pipe_ctx->stream->bit_depth_params); 732 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 733 } 734 735 static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx) 736 { 737 if (pipe_ctx->pipe_idx != underlay_idx) 738 return true; 739 if (!pipe_ctx->plane_state) 740 return false; 741 if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 742 return false; 743 return true; 744 } 745 746 static enum dc_status build_mapped_resource( 747 const struct dc *dc, 748 struct dc_state *context, 749 struct dc_stream_state *stream) 750 { 751 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 752 753 if (!pipe_ctx) 754 return DC_ERROR_UNEXPECTED; 755 756 if (!is_surface_pixel_format_supported(pipe_ctx, 757 dc->res_pool->underlay_pipe_index)) 758 return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; 759 760 dce110_resource_build_pipe_hw_param(pipe_ctx); 761 762 /* TODO: validate audio ASIC caps, encoder */ 763 764 resource_build_info_frame(pipe_ctx); 765 766 return DC_OK; 767 } 768 769 static bool dce110_validate_bandwidth( 770 struct dc *dc, 771 struct dc_state *context) 772 { 773 bool result = false; 774 775 DC_LOG_BANDWIDTH_CALCS( 776 "%s: start", 777 __func__); 778 779 if (bw_calcs( 780 dc->ctx, 781 dc->bw_dceip, 782 dc->bw_vbios, 783 context->res_ctx.pipe_ctx, 784 dc->res_pool->pipe_count, 785 &context->bw.dce)) 786 result = true; 787 788 if (!result) 789 DC_LOG_BANDWIDTH_VALIDATION("%s: %dx%d@%d Bandwidth validation failed!\n", 790 __func__, 791 context->streams[0]->timing.h_addressable, 792 context->streams[0]->timing.v_addressable, 793 context->streams[0]->timing.pix_clk_khz); 794 795 if (memcmp(&dc->current_state->bw.dce, 796 &context->bw.dce, sizeof(context->bw.dce))) { 797 struct log_entry log_entry; 798 dm_logger_open( 799 dc->ctx->logger, 800 &log_entry, 801 LOG_BANDWIDTH_CALCS); 802 dm_logger_append(&log_entry, "%s: finish,\n" 803 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 804 "stutMark_b: %d stutMark_a: %d\n", 805 __func__, 806 context->bw.dce.nbp_state_change_wm_ns[0].b_mark, 807 context->bw.dce.nbp_state_change_wm_ns[0].a_mark, 808 context->bw.dce.urgent_wm_ns[0].b_mark, 809 context->bw.dce.urgent_wm_ns[0].a_mark, 810 context->bw.dce.stutter_exit_wm_ns[0].b_mark, 811 context->bw.dce.stutter_exit_wm_ns[0].a_mark); 812 dm_logger_append(&log_entry, 813 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 814 "stutMark_b: %d stutMark_a: %d\n", 815 context->bw.dce.nbp_state_change_wm_ns[1].b_mark, 816 context->bw.dce.nbp_state_change_wm_ns[1].a_mark, 817 context->bw.dce.urgent_wm_ns[1].b_mark, 818 context->bw.dce.urgent_wm_ns[1].a_mark, 819 context->bw.dce.stutter_exit_wm_ns[1].b_mark, 820 context->bw.dce.stutter_exit_wm_ns[1].a_mark); 821 dm_logger_append(&log_entry, 822 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 823 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n", 824 context->bw.dce.nbp_state_change_wm_ns[2].b_mark, 825 context->bw.dce.nbp_state_change_wm_ns[2].a_mark, 826 context->bw.dce.urgent_wm_ns[2].b_mark, 827 context->bw.dce.urgent_wm_ns[2].a_mark, 828 context->bw.dce.stutter_exit_wm_ns[2].b_mark, 829 context->bw.dce.stutter_exit_wm_ns[2].a_mark, 830 context->bw.dce.stutter_mode_enable); 831 dm_logger_append(&log_entry, 832 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" 833 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n", 834 context->bw.dce.cpuc_state_change_enable, 835 context->bw.dce.cpup_state_change_enable, 836 context->bw.dce.nbp_state_change_enable, 837 context->bw.dce.all_displays_in_sync, 838 context->bw.dce.dispclk_khz, 839 context->bw.dce.sclk_khz, 840 context->bw.dce.sclk_deep_sleep_khz, 841 context->bw.dce.yclk_khz, 842 context->bw.dce.blackout_recovery_time_us); 843 dm_logger_close(&log_entry); 844 } 845 return result; 846 } 847 848 enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state, 849 struct dc_caps *caps) 850 { 851 if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) || 852 ((plane_state->dst_rect.height * 2) < plane_state->src_rect.height)) 853 return DC_FAIL_SURFACE_VALIDATE; 854 855 return DC_OK; 856 } 857 858 static bool dce110_validate_surface_sets( 859 struct dc_state *context) 860 { 861 int i, j; 862 863 for (i = 0; i < context->stream_count; i++) { 864 if (context->stream_status[i].plane_count == 0) 865 continue; 866 867 if (context->stream_status[i].plane_count > 2) 868 return false; 869 870 for (j = 0; j < context->stream_status[i].plane_count; j++) { 871 struct dc_plane_state *plane = 872 context->stream_status[i].plane_states[j]; 873 874 /* underlay validation */ 875 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 876 877 if ((plane->src_rect.width > 1920 || 878 plane->src_rect.height > 1080)) 879 return false; 880 881 /* we don't have the logic to support underlay 882 * only yet so block the use case where we get 883 * NV12 plane as top layer 884 */ 885 if (j == 0) 886 return false; 887 888 /* irrespective of plane format, 889 * stream should be RGB encoded 890 */ 891 if (context->streams[i]->timing.pixel_encoding 892 != PIXEL_ENCODING_RGB) 893 return false; 894 895 } 896 897 } 898 } 899 900 return true; 901 } 902 903 enum dc_status dce110_validate_global( 904 struct dc *dc, 905 struct dc_state *context) 906 { 907 if (!dce110_validate_surface_sets(context)) 908 return DC_FAIL_SURFACE_VALIDATE; 909 910 return DC_OK; 911 } 912 913 static enum dc_status dce110_add_stream_to_ctx( 914 struct dc *dc, 915 struct dc_state *new_ctx, 916 struct dc_stream_state *dc_stream) 917 { 918 enum dc_status result = DC_ERROR_UNEXPECTED; 919 920 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 921 922 if (result == DC_OK) 923 result = resource_map_clock_resources(dc, new_ctx, dc_stream); 924 925 926 if (result == DC_OK) 927 result = build_mapped_resource(dc, new_ctx, dc_stream); 928 929 return result; 930 } 931 932 static struct pipe_ctx *dce110_acquire_underlay( 933 struct dc_state *context, 934 const struct resource_pool *pool, 935 struct dc_stream_state *stream) 936 { 937 struct dc *dc = stream->ctx->dc; 938 struct resource_context *res_ctx = &context->res_ctx; 939 unsigned int underlay_idx = pool->underlay_pipe_index; 940 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; 941 942 if (res_ctx->pipe_ctx[underlay_idx].stream) 943 return NULL; 944 945 pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx]; 946 pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; 947 /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/ 948 pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; 949 pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; 950 pipe_ctx->pipe_idx = underlay_idx; 951 952 pipe_ctx->stream = stream; 953 954 if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) { 955 struct tg_color black_color = {0}; 956 struct dc_bios *dcb = dc->ctx->dc_bios; 957 958 dc->hwss.enable_display_power_gating( 959 dc, 960 pipe_ctx->stream_res.tg->inst, 961 dcb, PIPE_GATING_CONTROL_DISABLE); 962 963 /* 964 * This is for powering on underlay, so crtc does not 965 * need to be enabled 966 */ 967 968 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg, 969 &stream->timing, 970 false); 971 972 pipe_ctx->stream_res.tg->funcs->enable_advanced_request( 973 pipe_ctx->stream_res.tg, 974 true, 975 &stream->timing); 976 977 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi, 978 stream->timing.h_total, 979 stream->timing.v_total, 980 stream->timing.pix_clk_khz, 981 context->stream_count); 982 983 color_space_to_black_color(dc, 984 COLOR_SPACE_YCBCR601, &black_color); 985 pipe_ctx->stream_res.tg->funcs->set_blank_color( 986 pipe_ctx->stream_res.tg, 987 &black_color); 988 } 989 990 return pipe_ctx; 991 } 992 993 static void dce110_destroy_resource_pool(struct resource_pool **pool) 994 { 995 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 996 997 destruct(dce110_pool); 998 kfree(dce110_pool); 999 *pool = NULL; 1000 } 1001 1002 1003 static const struct resource_funcs dce110_res_pool_funcs = { 1004 .destroy = dce110_destroy_resource_pool, 1005 .link_enc_create = dce110_link_encoder_create, 1006 .validate_bandwidth = dce110_validate_bandwidth, 1007 .validate_plane = dce110_validate_plane, 1008 .acquire_idle_pipe_for_layer = dce110_acquire_underlay, 1009 .add_stream_to_ctx = dce110_add_stream_to_ctx, 1010 .validate_global = dce110_validate_global 1011 }; 1012 1013 static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) 1014 { 1015 struct dce110_timing_generator *dce110_tgv = kzalloc(sizeof(*dce110_tgv), 1016 GFP_KERNEL); 1017 struct dce_transform *dce110_xfmv = kzalloc(sizeof(*dce110_xfmv), 1018 GFP_KERNEL); 1019 struct dce_mem_input *dce110_miv = kzalloc(sizeof(*dce110_miv), 1020 GFP_KERNEL); 1021 struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv), 1022 GFP_KERNEL); 1023 1024 if (!dce110_tgv || !dce110_xfmv || !dce110_miv || !dce110_oppv) { 1025 kfree(dce110_tgv); 1026 kfree(dce110_xfmv); 1027 kfree(dce110_miv); 1028 kfree(dce110_oppv); 1029 return false; 1030 } 1031 1032 dce110_opp_v_construct(dce110_oppv, ctx); 1033 1034 dce110_timing_generator_v_construct(dce110_tgv, ctx); 1035 dce110_mem_input_v_construct(dce110_miv, ctx); 1036 dce110_transform_v_construct(dce110_xfmv, ctx); 1037 1038 pool->opps[pool->pipe_count] = &dce110_oppv->base; 1039 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; 1040 pool->mis[pool->pipe_count] = &dce110_miv->base; 1041 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; 1042 pool->pipe_count++; 1043 1044 /* update the public caps to indicate an underlay is available */ 1045 ctx->dc->caps.max_slave_planes = 1; 1046 ctx->dc->caps.max_slave_planes = 1; 1047 1048 return true; 1049 } 1050 1051 static void bw_calcs_data_update_from_pplib(struct dc *dc) 1052 { 1053 struct dm_pp_clock_levels clks = {0}; 1054 1055 /*do system clock*/ 1056 dm_pp_get_clock_levels_by_type( 1057 dc->ctx, 1058 DM_PP_CLOCK_TYPE_ENGINE_CLK, 1059 &clks); 1060 /* convert all the clock fro kHz to fix point mHz */ 1061 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 1062 clks.clocks_in_khz[clks.num_levels-1], 1000); 1063 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 1064 clks.clocks_in_khz[clks.num_levels/8], 1000); 1065 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 1066 clks.clocks_in_khz[clks.num_levels*2/8], 1000); 1067 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 1068 clks.clocks_in_khz[clks.num_levels*3/8], 1000); 1069 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 1070 clks.clocks_in_khz[clks.num_levels*4/8], 1000); 1071 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 1072 clks.clocks_in_khz[clks.num_levels*5/8], 1000); 1073 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1074 clks.clocks_in_khz[clks.num_levels*6/8], 1000); 1075 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1076 clks.clocks_in_khz[0], 1000); 1077 dc->sclk_lvls = clks; 1078 1079 /*do display clock*/ 1080 dm_pp_get_clock_levels_by_type( 1081 dc->ctx, 1082 DM_PP_CLOCK_TYPE_DISPLAY_CLK, 1083 &clks); 1084 dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed( 1085 clks.clocks_in_khz[clks.num_levels-1], 1000); 1086 dc->bw_vbios->mid_voltage_max_dispclk = bw_frc_to_fixed( 1087 clks.clocks_in_khz[clks.num_levels>>1], 1000); 1088 dc->bw_vbios->low_voltage_max_dispclk = bw_frc_to_fixed( 1089 clks.clocks_in_khz[0], 1000); 1090 1091 /*do memory clock*/ 1092 dm_pp_get_clock_levels_by_type( 1093 dc->ctx, 1094 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1095 &clks); 1096 1097 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1098 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000); 1099 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1100 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER, 1101 1000); 1102 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1103 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER, 1104 1000); 1105 } 1106 1107 const struct resource_caps *dce110_resource_cap( 1108 struct hw_asic_id *asic_id) 1109 { 1110 if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev)) 1111 return &stoney_resource_cap; 1112 else 1113 return &carrizo_resource_cap; 1114 } 1115 1116 static bool construct( 1117 uint8_t num_virtual_links, 1118 struct dc *dc, 1119 struct dce110_resource_pool *pool, 1120 struct hw_asic_id asic_id) 1121 { 1122 unsigned int i; 1123 struct dc_context *ctx = dc->ctx; 1124 struct dc_firmware_info info; 1125 struct dc_bios *bp; 1126 struct dm_pp_static_clock_info static_clk_info = {0}; 1127 1128 ctx->dc_bios->regs = &bios_regs; 1129 1130 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); 1131 pool->base.funcs = &dce110_res_pool_funcs; 1132 1133 /************************************************* 1134 * Resource + asic cap harcoding * 1135 *************************************************/ 1136 1137 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1138 pool->base.underlay_pipe_index = pool->base.pipe_count; 1139 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1140 dc->caps.max_downscale_ratio = 150; 1141 dc->caps.i2c_speed_in_khz = 100; 1142 dc->caps.max_cursor_size = 128; 1143 dc->caps.is_apu = true; 1144 1145 /************************************************* 1146 * Create resources * 1147 *************************************************/ 1148 1149 bp = ctx->dc_bios; 1150 1151 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1152 info.external_clock_source_frequency_for_dp != 0) { 1153 pool->base.dp_clock_source = 1154 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1155 1156 pool->base.clock_sources[0] = 1157 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, 1158 &clk_src_regs[0], false); 1159 pool->base.clock_sources[1] = 1160 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, 1161 &clk_src_regs[1], false); 1162 1163 pool->base.clk_src_count = 2; 1164 1165 /* TODO: find out if CZ support 3 PLLs */ 1166 } 1167 1168 if (pool->base.dp_clock_source == NULL) { 1169 dm_error("DC: failed to create dp clock source!\n"); 1170 BREAK_TO_DEBUGGER(); 1171 goto res_create_fail; 1172 } 1173 1174 for (i = 0; i < pool->base.clk_src_count; i++) { 1175 if (pool->base.clock_sources[i] == NULL) { 1176 dm_error("DC: failed to create clock sources!\n"); 1177 BREAK_TO_DEBUGGER(); 1178 goto res_create_fail; 1179 } 1180 } 1181 1182 pool->base.dccg = dce110_dccg_create(ctx, 1183 &disp_clk_regs, 1184 &disp_clk_shift, 1185 &disp_clk_mask); 1186 if (pool->base.dccg == NULL) { 1187 dm_error("DC: failed to create display clock!\n"); 1188 BREAK_TO_DEBUGGER(); 1189 goto res_create_fail; 1190 } 1191 1192 pool->base.dmcu = dce_dmcu_create(ctx, 1193 &dmcu_regs, 1194 &dmcu_shift, 1195 &dmcu_mask); 1196 if (pool->base.dmcu == NULL) { 1197 dm_error("DC: failed to create dmcu!\n"); 1198 BREAK_TO_DEBUGGER(); 1199 goto res_create_fail; 1200 } 1201 1202 pool->base.abm = dce_abm_create(ctx, 1203 &abm_regs, 1204 &abm_shift, 1205 &abm_mask); 1206 if (pool->base.abm == NULL) { 1207 dm_error("DC: failed to create abm!\n"); 1208 BREAK_TO_DEBUGGER(); 1209 goto res_create_fail; 1210 } 1211 1212 /* get static clock information for PPLIB or firmware, save 1213 * max_clock_state 1214 */ 1215 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 1216 pool->base.dccg->max_clks_state = 1217 static_clk_info.max_clocks_state; 1218 1219 { 1220 struct irq_service_init_data init_data; 1221 init_data.ctx = dc->ctx; 1222 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 1223 if (!pool->base.irqs) 1224 goto res_create_fail; 1225 } 1226 1227 for (i = 0; i < pool->base.pipe_count; i++) { 1228 pool->base.timing_generators[i] = dce110_timing_generator_create( 1229 ctx, i, &dce110_tg_offsets[i]); 1230 if (pool->base.timing_generators[i] == NULL) { 1231 BREAK_TO_DEBUGGER(); 1232 dm_error("DC: failed to create tg!\n"); 1233 goto res_create_fail; 1234 } 1235 1236 pool->base.mis[i] = dce110_mem_input_create(ctx, i); 1237 if (pool->base.mis[i] == NULL) { 1238 BREAK_TO_DEBUGGER(); 1239 dm_error( 1240 "DC: failed to create memory input!\n"); 1241 goto res_create_fail; 1242 } 1243 1244 pool->base.ipps[i] = dce110_ipp_create(ctx, i); 1245 if (pool->base.ipps[i] == NULL) { 1246 BREAK_TO_DEBUGGER(); 1247 dm_error( 1248 "DC: failed to create input pixel processor!\n"); 1249 goto res_create_fail; 1250 } 1251 1252 pool->base.transforms[i] = dce110_transform_create(ctx, i); 1253 if (pool->base.transforms[i] == NULL) { 1254 BREAK_TO_DEBUGGER(); 1255 dm_error( 1256 "DC: failed to create transform!\n"); 1257 goto res_create_fail; 1258 } 1259 1260 pool->base.opps[i] = dce110_opp_create(ctx, i); 1261 if (pool->base.opps[i] == NULL) { 1262 BREAK_TO_DEBUGGER(); 1263 dm_error( 1264 "DC: failed to create output pixel processor!\n"); 1265 goto res_create_fail; 1266 } 1267 } 1268 1269 dc->fbc_compressor = dce110_compressor_create(ctx); 1270 1271 if (!underlay_create(ctx, &pool->base)) 1272 goto res_create_fail; 1273 1274 if (!resource_construct(num_virtual_links, dc, &pool->base, 1275 &res_create_funcs)) 1276 goto res_create_fail; 1277 1278 /* Create hardware sequencer */ 1279 dce110_hw_sequencer_construct(dc); 1280 1281 dc->caps.max_planes = pool->base.pipe_count; 1282 1283 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1284 1285 bw_calcs_data_update_from_pplib(dc); 1286 1287 return true; 1288 1289 res_create_fail: 1290 destruct(pool); 1291 return false; 1292 } 1293 1294 struct resource_pool *dce110_create_resource_pool( 1295 uint8_t num_virtual_links, 1296 struct dc *dc, 1297 struct hw_asic_id asic_id) 1298 { 1299 struct dce110_resource_pool *pool = 1300 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1301 1302 if (!pool) 1303 return NULL; 1304 1305 if (construct(num_virtual_links, dc, pool, asic_id)) 1306 return &pool->base; 1307 1308 BREAK_TO_DEBUGGER(); 1309 return NULL; 1310 } 1311