1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "link_encoder.h" 29 #include "stream_encoder.h" 30 31 #include "resource.h" 32 #include "dce110/dce110_resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dce/dce_audio.h" 35 #include "dce110/dce110_timing_generator.h" 36 #include "irq/dce110/irq_service_dce110.h" 37 #include "dce110/dce110_timing_generator_v.h" 38 #include "dce/dce_link_encoder.h" 39 #include "dce/dce_stream_encoder.h" 40 #include "dce/dce_mem_input.h" 41 #include "dce110/dce110_mem_input_v.h" 42 #include "dce/dce_ipp.h" 43 #include "dce/dce_transform.h" 44 #include "dce110/dce110_transform_v.h" 45 #include "dce/dce_opp.h" 46 #include "dce110/dce110_opp_v.h" 47 #include "dce/dce_clock_source.h" 48 #include "dce/dce_hwseq.h" 49 #include "dce110/dce110_hw_sequencer.h" 50 #include "dce/dce_aux.h" 51 #include "dce/dce_abm.h" 52 #include "dce/dce_dmcu.h" 53 #include "dce/dce_i2c.h" 54 55 #define DC_LOGGER \ 56 dc->ctx->logger 57 58 #include "dce110/dce110_compressor.h" 59 60 #include "reg_helper.h" 61 62 #include "dce/dce_11_0_d.h" 63 #include "dce/dce_11_0_sh_mask.h" 64 65 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 66 #include "gmc/gmc_8_2_d.h" 67 #include "gmc/gmc_8_2_sh_mask.h" 68 #endif 69 70 #ifndef mmDP_DPHY_INTERNAL_CTRL 71 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 72 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 73 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 74 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 75 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 76 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 77 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 78 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 79 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 80 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 81 #endif 82 83 #ifndef mmBIOS_SCRATCH_2 84 #define mmBIOS_SCRATCH_2 0x05CB 85 #define mmBIOS_SCRATCH_3 0x05CC 86 #define mmBIOS_SCRATCH_6 0x05CF 87 #endif 88 89 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 90 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 91 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 92 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 93 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 94 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 95 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 96 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 97 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 98 #endif 99 100 #ifndef mmDP_DPHY_FAST_TRAINING 101 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 102 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 103 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 104 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 105 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 106 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 107 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 108 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 109 #endif 110 111 #ifndef DPHY_RX_FAST_TRAINING_CAPABLE 112 #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1 113 #endif 114 115 static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = { 116 { 117 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 118 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 119 }, 120 { 121 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 122 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 123 }, 124 { 125 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 126 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 127 }, 128 { 129 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 130 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 131 }, 132 { 133 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 134 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 135 }, 136 { 137 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 138 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 139 } 140 }; 141 142 /* set register offset */ 143 #define SR(reg_name)\ 144 .reg_name = mm ## reg_name 145 146 /* set register offset with instance */ 147 #define SRI(reg_name, block, id)\ 148 .reg_name = mm ## block ## id ## _ ## reg_name 149 150 static const struct dce_dmcu_registers dmcu_regs = { 151 DMCU_DCE110_COMMON_REG_LIST() 152 }; 153 154 static const struct dce_dmcu_shift dmcu_shift = { 155 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 156 }; 157 158 static const struct dce_dmcu_mask dmcu_mask = { 159 DMCU_MASK_SH_LIST_DCE110(_MASK) 160 }; 161 162 static const struct dce_abm_registers abm_regs = { 163 ABM_DCE110_COMMON_REG_LIST() 164 }; 165 166 static const struct dce_abm_shift abm_shift = { 167 ABM_MASK_SH_LIST_DCE110(__SHIFT) 168 }; 169 170 static const struct dce_abm_mask abm_mask = { 171 ABM_MASK_SH_LIST_DCE110(_MASK) 172 }; 173 174 #define ipp_regs(id)\ 175 [id] = {\ 176 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 177 } 178 179 static const struct dce_ipp_registers ipp_regs[] = { 180 ipp_regs(0), 181 ipp_regs(1), 182 ipp_regs(2) 183 }; 184 185 static const struct dce_ipp_shift ipp_shift = { 186 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 187 }; 188 189 static const struct dce_ipp_mask ipp_mask = { 190 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 191 }; 192 193 #define transform_regs(id)\ 194 [id] = {\ 195 XFM_COMMON_REG_LIST_DCE110(id)\ 196 } 197 198 static const struct dce_transform_registers xfm_regs[] = { 199 transform_regs(0), 200 transform_regs(1), 201 transform_regs(2) 202 }; 203 204 static const struct dce_transform_shift xfm_shift = { 205 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 206 }; 207 208 static const struct dce_transform_mask xfm_mask = { 209 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 210 }; 211 212 #define aux_regs(id)\ 213 [id] = {\ 214 AUX_REG_LIST(id)\ 215 } 216 217 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 218 aux_regs(0), 219 aux_regs(1), 220 aux_regs(2), 221 aux_regs(3), 222 aux_regs(4), 223 aux_regs(5) 224 }; 225 226 #define hpd_regs(id)\ 227 [id] = {\ 228 HPD_REG_LIST(id)\ 229 } 230 231 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 232 hpd_regs(0), 233 hpd_regs(1), 234 hpd_regs(2), 235 hpd_regs(3), 236 hpd_regs(4), 237 hpd_regs(5) 238 }; 239 240 241 #define link_regs(id)\ 242 [id] = {\ 243 LE_DCE110_REG_LIST(id)\ 244 } 245 246 static const struct dce110_link_enc_registers link_enc_regs[] = { 247 link_regs(0), 248 link_regs(1), 249 link_regs(2), 250 link_regs(3), 251 link_regs(4), 252 link_regs(5), 253 link_regs(6), 254 }; 255 256 #define stream_enc_regs(id)\ 257 [id] = {\ 258 SE_COMMON_REG_LIST(id),\ 259 .TMDS_CNTL = 0,\ 260 } 261 262 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 263 stream_enc_regs(0), 264 stream_enc_regs(1), 265 stream_enc_regs(2) 266 }; 267 268 static const struct dce_stream_encoder_shift se_shift = { 269 SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 270 }; 271 272 static const struct dce_stream_encoder_mask se_mask = { 273 SE_COMMON_MASK_SH_LIST_DCE110(_MASK) 274 }; 275 276 #define opp_regs(id)\ 277 [id] = {\ 278 OPP_DCE_110_REG_LIST(id),\ 279 } 280 281 static const struct dce_opp_registers opp_regs[] = { 282 opp_regs(0), 283 opp_regs(1), 284 opp_regs(2), 285 opp_regs(3), 286 opp_regs(4), 287 opp_regs(5) 288 }; 289 290 static const struct dce_opp_shift opp_shift = { 291 OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT) 292 }; 293 294 static const struct dce_opp_mask opp_mask = { 295 OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK) 296 }; 297 298 #define aux_engine_regs(id)\ 299 [id] = {\ 300 AUX_COMMON_REG_LIST(id), \ 301 .AUX_RESET_MASK = 0 \ 302 } 303 304 static const struct dce110_aux_registers aux_engine_regs[] = { 305 aux_engine_regs(0), 306 aux_engine_regs(1), 307 aux_engine_regs(2), 308 aux_engine_regs(3), 309 aux_engine_regs(4), 310 aux_engine_regs(5) 311 }; 312 313 #define audio_regs(id)\ 314 [id] = {\ 315 AUD_COMMON_REG_LIST(id)\ 316 } 317 318 static const struct dce_audio_registers audio_regs[] = { 319 audio_regs(0), 320 audio_regs(1), 321 audio_regs(2), 322 audio_regs(3), 323 audio_regs(4), 324 audio_regs(5), 325 audio_regs(6), 326 }; 327 328 static const struct dce_audio_shift audio_shift = { 329 AUD_COMMON_MASK_SH_LIST(__SHIFT) 330 }; 331 332 static const struct dce_aduio_mask audio_mask = { 333 AUD_COMMON_MASK_SH_LIST(_MASK) 334 }; 335 336 /* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */ 337 338 339 #define clk_src_regs(id)\ 340 [id] = {\ 341 CS_COMMON_REG_LIST_DCE_100_110(id),\ 342 } 343 344 static const struct dce110_clk_src_regs clk_src_regs[] = { 345 clk_src_regs(0), 346 clk_src_regs(1), 347 clk_src_regs(2) 348 }; 349 350 static const struct dce110_clk_src_shift cs_shift = { 351 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 352 }; 353 354 static const struct dce110_clk_src_mask cs_mask = { 355 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 356 }; 357 358 static const struct bios_registers bios_regs = { 359 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 360 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 361 }; 362 363 static const struct resource_caps carrizo_resource_cap = { 364 .num_timing_generator = 3, 365 .num_video_plane = 1, 366 .num_audio = 3, 367 .num_stream_encoder = 3, 368 .num_pll = 2, 369 .num_ddc = 3, 370 }; 371 372 static const struct resource_caps stoney_resource_cap = { 373 .num_timing_generator = 2, 374 .num_video_plane = 1, 375 .num_audio = 3, 376 .num_stream_encoder = 3, 377 .num_pll = 2, 378 .num_ddc = 3, 379 }; 380 381 static const struct dc_plane_cap plane_cap = { 382 .type = DC_PLANE_TYPE_DCE_RGB, 383 .blends_with_below = true, 384 .blends_with_above = true, 385 .per_pixel_alpha = 1, 386 387 .pixel_format_support = { 388 .argb8888 = true, 389 .nv12 = false, 390 .fp16 = false 391 }, 392 393 .max_upscale_factor = { 394 .argb8888 = 16000, 395 .nv12 = 1, 396 .fp16 = 1 397 }, 398 399 .max_downscale_factor = { 400 .argb8888 = 250, 401 .nv12 = 1, 402 .fp16 = 1 403 } 404 }; 405 406 static const struct dc_plane_cap underlay_plane_cap = { 407 .type = DC_PLANE_TYPE_DCE_UNDERLAY, 408 .blends_with_above = true, 409 .per_pixel_alpha = 1, 410 411 .pixel_format_support = { 412 .argb8888 = false, 413 .nv12 = true, 414 .fp16 = false 415 }, 416 417 .max_upscale_factor = { 418 .argb8888 = 1, 419 .nv12 = 16000, 420 .fp16 = 1 421 }, 422 423 .max_downscale_factor = { 424 .argb8888 = 1, 425 .nv12 = 250, 426 .fp16 = 1 427 } 428 }; 429 430 #define CTX ctx 431 #define REG(reg) mm ## reg 432 433 #ifndef mmCC_DC_HDMI_STRAPS 434 #define mmCC_DC_HDMI_STRAPS 0x4819 435 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 436 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 437 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 438 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 439 #endif 440 441 static void read_dce_straps( 442 struct dc_context *ctx, 443 struct resource_straps *straps) 444 { 445 REG_GET_2(CC_DC_HDMI_STRAPS, 446 HDMI_DISABLE, &straps->hdmi_disable, 447 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 448 449 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 450 } 451 452 static struct audio *create_audio( 453 struct dc_context *ctx, unsigned int inst) 454 { 455 return dce_audio_create(ctx, inst, 456 &audio_regs[inst], &audio_shift, &audio_mask); 457 } 458 459 static struct timing_generator *dce110_timing_generator_create( 460 struct dc_context *ctx, 461 uint32_t instance, 462 const struct dce110_timing_generator_offsets *offsets) 463 { 464 struct dce110_timing_generator *tg110 = 465 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 466 467 if (!tg110) 468 return NULL; 469 470 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 471 return &tg110->base; 472 } 473 474 static struct stream_encoder *dce110_stream_encoder_create( 475 enum engine_id eng_id, 476 struct dc_context *ctx) 477 { 478 struct dce110_stream_encoder *enc110 = 479 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 480 481 if (!enc110) 482 return NULL; 483 484 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 485 &stream_enc_regs[eng_id], 486 &se_shift, &se_mask); 487 return &enc110->base; 488 } 489 490 #define SRII(reg_name, block, id)\ 491 .reg_name[id] = mm ## block ## id ## _ ## reg_name 492 493 static const struct dce_hwseq_registers hwseq_stoney_reg = { 494 HWSEQ_ST_REG_LIST() 495 }; 496 497 static const struct dce_hwseq_registers hwseq_cz_reg = { 498 HWSEQ_CZ_REG_LIST() 499 }; 500 501 static const struct dce_hwseq_shift hwseq_shift = { 502 HWSEQ_DCE11_MASK_SH_LIST(__SHIFT), 503 }; 504 505 static const struct dce_hwseq_mask hwseq_mask = { 506 HWSEQ_DCE11_MASK_SH_LIST(_MASK), 507 }; 508 509 static struct dce_hwseq *dce110_hwseq_create( 510 struct dc_context *ctx) 511 { 512 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 513 514 if (hws) { 515 hws->ctx = ctx; 516 hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ? 517 &hwseq_stoney_reg : &hwseq_cz_reg; 518 hws->shifts = &hwseq_shift; 519 hws->masks = &hwseq_mask; 520 hws->wa.blnd_crtc_trigger = true; 521 } 522 return hws; 523 } 524 525 static const struct resource_create_funcs res_create_funcs = { 526 .read_dce_straps = read_dce_straps, 527 .create_audio = create_audio, 528 .create_stream_encoder = dce110_stream_encoder_create, 529 .create_hwseq = dce110_hwseq_create, 530 }; 531 532 #define mi_inst_regs(id) { \ 533 MI_DCE11_REG_LIST(id), \ 534 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 535 } 536 static const struct dce_mem_input_registers mi_regs[] = { 537 mi_inst_regs(0), 538 mi_inst_regs(1), 539 mi_inst_regs(2), 540 }; 541 542 static const struct dce_mem_input_shift mi_shifts = { 543 MI_DCE11_MASK_SH_LIST(__SHIFT), 544 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 545 }; 546 547 static const struct dce_mem_input_mask mi_masks = { 548 MI_DCE11_MASK_SH_LIST(_MASK), 549 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 550 }; 551 552 553 static struct mem_input *dce110_mem_input_create( 554 struct dc_context *ctx, 555 uint32_t inst) 556 { 557 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 558 GFP_KERNEL); 559 560 if (!dce_mi) { 561 BREAK_TO_DEBUGGER(); 562 return NULL; 563 } 564 565 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 566 dce_mi->wa.single_head_rdreq_dmif_limit = 3; 567 return &dce_mi->base; 568 } 569 570 static void dce110_transform_destroy(struct transform **xfm) 571 { 572 kfree(TO_DCE_TRANSFORM(*xfm)); 573 *xfm = NULL; 574 } 575 576 static struct transform *dce110_transform_create( 577 struct dc_context *ctx, 578 uint32_t inst) 579 { 580 struct dce_transform *transform = 581 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 582 583 if (!transform) 584 return NULL; 585 586 dce_transform_construct(transform, ctx, inst, 587 &xfm_regs[inst], &xfm_shift, &xfm_mask); 588 return &transform->base; 589 } 590 591 static struct input_pixel_processor *dce110_ipp_create( 592 struct dc_context *ctx, uint32_t inst) 593 { 594 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 595 596 if (!ipp) { 597 BREAK_TO_DEBUGGER(); 598 return NULL; 599 } 600 601 dce_ipp_construct(ipp, ctx, inst, 602 &ipp_regs[inst], &ipp_shift, &ipp_mask); 603 return &ipp->base; 604 } 605 606 static const struct encoder_feature_support link_enc_feature = { 607 .max_hdmi_deep_color = COLOR_DEPTH_121212, 608 .max_hdmi_pixel_clock = 300000, 609 .flags.bits.IS_HBR2_CAPABLE = true, 610 .flags.bits.IS_TPS3_CAPABLE = true 611 }; 612 613 static struct link_encoder *dce110_link_encoder_create( 614 const struct encoder_init_data *enc_init_data) 615 { 616 struct dce110_link_encoder *enc110 = 617 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 618 619 if (!enc110) 620 return NULL; 621 622 dce110_link_encoder_construct(enc110, 623 enc_init_data, 624 &link_enc_feature, 625 &link_enc_regs[enc_init_data->transmitter], 626 &link_enc_aux_regs[enc_init_data->channel - 1], 627 &link_enc_hpd_regs[enc_init_data->hpd_source]); 628 return &enc110->base; 629 } 630 631 static struct output_pixel_processor *dce110_opp_create( 632 struct dc_context *ctx, 633 uint32_t inst) 634 { 635 struct dce110_opp *opp = 636 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 637 638 if (!opp) 639 return NULL; 640 641 dce110_opp_construct(opp, 642 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 643 return &opp->base; 644 } 645 646 struct dce_aux *dce110_aux_engine_create( 647 struct dc_context *ctx, 648 uint32_t inst) 649 { 650 struct aux_engine_dce110 *aux_engine = 651 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 652 653 if (!aux_engine) 654 return NULL; 655 656 dce110_aux_engine_construct(aux_engine, ctx, inst, 657 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 658 &aux_engine_regs[inst]); 659 660 return &aux_engine->base; 661 } 662 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 663 664 static const struct dce_i2c_registers i2c_hw_regs[] = { 665 i2c_inst_regs(1), 666 i2c_inst_regs(2), 667 i2c_inst_regs(3), 668 i2c_inst_regs(4), 669 i2c_inst_regs(5), 670 i2c_inst_regs(6), 671 }; 672 673 static const struct dce_i2c_shift i2c_shifts = { 674 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 675 }; 676 677 static const struct dce_i2c_mask i2c_masks = { 678 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 679 }; 680 681 struct dce_i2c_hw *dce110_i2c_hw_create( 682 struct dc_context *ctx, 683 uint32_t inst) 684 { 685 struct dce_i2c_hw *dce_i2c_hw = 686 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 687 688 if (!dce_i2c_hw) 689 return NULL; 690 691 dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst, 692 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 693 694 return dce_i2c_hw; 695 } 696 struct clock_source *dce110_clock_source_create( 697 struct dc_context *ctx, 698 struct dc_bios *bios, 699 enum clock_source_id id, 700 const struct dce110_clk_src_regs *regs, 701 bool dp_clk_src) 702 { 703 struct dce110_clk_src *clk_src = 704 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 705 706 if (!clk_src) 707 return NULL; 708 709 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 710 regs, &cs_shift, &cs_mask)) { 711 clk_src->base.dp_clk_src = dp_clk_src; 712 return &clk_src->base; 713 } 714 715 BREAK_TO_DEBUGGER(); 716 return NULL; 717 } 718 719 void dce110_clock_source_destroy(struct clock_source **clk_src) 720 { 721 struct dce110_clk_src *dce110_clk_src; 722 723 if (!clk_src) 724 return; 725 726 dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src); 727 728 kfree(dce110_clk_src->dp_ss_params); 729 kfree(dce110_clk_src->hdmi_ss_params); 730 kfree(dce110_clk_src->dvi_ss_params); 731 732 kfree(dce110_clk_src); 733 *clk_src = NULL; 734 } 735 736 static void destruct(struct dce110_resource_pool *pool) 737 { 738 unsigned int i; 739 740 for (i = 0; i < pool->base.pipe_count; i++) { 741 if (pool->base.opps[i] != NULL) 742 dce110_opp_destroy(&pool->base.opps[i]); 743 744 if (pool->base.transforms[i] != NULL) 745 dce110_transform_destroy(&pool->base.transforms[i]); 746 747 if (pool->base.ipps[i] != NULL) 748 dce_ipp_destroy(&pool->base.ipps[i]); 749 750 if (pool->base.mis[i] != NULL) { 751 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 752 pool->base.mis[i] = NULL; 753 } 754 755 if (pool->base.timing_generators[i] != NULL) { 756 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 757 pool->base.timing_generators[i] = NULL; 758 } 759 } 760 761 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 762 if (pool->base.engines[i] != NULL) 763 dce110_engine_destroy(&pool->base.engines[i]); 764 if (pool->base.hw_i2cs[i] != NULL) { 765 kfree(pool->base.hw_i2cs[i]); 766 pool->base.hw_i2cs[i] = NULL; 767 } 768 if (pool->base.sw_i2cs[i] != NULL) { 769 kfree(pool->base.sw_i2cs[i]); 770 pool->base.sw_i2cs[i] = NULL; 771 } 772 } 773 774 for (i = 0; i < pool->base.stream_enc_count; i++) { 775 if (pool->base.stream_enc[i] != NULL) 776 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 777 } 778 779 for (i = 0; i < pool->base.clk_src_count; i++) { 780 if (pool->base.clock_sources[i] != NULL) { 781 dce110_clock_source_destroy(&pool->base.clock_sources[i]); 782 } 783 } 784 785 if (pool->base.dp_clock_source != NULL) 786 dce110_clock_source_destroy(&pool->base.dp_clock_source); 787 788 for (i = 0; i < pool->base.audio_count; i++) { 789 if (pool->base.audios[i] != NULL) { 790 dce_aud_destroy(&pool->base.audios[i]); 791 } 792 } 793 794 if (pool->base.abm != NULL) 795 dce_abm_destroy(&pool->base.abm); 796 797 if (pool->base.dmcu != NULL) 798 dce_dmcu_destroy(&pool->base.dmcu); 799 800 if (pool->base.irqs != NULL) { 801 dal_irq_service_destroy(&pool->base.irqs); 802 } 803 } 804 805 806 static void get_pixel_clock_parameters( 807 const struct pipe_ctx *pipe_ctx, 808 struct pixel_clk_params *pixel_clk_params) 809 { 810 const struct dc_stream_state *stream = pipe_ctx->stream; 811 812 /*TODO: is this halved for YCbCr 420? in that case we might want to move 813 * the pixel clock normalization for hdmi up to here instead of doing it 814 * in pll_adjust_pix_clk 815 */ 816 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 817 pixel_clk_params->encoder_object_id = stream->link->link_enc->id; 818 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 819 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 820 /* TODO: un-hardcode*/ 821 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 822 LINK_RATE_REF_FREQ_IN_KHZ; 823 pixel_clk_params->flags.ENABLE_SS = 0; 824 pixel_clk_params->color_depth = 825 stream->timing.display_color_depth; 826 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 827 pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding == 828 PIXEL_ENCODING_YCBCR420); 829 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 830 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) { 831 pixel_clk_params->color_depth = COLOR_DEPTH_888; 832 } 833 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 834 pixel_clk_params->requested_pix_clk_100hz = pixel_clk_params->requested_pix_clk_100hz / 2; 835 } 836 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 837 pixel_clk_params->requested_pix_clk_100hz *= 2; 838 839 } 840 841 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 842 { 843 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 844 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 845 pipe_ctx->clock_source, 846 &pipe_ctx->stream_res.pix_clk_params, 847 &pipe_ctx->pll_settings); 848 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 849 &pipe_ctx->stream->bit_depth_params); 850 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 851 } 852 853 static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx) 854 { 855 if (pipe_ctx->pipe_idx != underlay_idx) 856 return true; 857 if (!pipe_ctx->plane_state) 858 return false; 859 if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 860 return false; 861 return true; 862 } 863 864 static enum dc_status build_mapped_resource( 865 const struct dc *dc, 866 struct dc_state *context, 867 struct dc_stream_state *stream) 868 { 869 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 870 871 if (!pipe_ctx) 872 return DC_ERROR_UNEXPECTED; 873 874 if (!is_surface_pixel_format_supported(pipe_ctx, 875 dc->res_pool->underlay_pipe_index)) 876 return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; 877 878 dce110_resource_build_pipe_hw_param(pipe_ctx); 879 880 /* TODO: validate audio ASIC caps, encoder */ 881 882 resource_build_info_frame(pipe_ctx); 883 884 return DC_OK; 885 } 886 887 static bool dce110_validate_bandwidth( 888 struct dc *dc, 889 struct dc_state *context, 890 bool fast_validate) 891 { 892 bool result = false; 893 894 DC_LOG_BANDWIDTH_CALCS( 895 "%s: start", 896 __func__); 897 898 if (bw_calcs( 899 dc->ctx, 900 dc->bw_dceip, 901 dc->bw_vbios, 902 context->res_ctx.pipe_ctx, 903 dc->res_pool->pipe_count, 904 &context->bw_ctx.bw.dce)) 905 result = true; 906 907 if (!result) 908 DC_LOG_BANDWIDTH_VALIDATION("%s: %dx%d@%d Bandwidth validation failed!\n", 909 __func__, 910 context->streams[0]->timing.h_addressable, 911 context->streams[0]->timing.v_addressable, 912 context->streams[0]->timing.pix_clk_100hz / 10); 913 914 if (memcmp(&dc->current_state->bw_ctx.bw.dce, 915 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { 916 917 DC_LOG_BANDWIDTH_CALCS( 918 "%s: finish,\n" 919 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 920 "stutMark_b: %d stutMark_a: %d\n" 921 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 922 "stutMark_b: %d stutMark_a: %d\n" 923 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 924 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n" 925 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" 926 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n" 927 , 928 __func__, 929 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark, 930 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark, 931 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, 932 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, 933 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark, 934 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark, 935 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark, 936 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark, 937 context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark, 938 context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark, 939 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark, 940 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark, 941 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark, 942 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark, 943 context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark, 944 context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark, 945 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark, 946 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark, 947 context->bw_ctx.bw.dce.stutter_mode_enable, 948 context->bw_ctx.bw.dce.cpuc_state_change_enable, 949 context->bw_ctx.bw.dce.cpup_state_change_enable, 950 context->bw_ctx.bw.dce.nbp_state_change_enable, 951 context->bw_ctx.bw.dce.all_displays_in_sync, 952 context->bw_ctx.bw.dce.dispclk_khz, 953 context->bw_ctx.bw.dce.sclk_khz, 954 context->bw_ctx.bw.dce.sclk_deep_sleep_khz, 955 context->bw_ctx.bw.dce.yclk_khz, 956 context->bw_ctx.bw.dce.blackout_recovery_time_us); 957 } 958 return result; 959 } 960 961 enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state, 962 struct dc_caps *caps) 963 { 964 if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) || 965 ((plane_state->dst_rect.height * 2) < plane_state->src_rect.height)) 966 return DC_FAIL_SURFACE_VALIDATE; 967 968 return DC_OK; 969 } 970 971 static bool dce110_validate_surface_sets( 972 struct dc_state *context) 973 { 974 int i, j; 975 976 for (i = 0; i < context->stream_count; i++) { 977 if (context->stream_status[i].plane_count == 0) 978 continue; 979 980 if (context->stream_status[i].plane_count > 2) 981 return false; 982 983 for (j = 0; j < context->stream_status[i].plane_count; j++) { 984 struct dc_plane_state *plane = 985 context->stream_status[i].plane_states[j]; 986 987 /* underlay validation */ 988 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 989 990 if ((plane->src_rect.width > 1920 || 991 plane->src_rect.height > 1080)) 992 return false; 993 994 /* we don't have the logic to support underlay 995 * only yet so block the use case where we get 996 * NV12 plane as top layer 997 */ 998 if (j == 0) 999 return false; 1000 1001 /* irrespective of plane format, 1002 * stream should be RGB encoded 1003 */ 1004 if (context->streams[i]->timing.pixel_encoding 1005 != PIXEL_ENCODING_RGB) 1006 return false; 1007 1008 } 1009 1010 } 1011 } 1012 1013 return true; 1014 } 1015 1016 enum dc_status dce110_validate_global( 1017 struct dc *dc, 1018 struct dc_state *context) 1019 { 1020 if (!dce110_validate_surface_sets(context)) 1021 return DC_FAIL_SURFACE_VALIDATE; 1022 1023 return DC_OK; 1024 } 1025 1026 static enum dc_status dce110_add_stream_to_ctx( 1027 struct dc *dc, 1028 struct dc_state *new_ctx, 1029 struct dc_stream_state *dc_stream) 1030 { 1031 enum dc_status result = DC_ERROR_UNEXPECTED; 1032 1033 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1034 1035 if (result == DC_OK) 1036 result = resource_map_clock_resources(dc, new_ctx, dc_stream); 1037 1038 1039 if (result == DC_OK) 1040 result = build_mapped_resource(dc, new_ctx, dc_stream); 1041 1042 return result; 1043 } 1044 1045 static struct pipe_ctx *dce110_acquire_underlay( 1046 struct dc_state *context, 1047 const struct resource_pool *pool, 1048 struct dc_stream_state *stream) 1049 { 1050 struct dc *dc = stream->ctx->dc; 1051 struct resource_context *res_ctx = &context->res_ctx; 1052 unsigned int underlay_idx = pool->underlay_pipe_index; 1053 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; 1054 1055 if (res_ctx->pipe_ctx[underlay_idx].stream) 1056 return NULL; 1057 1058 pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx]; 1059 pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; 1060 /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/ 1061 pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; 1062 pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; 1063 pipe_ctx->pipe_idx = underlay_idx; 1064 1065 pipe_ctx->stream = stream; 1066 1067 if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) { 1068 struct tg_color black_color = {0}; 1069 struct dc_bios *dcb = dc->ctx->dc_bios; 1070 1071 dc->hwss.enable_display_power_gating( 1072 dc, 1073 pipe_ctx->stream_res.tg->inst, 1074 dcb, PIPE_GATING_CONTROL_DISABLE); 1075 1076 /* 1077 * This is for powering on underlay, so crtc does not 1078 * need to be enabled 1079 */ 1080 1081 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg, 1082 &stream->timing, 1083 0, 1084 0, 1085 0, 1086 0, 1087 pipe_ctx->stream->signal, 1088 false); 1089 1090 pipe_ctx->stream_res.tg->funcs->enable_advanced_request( 1091 pipe_ctx->stream_res.tg, 1092 true, 1093 &stream->timing); 1094 1095 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi, 1096 stream->timing.h_total, 1097 stream->timing.v_total, 1098 stream->timing.pix_clk_100hz / 10, 1099 context->stream_count); 1100 1101 color_space_to_black_color(dc, 1102 COLOR_SPACE_YCBCR601, &black_color); 1103 pipe_ctx->stream_res.tg->funcs->set_blank_color( 1104 pipe_ctx->stream_res.tg, 1105 &black_color); 1106 } 1107 1108 return pipe_ctx; 1109 } 1110 1111 static void dce110_destroy_resource_pool(struct resource_pool **pool) 1112 { 1113 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 1114 1115 destruct(dce110_pool); 1116 kfree(dce110_pool); 1117 *pool = NULL; 1118 } 1119 1120 struct stream_encoder *dce110_find_first_free_match_stream_enc_for_link( 1121 struct resource_context *res_ctx, 1122 const struct resource_pool *pool, 1123 struct dc_stream_state *stream) 1124 { 1125 int i; 1126 int j = -1; 1127 struct dc_link *link = stream->link; 1128 1129 for (i = 0; i < pool->stream_enc_count; i++) { 1130 if (!res_ctx->is_stream_enc_acquired[i] && 1131 pool->stream_enc[i]) { 1132 /* Store first available for MST second display 1133 * in daisy chain use case 1134 */ 1135 j = i; 1136 if (pool->stream_enc[i]->id == 1137 link->link_enc->preferred_engine) 1138 return pool->stream_enc[i]; 1139 } 1140 } 1141 1142 /* 1143 * For CZ and later, we can allow DIG FE and BE to differ for all display types 1144 */ 1145 1146 if (j >= 0) 1147 return pool->stream_enc[j]; 1148 1149 return NULL; 1150 } 1151 1152 1153 static const struct resource_funcs dce110_res_pool_funcs = { 1154 .destroy = dce110_destroy_resource_pool, 1155 .link_enc_create = dce110_link_encoder_create, 1156 .validate_bandwidth = dce110_validate_bandwidth, 1157 .validate_plane = dce110_validate_plane, 1158 .acquire_idle_pipe_for_layer = dce110_acquire_underlay, 1159 .add_stream_to_ctx = dce110_add_stream_to_ctx, 1160 .validate_global = dce110_validate_global, 1161 .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link 1162 }; 1163 1164 static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) 1165 { 1166 struct dce110_timing_generator *dce110_tgv = kzalloc(sizeof(*dce110_tgv), 1167 GFP_KERNEL); 1168 struct dce_transform *dce110_xfmv = kzalloc(sizeof(*dce110_xfmv), 1169 GFP_KERNEL); 1170 struct dce_mem_input *dce110_miv = kzalloc(sizeof(*dce110_miv), 1171 GFP_KERNEL); 1172 struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv), 1173 GFP_KERNEL); 1174 1175 if (!dce110_tgv || !dce110_xfmv || !dce110_miv || !dce110_oppv) { 1176 kfree(dce110_tgv); 1177 kfree(dce110_xfmv); 1178 kfree(dce110_miv); 1179 kfree(dce110_oppv); 1180 return false; 1181 } 1182 1183 dce110_opp_v_construct(dce110_oppv, ctx); 1184 1185 dce110_timing_generator_v_construct(dce110_tgv, ctx); 1186 dce110_mem_input_v_construct(dce110_miv, ctx); 1187 dce110_transform_v_construct(dce110_xfmv, ctx); 1188 1189 pool->opps[pool->pipe_count] = &dce110_oppv->base; 1190 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; 1191 pool->mis[pool->pipe_count] = &dce110_miv->base; 1192 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; 1193 pool->pipe_count++; 1194 1195 /* update the public caps to indicate an underlay is available */ 1196 ctx->dc->caps.max_slave_planes = 1; 1197 ctx->dc->caps.max_slave_planes = 1; 1198 1199 return true; 1200 } 1201 1202 static void bw_calcs_data_update_from_pplib(struct dc *dc) 1203 { 1204 struct dm_pp_clock_levels clks = {0}; 1205 1206 /*do system clock*/ 1207 dm_pp_get_clock_levels_by_type( 1208 dc->ctx, 1209 DM_PP_CLOCK_TYPE_ENGINE_CLK, 1210 &clks); 1211 /* convert all the clock fro kHz to fix point mHz */ 1212 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 1213 clks.clocks_in_khz[clks.num_levels-1], 1000); 1214 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 1215 clks.clocks_in_khz[clks.num_levels/8], 1000); 1216 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 1217 clks.clocks_in_khz[clks.num_levels*2/8], 1000); 1218 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 1219 clks.clocks_in_khz[clks.num_levels*3/8], 1000); 1220 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 1221 clks.clocks_in_khz[clks.num_levels*4/8], 1000); 1222 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 1223 clks.clocks_in_khz[clks.num_levels*5/8], 1000); 1224 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1225 clks.clocks_in_khz[clks.num_levels*6/8], 1000); 1226 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1227 clks.clocks_in_khz[0], 1000); 1228 dc->sclk_lvls = clks; 1229 1230 /*do display clock*/ 1231 dm_pp_get_clock_levels_by_type( 1232 dc->ctx, 1233 DM_PP_CLOCK_TYPE_DISPLAY_CLK, 1234 &clks); 1235 dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed( 1236 clks.clocks_in_khz[clks.num_levels-1], 1000); 1237 dc->bw_vbios->mid_voltage_max_dispclk = bw_frc_to_fixed( 1238 clks.clocks_in_khz[clks.num_levels>>1], 1000); 1239 dc->bw_vbios->low_voltage_max_dispclk = bw_frc_to_fixed( 1240 clks.clocks_in_khz[0], 1000); 1241 1242 /*do memory clock*/ 1243 dm_pp_get_clock_levels_by_type( 1244 dc->ctx, 1245 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1246 &clks); 1247 1248 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1249 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER_CZ, 1000); 1250 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1251 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ, 1252 1000); 1253 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1254 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER_CZ, 1255 1000); 1256 } 1257 1258 const struct resource_caps *dce110_resource_cap( 1259 struct hw_asic_id *asic_id) 1260 { 1261 if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev)) 1262 return &stoney_resource_cap; 1263 else 1264 return &carrizo_resource_cap; 1265 } 1266 1267 static bool construct( 1268 uint8_t num_virtual_links, 1269 struct dc *dc, 1270 struct dce110_resource_pool *pool, 1271 struct hw_asic_id asic_id) 1272 { 1273 unsigned int i; 1274 struct dc_context *ctx = dc->ctx; 1275 struct dc_firmware_info info; 1276 struct dc_bios *bp; 1277 1278 ctx->dc_bios->regs = &bios_regs; 1279 1280 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); 1281 pool->base.funcs = &dce110_res_pool_funcs; 1282 1283 /************************************************* 1284 * Resource + asic cap harcoding * 1285 *************************************************/ 1286 1287 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1288 pool->base.underlay_pipe_index = pool->base.pipe_count; 1289 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1290 dc->caps.max_downscale_ratio = 150; 1291 dc->caps.i2c_speed_in_khz = 100; 1292 dc->caps.max_cursor_size = 128; 1293 dc->caps.is_apu = true; 1294 1295 /************************************************* 1296 * Create resources * 1297 *************************************************/ 1298 1299 bp = ctx->dc_bios; 1300 1301 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1302 info.external_clock_source_frequency_for_dp != 0) { 1303 pool->base.dp_clock_source = 1304 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1305 1306 pool->base.clock_sources[0] = 1307 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, 1308 &clk_src_regs[0], false); 1309 pool->base.clock_sources[1] = 1310 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, 1311 &clk_src_regs[1], false); 1312 1313 pool->base.clk_src_count = 2; 1314 1315 /* TODO: find out if CZ support 3 PLLs */ 1316 } 1317 1318 if (pool->base.dp_clock_source == NULL) { 1319 dm_error("DC: failed to create dp clock source!\n"); 1320 BREAK_TO_DEBUGGER(); 1321 goto res_create_fail; 1322 } 1323 1324 for (i = 0; i < pool->base.clk_src_count; i++) { 1325 if (pool->base.clock_sources[i] == NULL) { 1326 dm_error("DC: failed to create clock sources!\n"); 1327 BREAK_TO_DEBUGGER(); 1328 goto res_create_fail; 1329 } 1330 } 1331 1332 pool->base.dmcu = dce_dmcu_create(ctx, 1333 &dmcu_regs, 1334 &dmcu_shift, 1335 &dmcu_mask); 1336 if (pool->base.dmcu == NULL) { 1337 dm_error("DC: failed to create dmcu!\n"); 1338 BREAK_TO_DEBUGGER(); 1339 goto res_create_fail; 1340 } 1341 1342 pool->base.abm = dce_abm_create(ctx, 1343 &abm_regs, 1344 &abm_shift, 1345 &abm_mask); 1346 if (pool->base.abm == NULL) { 1347 dm_error("DC: failed to create abm!\n"); 1348 BREAK_TO_DEBUGGER(); 1349 goto res_create_fail; 1350 } 1351 1352 { 1353 struct irq_service_init_data init_data; 1354 init_data.ctx = dc->ctx; 1355 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 1356 if (!pool->base.irqs) 1357 goto res_create_fail; 1358 } 1359 1360 for (i = 0; i < pool->base.pipe_count; i++) { 1361 pool->base.timing_generators[i] = dce110_timing_generator_create( 1362 ctx, i, &dce110_tg_offsets[i]); 1363 if (pool->base.timing_generators[i] == NULL) { 1364 BREAK_TO_DEBUGGER(); 1365 dm_error("DC: failed to create tg!\n"); 1366 goto res_create_fail; 1367 } 1368 1369 pool->base.mis[i] = dce110_mem_input_create(ctx, i); 1370 if (pool->base.mis[i] == NULL) { 1371 BREAK_TO_DEBUGGER(); 1372 dm_error( 1373 "DC: failed to create memory input!\n"); 1374 goto res_create_fail; 1375 } 1376 1377 pool->base.ipps[i] = dce110_ipp_create(ctx, i); 1378 if (pool->base.ipps[i] == NULL) { 1379 BREAK_TO_DEBUGGER(); 1380 dm_error( 1381 "DC: failed to create input pixel processor!\n"); 1382 goto res_create_fail; 1383 } 1384 1385 pool->base.transforms[i] = dce110_transform_create(ctx, i); 1386 if (pool->base.transforms[i] == NULL) { 1387 BREAK_TO_DEBUGGER(); 1388 dm_error( 1389 "DC: failed to create transform!\n"); 1390 goto res_create_fail; 1391 } 1392 1393 pool->base.opps[i] = dce110_opp_create(ctx, i); 1394 if (pool->base.opps[i] == NULL) { 1395 BREAK_TO_DEBUGGER(); 1396 dm_error( 1397 "DC: failed to create output pixel processor!\n"); 1398 goto res_create_fail; 1399 } 1400 } 1401 1402 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1403 pool->base.engines[i] = dce110_aux_engine_create(ctx, i); 1404 if (pool->base.engines[i] == NULL) { 1405 BREAK_TO_DEBUGGER(); 1406 dm_error( 1407 "DC:failed to create aux engine!!\n"); 1408 goto res_create_fail; 1409 } 1410 pool->base.hw_i2cs[i] = dce110_i2c_hw_create(ctx, i); 1411 if (pool->base.hw_i2cs[i] == NULL) { 1412 BREAK_TO_DEBUGGER(); 1413 dm_error( 1414 "DC:failed to create i2c engine!!\n"); 1415 goto res_create_fail; 1416 } 1417 pool->base.sw_i2cs[i] = NULL; 1418 } 1419 1420 if (dc->config.fbc_support) 1421 dc->fbc_compressor = dce110_compressor_create(ctx); 1422 1423 if (!underlay_create(ctx, &pool->base)) 1424 goto res_create_fail; 1425 1426 if (!resource_construct(num_virtual_links, dc, &pool->base, 1427 &res_create_funcs)) 1428 goto res_create_fail; 1429 1430 /* Create hardware sequencer */ 1431 dce110_hw_sequencer_construct(dc); 1432 1433 dc->caps.max_planes = pool->base.pipe_count; 1434 1435 for (i = 0; i < pool->base.underlay_pipe_index; ++i) 1436 dc->caps.planes[i] = plane_cap; 1437 1438 dc->caps.planes[pool->base.underlay_pipe_index] = underlay_plane_cap; 1439 1440 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1441 1442 bw_calcs_data_update_from_pplib(dc); 1443 1444 return true; 1445 1446 res_create_fail: 1447 destruct(pool); 1448 return false; 1449 } 1450 1451 struct resource_pool *dce110_create_resource_pool( 1452 uint8_t num_virtual_links, 1453 struct dc *dc, 1454 struct hw_asic_id asic_id) 1455 { 1456 struct dce110_resource_pool *pool = 1457 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1458 1459 if (!pool) 1460 return NULL; 1461 1462 if (construct(num_virtual_links, dc, pool, asic_id)) 1463 return &pool->base; 1464 1465 BREAK_TO_DEBUGGER(); 1466 return NULL; 1467 } 1468