1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "link_encoder.h" 29 #include "stream_encoder.h" 30 31 #include "resource.h" 32 #include "dce110/dce110_resource.h" 33 34 #include "include/irq_service_interface.h" 35 #include "dce/dce_audio.h" 36 #include "dce110/dce110_timing_generator.h" 37 #include "irq/dce110/irq_service_dce110.h" 38 #include "dce110/dce110_timing_generator_v.h" 39 #include "dce/dce_link_encoder.h" 40 #include "dce/dce_stream_encoder.h" 41 #include "dce/dce_mem_input.h" 42 #include "dce110/dce110_mem_input_v.h" 43 #include "dce/dce_ipp.h" 44 #include "dce/dce_transform.h" 45 #include "dce110/dce110_transform_v.h" 46 #include "dce/dce_opp.h" 47 #include "dce110/dce110_opp_v.h" 48 #include "dce/dce_clocks.h" 49 #include "dce/dce_clock_source.h" 50 #include "dce/dce_hwseq.h" 51 #include "dce110/dce110_hw_sequencer.h" 52 #include "dce/dce_aux.h" 53 #include "dce/dce_abm.h" 54 #include "dce/dce_dmcu.h" 55 #include "dce/dce_i2c.h" 56 57 #define DC_LOGGER \ 58 dc->ctx->logger 59 60 #include "dce110/dce110_compressor.h" 61 62 #include "reg_helper.h" 63 64 #include "dce/dce_11_0_d.h" 65 #include "dce/dce_11_0_sh_mask.h" 66 67 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 68 #include "gmc/gmc_8_2_d.h" 69 #include "gmc/gmc_8_2_sh_mask.h" 70 #endif 71 72 #ifndef mmDP_DPHY_INTERNAL_CTRL 73 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 74 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 75 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 76 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 77 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 78 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 79 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 80 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 81 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 82 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 83 #endif 84 85 #ifndef mmBIOS_SCRATCH_2 86 #define mmBIOS_SCRATCH_2 0x05CB 87 #define mmBIOS_SCRATCH_6 0x05CF 88 #endif 89 90 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 91 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 92 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 93 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 94 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 95 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 96 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 97 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 98 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 99 #endif 100 101 #ifndef mmDP_DPHY_FAST_TRAINING 102 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 103 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 104 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 105 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 106 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 107 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 108 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 109 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 110 #endif 111 112 #ifndef DPHY_RX_FAST_TRAINING_CAPABLE 113 #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1 114 #endif 115 116 static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = { 117 { 118 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 119 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 120 }, 121 { 122 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 123 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 124 }, 125 { 126 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 127 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 128 }, 129 { 130 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 131 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 132 }, 133 { 134 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 135 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 136 }, 137 { 138 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 139 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 140 } 141 }; 142 143 /* set register offset */ 144 #define SR(reg_name)\ 145 .reg_name = mm ## reg_name 146 147 /* set register offset with instance */ 148 #define SRI(reg_name, block, id)\ 149 .reg_name = mm ## block ## id ## _ ## reg_name 150 151 static const struct dccg_registers disp_clk_regs = { 152 CLK_COMMON_REG_LIST_DCE_BASE() 153 }; 154 155 static const struct dccg_shift disp_clk_shift = { 156 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 157 }; 158 159 static const struct dccg_mask disp_clk_mask = { 160 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 161 }; 162 163 static const struct dce_dmcu_registers dmcu_regs = { 164 DMCU_DCE110_COMMON_REG_LIST() 165 }; 166 167 static const struct dce_dmcu_shift dmcu_shift = { 168 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 169 }; 170 171 static const struct dce_dmcu_mask dmcu_mask = { 172 DMCU_MASK_SH_LIST_DCE110(_MASK) 173 }; 174 175 static const struct dce_abm_registers abm_regs = { 176 ABM_DCE110_COMMON_REG_LIST() 177 }; 178 179 static const struct dce_abm_shift abm_shift = { 180 ABM_MASK_SH_LIST_DCE110(__SHIFT) 181 }; 182 183 static const struct dce_abm_mask abm_mask = { 184 ABM_MASK_SH_LIST_DCE110(_MASK) 185 }; 186 187 #define ipp_regs(id)\ 188 [id] = {\ 189 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 190 } 191 192 static const struct dce_ipp_registers ipp_regs[] = { 193 ipp_regs(0), 194 ipp_regs(1), 195 ipp_regs(2) 196 }; 197 198 static const struct dce_ipp_shift ipp_shift = { 199 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 200 }; 201 202 static const struct dce_ipp_mask ipp_mask = { 203 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 204 }; 205 206 #define transform_regs(id)\ 207 [id] = {\ 208 XFM_COMMON_REG_LIST_DCE110(id)\ 209 } 210 211 static const struct dce_transform_registers xfm_regs[] = { 212 transform_regs(0), 213 transform_regs(1), 214 transform_regs(2) 215 }; 216 217 static const struct dce_transform_shift xfm_shift = { 218 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 219 }; 220 221 static const struct dce_transform_mask xfm_mask = { 222 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 223 }; 224 225 #define aux_regs(id)\ 226 [id] = {\ 227 AUX_REG_LIST(id)\ 228 } 229 230 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 231 aux_regs(0), 232 aux_regs(1), 233 aux_regs(2), 234 aux_regs(3), 235 aux_regs(4), 236 aux_regs(5) 237 }; 238 239 #define hpd_regs(id)\ 240 [id] = {\ 241 HPD_REG_LIST(id)\ 242 } 243 244 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 245 hpd_regs(0), 246 hpd_regs(1), 247 hpd_regs(2), 248 hpd_regs(3), 249 hpd_regs(4), 250 hpd_regs(5) 251 }; 252 253 254 #define link_regs(id)\ 255 [id] = {\ 256 LE_DCE110_REG_LIST(id)\ 257 } 258 259 static const struct dce110_link_enc_registers link_enc_regs[] = { 260 link_regs(0), 261 link_regs(1), 262 link_regs(2), 263 link_regs(3), 264 link_regs(4), 265 link_regs(5), 266 link_regs(6), 267 }; 268 269 #define stream_enc_regs(id)\ 270 [id] = {\ 271 SE_COMMON_REG_LIST(id),\ 272 .TMDS_CNTL = 0,\ 273 } 274 275 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 276 stream_enc_regs(0), 277 stream_enc_regs(1), 278 stream_enc_regs(2) 279 }; 280 281 static const struct dce_stream_encoder_shift se_shift = { 282 SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 283 }; 284 285 static const struct dce_stream_encoder_mask se_mask = { 286 SE_COMMON_MASK_SH_LIST_DCE110(_MASK) 287 }; 288 289 #define opp_regs(id)\ 290 [id] = {\ 291 OPP_DCE_110_REG_LIST(id),\ 292 } 293 294 static const struct dce_opp_registers opp_regs[] = { 295 opp_regs(0), 296 opp_regs(1), 297 opp_regs(2), 298 opp_regs(3), 299 opp_regs(4), 300 opp_regs(5) 301 }; 302 303 static const struct dce_opp_shift opp_shift = { 304 OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT) 305 }; 306 307 static const struct dce_opp_mask opp_mask = { 308 OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK) 309 }; 310 311 #define aux_engine_regs(id)\ 312 [id] = {\ 313 AUX_COMMON_REG_LIST(id), \ 314 .AUX_RESET_MASK = 0 \ 315 } 316 317 static const struct dce110_aux_registers aux_engine_regs[] = { 318 aux_engine_regs(0), 319 aux_engine_regs(1), 320 aux_engine_regs(2), 321 aux_engine_regs(3), 322 aux_engine_regs(4), 323 aux_engine_regs(5) 324 }; 325 326 #define audio_regs(id)\ 327 [id] = {\ 328 AUD_COMMON_REG_LIST(id)\ 329 } 330 331 static const struct dce_audio_registers audio_regs[] = { 332 audio_regs(0), 333 audio_regs(1), 334 audio_regs(2), 335 audio_regs(3), 336 audio_regs(4), 337 audio_regs(5), 338 audio_regs(6), 339 }; 340 341 static const struct dce_audio_shift audio_shift = { 342 AUD_COMMON_MASK_SH_LIST(__SHIFT) 343 }; 344 345 static const struct dce_aduio_mask audio_mask = { 346 AUD_COMMON_MASK_SH_LIST(_MASK) 347 }; 348 349 /* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */ 350 351 352 #define clk_src_regs(id)\ 353 [id] = {\ 354 CS_COMMON_REG_LIST_DCE_100_110(id),\ 355 } 356 357 static const struct dce110_clk_src_regs clk_src_regs[] = { 358 clk_src_regs(0), 359 clk_src_regs(1), 360 clk_src_regs(2) 361 }; 362 363 static const struct dce110_clk_src_shift cs_shift = { 364 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 365 }; 366 367 static const struct dce110_clk_src_mask cs_mask = { 368 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 369 }; 370 371 static const struct bios_registers bios_regs = { 372 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 373 }; 374 375 static const struct resource_caps carrizo_resource_cap = { 376 .num_timing_generator = 3, 377 .num_video_plane = 1, 378 .num_audio = 3, 379 .num_stream_encoder = 3, 380 .num_pll = 2, 381 .num_ddc = 3, 382 }; 383 384 static const struct resource_caps stoney_resource_cap = { 385 .num_timing_generator = 2, 386 .num_video_plane = 1, 387 .num_audio = 3, 388 .num_stream_encoder = 3, 389 .num_pll = 2, 390 .num_ddc = 3, 391 }; 392 393 #define CTX ctx 394 #define REG(reg) mm ## reg 395 396 #ifndef mmCC_DC_HDMI_STRAPS 397 #define mmCC_DC_HDMI_STRAPS 0x4819 398 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 399 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 400 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 401 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 402 #endif 403 404 static void read_dce_straps( 405 struct dc_context *ctx, 406 struct resource_straps *straps) 407 { 408 REG_GET_2(CC_DC_HDMI_STRAPS, 409 HDMI_DISABLE, &straps->hdmi_disable, 410 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 411 412 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 413 } 414 415 static struct audio *create_audio( 416 struct dc_context *ctx, unsigned int inst) 417 { 418 return dce_audio_create(ctx, inst, 419 &audio_regs[inst], &audio_shift, &audio_mask); 420 } 421 422 static struct timing_generator *dce110_timing_generator_create( 423 struct dc_context *ctx, 424 uint32_t instance, 425 const struct dce110_timing_generator_offsets *offsets) 426 { 427 struct dce110_timing_generator *tg110 = 428 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 429 430 if (!tg110) 431 return NULL; 432 433 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 434 return &tg110->base; 435 } 436 437 static struct stream_encoder *dce110_stream_encoder_create( 438 enum engine_id eng_id, 439 struct dc_context *ctx) 440 { 441 struct dce110_stream_encoder *enc110 = 442 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 443 444 if (!enc110) 445 return NULL; 446 447 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 448 &stream_enc_regs[eng_id], 449 &se_shift, &se_mask); 450 return &enc110->base; 451 } 452 453 #define SRII(reg_name, block, id)\ 454 .reg_name[id] = mm ## block ## id ## _ ## reg_name 455 456 static const struct dce_hwseq_registers hwseq_stoney_reg = { 457 HWSEQ_ST_REG_LIST() 458 }; 459 460 static const struct dce_hwseq_registers hwseq_cz_reg = { 461 HWSEQ_CZ_REG_LIST() 462 }; 463 464 static const struct dce_hwseq_shift hwseq_shift = { 465 HWSEQ_DCE11_MASK_SH_LIST(__SHIFT), 466 }; 467 468 static const struct dce_hwseq_mask hwseq_mask = { 469 HWSEQ_DCE11_MASK_SH_LIST(_MASK), 470 }; 471 472 static struct dce_hwseq *dce110_hwseq_create( 473 struct dc_context *ctx) 474 { 475 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 476 477 if (hws) { 478 hws->ctx = ctx; 479 hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ? 480 &hwseq_stoney_reg : &hwseq_cz_reg; 481 hws->shifts = &hwseq_shift; 482 hws->masks = &hwseq_mask; 483 hws->wa.blnd_crtc_trigger = true; 484 } 485 return hws; 486 } 487 488 static const struct resource_create_funcs res_create_funcs = { 489 .read_dce_straps = read_dce_straps, 490 .create_audio = create_audio, 491 .create_stream_encoder = dce110_stream_encoder_create, 492 .create_hwseq = dce110_hwseq_create, 493 }; 494 495 #define mi_inst_regs(id) { \ 496 MI_DCE11_REG_LIST(id), \ 497 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 498 } 499 static const struct dce_mem_input_registers mi_regs[] = { 500 mi_inst_regs(0), 501 mi_inst_regs(1), 502 mi_inst_regs(2), 503 }; 504 505 static const struct dce_mem_input_shift mi_shifts = { 506 MI_DCE11_MASK_SH_LIST(__SHIFT), 507 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 508 }; 509 510 static const struct dce_mem_input_mask mi_masks = { 511 MI_DCE11_MASK_SH_LIST(_MASK), 512 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 513 }; 514 515 516 static struct mem_input *dce110_mem_input_create( 517 struct dc_context *ctx, 518 uint32_t inst) 519 { 520 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 521 GFP_KERNEL); 522 523 if (!dce_mi) { 524 BREAK_TO_DEBUGGER(); 525 return NULL; 526 } 527 528 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 529 dce_mi->wa.single_head_rdreq_dmif_limit = 3; 530 return &dce_mi->base; 531 } 532 533 static void dce110_transform_destroy(struct transform **xfm) 534 { 535 kfree(TO_DCE_TRANSFORM(*xfm)); 536 *xfm = NULL; 537 } 538 539 static struct transform *dce110_transform_create( 540 struct dc_context *ctx, 541 uint32_t inst) 542 { 543 struct dce_transform *transform = 544 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 545 546 if (!transform) 547 return NULL; 548 549 dce_transform_construct(transform, ctx, inst, 550 &xfm_regs[inst], &xfm_shift, &xfm_mask); 551 return &transform->base; 552 } 553 554 static struct input_pixel_processor *dce110_ipp_create( 555 struct dc_context *ctx, uint32_t inst) 556 { 557 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 558 559 if (!ipp) { 560 BREAK_TO_DEBUGGER(); 561 return NULL; 562 } 563 564 dce_ipp_construct(ipp, ctx, inst, 565 &ipp_regs[inst], &ipp_shift, &ipp_mask); 566 return &ipp->base; 567 } 568 569 static const struct encoder_feature_support link_enc_feature = { 570 .max_hdmi_deep_color = COLOR_DEPTH_121212, 571 .max_hdmi_pixel_clock = 300000, 572 .flags.bits.IS_HBR2_CAPABLE = true, 573 .flags.bits.IS_TPS3_CAPABLE = true 574 }; 575 576 static struct link_encoder *dce110_link_encoder_create( 577 const struct encoder_init_data *enc_init_data) 578 { 579 struct dce110_link_encoder *enc110 = 580 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 581 582 if (!enc110) 583 return NULL; 584 585 dce110_link_encoder_construct(enc110, 586 enc_init_data, 587 &link_enc_feature, 588 &link_enc_regs[enc_init_data->transmitter], 589 &link_enc_aux_regs[enc_init_data->channel - 1], 590 &link_enc_hpd_regs[enc_init_data->hpd_source]); 591 return &enc110->base; 592 } 593 594 static struct output_pixel_processor *dce110_opp_create( 595 struct dc_context *ctx, 596 uint32_t inst) 597 { 598 struct dce110_opp *opp = 599 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 600 601 if (!opp) 602 return NULL; 603 604 dce110_opp_construct(opp, 605 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 606 return &opp->base; 607 } 608 609 struct aux_engine *dce110_aux_engine_create( 610 struct dc_context *ctx, 611 uint32_t inst) 612 { 613 struct aux_engine_dce110 *aux_engine = 614 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 615 616 if (!aux_engine) 617 return NULL; 618 619 dce110_aux_engine_construct(aux_engine, ctx, inst, 620 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 621 &aux_engine_regs[inst]); 622 623 return &aux_engine->base; 624 } 625 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 626 627 static const struct dce_i2c_registers i2c_hw_regs[] = { 628 i2c_inst_regs(1), 629 i2c_inst_regs(2), 630 i2c_inst_regs(3), 631 i2c_inst_regs(4), 632 i2c_inst_regs(5), 633 i2c_inst_regs(6), 634 }; 635 636 static const struct dce_i2c_shift i2c_shifts = { 637 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 638 }; 639 640 static const struct dce_i2c_mask i2c_masks = { 641 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 642 }; 643 644 struct dce_i2c_hw *dce110_i2c_hw_create( 645 struct dc_context *ctx, 646 uint32_t inst) 647 { 648 struct dce_i2c_hw *dce_i2c_hw = 649 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 650 651 if (!dce_i2c_hw) 652 return NULL; 653 654 dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst, 655 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 656 657 return dce_i2c_hw; 658 } 659 struct clock_source *dce110_clock_source_create( 660 struct dc_context *ctx, 661 struct dc_bios *bios, 662 enum clock_source_id id, 663 const struct dce110_clk_src_regs *regs, 664 bool dp_clk_src) 665 { 666 struct dce110_clk_src *clk_src = 667 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 668 669 if (!clk_src) 670 return NULL; 671 672 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 673 regs, &cs_shift, &cs_mask)) { 674 clk_src->base.dp_clk_src = dp_clk_src; 675 return &clk_src->base; 676 } 677 678 BREAK_TO_DEBUGGER(); 679 return NULL; 680 } 681 682 void dce110_clock_source_destroy(struct clock_source **clk_src) 683 { 684 struct dce110_clk_src *dce110_clk_src; 685 686 if (!clk_src) 687 return; 688 689 dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src); 690 691 kfree(dce110_clk_src->dp_ss_params); 692 kfree(dce110_clk_src->hdmi_ss_params); 693 kfree(dce110_clk_src->dvi_ss_params); 694 695 kfree(dce110_clk_src); 696 *clk_src = NULL; 697 } 698 699 static void destruct(struct dce110_resource_pool *pool) 700 { 701 unsigned int i; 702 703 for (i = 0; i < pool->base.pipe_count; i++) { 704 if (pool->base.opps[i] != NULL) 705 dce110_opp_destroy(&pool->base.opps[i]); 706 707 if (pool->base.transforms[i] != NULL) 708 dce110_transform_destroy(&pool->base.transforms[i]); 709 710 if (pool->base.ipps[i] != NULL) 711 dce_ipp_destroy(&pool->base.ipps[i]); 712 713 if (pool->base.mis[i] != NULL) { 714 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 715 pool->base.mis[i] = NULL; 716 } 717 718 if (pool->base.timing_generators[i] != NULL) { 719 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 720 pool->base.timing_generators[i] = NULL; 721 } 722 } 723 724 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 725 if (pool->base.engines[i] != NULL) 726 dce110_engine_destroy(&pool->base.engines[i]); 727 if (pool->base.hw_i2cs[i] != NULL) { 728 kfree(pool->base.hw_i2cs[i]); 729 pool->base.hw_i2cs[i] = NULL; 730 } 731 if (pool->base.sw_i2cs[i] != NULL) { 732 kfree(pool->base.sw_i2cs[i]); 733 pool->base.sw_i2cs[i] = NULL; 734 } 735 } 736 737 for (i = 0; i < pool->base.stream_enc_count; i++) { 738 if (pool->base.stream_enc[i] != NULL) 739 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 740 } 741 742 for (i = 0; i < pool->base.clk_src_count; i++) { 743 if (pool->base.clock_sources[i] != NULL) { 744 dce110_clock_source_destroy(&pool->base.clock_sources[i]); 745 } 746 } 747 748 if (pool->base.dp_clock_source != NULL) 749 dce110_clock_source_destroy(&pool->base.dp_clock_source); 750 751 for (i = 0; i < pool->base.audio_count; i++) { 752 if (pool->base.audios[i] != NULL) { 753 dce_aud_destroy(&pool->base.audios[i]); 754 } 755 } 756 757 if (pool->base.abm != NULL) 758 dce_abm_destroy(&pool->base.abm); 759 760 if (pool->base.dmcu != NULL) 761 dce_dmcu_destroy(&pool->base.dmcu); 762 763 if (pool->base.dccg != NULL) 764 dce_dccg_destroy(&pool->base.dccg); 765 766 if (pool->base.irqs != NULL) { 767 dal_irq_service_destroy(&pool->base.irqs); 768 } 769 } 770 771 772 static void get_pixel_clock_parameters( 773 const struct pipe_ctx *pipe_ctx, 774 struct pixel_clk_params *pixel_clk_params) 775 { 776 const struct dc_stream_state *stream = pipe_ctx->stream; 777 778 /*TODO: is this halved for YCbCr 420? in that case we might want to move 779 * the pixel clock normalization for hdmi up to here instead of doing it 780 * in pll_adjust_pix_clk 781 */ 782 pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz; 783 pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id; 784 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 785 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 786 /* TODO: un-hardcode*/ 787 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 788 LINK_RATE_REF_FREQ_IN_KHZ; 789 pixel_clk_params->flags.ENABLE_SS = 0; 790 pixel_clk_params->color_depth = 791 stream->timing.display_color_depth; 792 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 793 pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding == 794 PIXEL_ENCODING_YCBCR420); 795 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 796 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) { 797 pixel_clk_params->color_depth = COLOR_DEPTH_888; 798 } 799 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 800 pixel_clk_params->requested_pix_clk = pixel_clk_params->requested_pix_clk / 2; 801 } 802 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 803 pixel_clk_params->requested_pix_clk *= 2; 804 805 } 806 807 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 808 { 809 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 810 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 811 pipe_ctx->clock_source, 812 &pipe_ctx->stream_res.pix_clk_params, 813 &pipe_ctx->pll_settings); 814 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 815 &pipe_ctx->stream->bit_depth_params); 816 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 817 } 818 819 static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx) 820 { 821 if (pipe_ctx->pipe_idx != underlay_idx) 822 return true; 823 if (!pipe_ctx->plane_state) 824 return false; 825 if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 826 return false; 827 return true; 828 } 829 830 static enum dc_status build_mapped_resource( 831 const struct dc *dc, 832 struct dc_state *context, 833 struct dc_stream_state *stream) 834 { 835 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 836 837 if (!pipe_ctx) 838 return DC_ERROR_UNEXPECTED; 839 840 if (!is_surface_pixel_format_supported(pipe_ctx, 841 dc->res_pool->underlay_pipe_index)) 842 return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; 843 844 dce110_resource_build_pipe_hw_param(pipe_ctx); 845 846 /* TODO: validate audio ASIC caps, encoder */ 847 848 resource_build_info_frame(pipe_ctx); 849 850 return DC_OK; 851 } 852 853 static bool dce110_validate_bandwidth( 854 struct dc *dc, 855 struct dc_state *context) 856 { 857 bool result = false; 858 859 DC_LOG_BANDWIDTH_CALCS( 860 "%s: start", 861 __func__); 862 863 if (bw_calcs( 864 dc->ctx, 865 dc->bw_dceip, 866 dc->bw_vbios, 867 context->res_ctx.pipe_ctx, 868 dc->res_pool->pipe_count, 869 &context->bw.dce)) 870 result = true; 871 872 if (!result) 873 DC_LOG_BANDWIDTH_VALIDATION("%s: %dx%d@%d Bandwidth validation failed!\n", 874 __func__, 875 context->streams[0]->timing.h_addressable, 876 context->streams[0]->timing.v_addressable, 877 context->streams[0]->timing.pix_clk_khz); 878 879 if (memcmp(&dc->current_state->bw.dce, 880 &context->bw.dce, sizeof(context->bw.dce))) { 881 882 DC_LOG_BANDWIDTH_CALCS( 883 "%s: finish,\n" 884 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 885 "stutMark_b: %d stutMark_a: %d\n" 886 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 887 "stutMark_b: %d stutMark_a: %d\n" 888 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 889 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n" 890 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" 891 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n" 892 , 893 __func__, 894 context->bw.dce.nbp_state_change_wm_ns[0].b_mark, 895 context->bw.dce.nbp_state_change_wm_ns[0].a_mark, 896 context->bw.dce.urgent_wm_ns[0].b_mark, 897 context->bw.dce.urgent_wm_ns[0].a_mark, 898 context->bw.dce.stutter_exit_wm_ns[0].b_mark, 899 context->bw.dce.stutter_exit_wm_ns[0].a_mark, 900 context->bw.dce.nbp_state_change_wm_ns[1].b_mark, 901 context->bw.dce.nbp_state_change_wm_ns[1].a_mark, 902 context->bw.dce.urgent_wm_ns[1].b_mark, 903 context->bw.dce.urgent_wm_ns[1].a_mark, 904 context->bw.dce.stutter_exit_wm_ns[1].b_mark, 905 context->bw.dce.stutter_exit_wm_ns[1].a_mark, 906 context->bw.dce.nbp_state_change_wm_ns[2].b_mark, 907 context->bw.dce.nbp_state_change_wm_ns[2].a_mark, 908 context->bw.dce.urgent_wm_ns[2].b_mark, 909 context->bw.dce.urgent_wm_ns[2].a_mark, 910 context->bw.dce.stutter_exit_wm_ns[2].b_mark, 911 context->bw.dce.stutter_exit_wm_ns[2].a_mark, 912 context->bw.dce.stutter_mode_enable, 913 context->bw.dce.cpuc_state_change_enable, 914 context->bw.dce.cpup_state_change_enable, 915 context->bw.dce.nbp_state_change_enable, 916 context->bw.dce.all_displays_in_sync, 917 context->bw.dce.dispclk_khz, 918 context->bw.dce.sclk_khz, 919 context->bw.dce.sclk_deep_sleep_khz, 920 context->bw.dce.yclk_khz, 921 context->bw.dce.blackout_recovery_time_us); 922 } 923 return result; 924 } 925 926 enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state, 927 struct dc_caps *caps) 928 { 929 if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) || 930 ((plane_state->dst_rect.height * 2) < plane_state->src_rect.height)) 931 return DC_FAIL_SURFACE_VALIDATE; 932 933 return DC_OK; 934 } 935 936 static bool dce110_validate_surface_sets( 937 struct dc_state *context) 938 { 939 int i, j; 940 941 for (i = 0; i < context->stream_count; i++) { 942 if (context->stream_status[i].plane_count == 0) 943 continue; 944 945 if (context->stream_status[i].plane_count > 2) 946 return false; 947 948 for (j = 0; j < context->stream_status[i].plane_count; j++) { 949 struct dc_plane_state *plane = 950 context->stream_status[i].plane_states[j]; 951 952 /* underlay validation */ 953 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 954 955 if ((plane->src_rect.width > 1920 || 956 plane->src_rect.height > 1080)) 957 return false; 958 959 /* we don't have the logic to support underlay 960 * only yet so block the use case where we get 961 * NV12 plane as top layer 962 */ 963 if (j == 0) 964 return false; 965 966 /* irrespective of plane format, 967 * stream should be RGB encoded 968 */ 969 if (context->streams[i]->timing.pixel_encoding 970 != PIXEL_ENCODING_RGB) 971 return false; 972 973 } 974 975 } 976 } 977 978 return true; 979 } 980 981 enum dc_status dce110_validate_global( 982 struct dc *dc, 983 struct dc_state *context) 984 { 985 if (!dce110_validate_surface_sets(context)) 986 return DC_FAIL_SURFACE_VALIDATE; 987 988 return DC_OK; 989 } 990 991 static enum dc_status dce110_add_stream_to_ctx( 992 struct dc *dc, 993 struct dc_state *new_ctx, 994 struct dc_stream_state *dc_stream) 995 { 996 enum dc_status result = DC_ERROR_UNEXPECTED; 997 998 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 999 1000 if (result == DC_OK) 1001 result = resource_map_clock_resources(dc, new_ctx, dc_stream); 1002 1003 1004 if (result == DC_OK) 1005 result = build_mapped_resource(dc, new_ctx, dc_stream); 1006 1007 return result; 1008 } 1009 1010 static struct pipe_ctx *dce110_acquire_underlay( 1011 struct dc_state *context, 1012 const struct resource_pool *pool, 1013 struct dc_stream_state *stream) 1014 { 1015 struct dc *dc = stream->ctx->dc; 1016 struct resource_context *res_ctx = &context->res_ctx; 1017 unsigned int underlay_idx = pool->underlay_pipe_index; 1018 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; 1019 1020 if (res_ctx->pipe_ctx[underlay_idx].stream) 1021 return NULL; 1022 1023 pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx]; 1024 pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; 1025 /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/ 1026 pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; 1027 pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; 1028 pipe_ctx->pipe_idx = underlay_idx; 1029 1030 pipe_ctx->stream = stream; 1031 1032 if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) { 1033 struct tg_color black_color = {0}; 1034 struct dc_bios *dcb = dc->ctx->dc_bios; 1035 1036 dc->hwss.enable_display_power_gating( 1037 dc, 1038 pipe_ctx->stream_res.tg->inst, 1039 dcb, PIPE_GATING_CONTROL_DISABLE); 1040 1041 /* 1042 * This is for powering on underlay, so crtc does not 1043 * need to be enabled 1044 */ 1045 1046 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg, 1047 &stream->timing, 1048 false); 1049 1050 pipe_ctx->stream_res.tg->funcs->enable_advanced_request( 1051 pipe_ctx->stream_res.tg, 1052 true, 1053 &stream->timing); 1054 1055 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi, 1056 stream->timing.h_total, 1057 stream->timing.v_total, 1058 stream->timing.pix_clk_khz, 1059 context->stream_count); 1060 1061 color_space_to_black_color(dc, 1062 COLOR_SPACE_YCBCR601, &black_color); 1063 pipe_ctx->stream_res.tg->funcs->set_blank_color( 1064 pipe_ctx->stream_res.tg, 1065 &black_color); 1066 } 1067 1068 return pipe_ctx; 1069 } 1070 1071 static void dce110_destroy_resource_pool(struct resource_pool **pool) 1072 { 1073 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 1074 1075 destruct(dce110_pool); 1076 kfree(dce110_pool); 1077 *pool = NULL; 1078 } 1079 1080 1081 static const struct resource_funcs dce110_res_pool_funcs = { 1082 .destroy = dce110_destroy_resource_pool, 1083 .link_enc_create = dce110_link_encoder_create, 1084 .validate_bandwidth = dce110_validate_bandwidth, 1085 .validate_plane = dce110_validate_plane, 1086 .acquire_idle_pipe_for_layer = dce110_acquire_underlay, 1087 .add_stream_to_ctx = dce110_add_stream_to_ctx, 1088 .validate_global = dce110_validate_global 1089 }; 1090 1091 static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) 1092 { 1093 struct dce110_timing_generator *dce110_tgv = kzalloc(sizeof(*dce110_tgv), 1094 GFP_KERNEL); 1095 struct dce_transform *dce110_xfmv = kzalloc(sizeof(*dce110_xfmv), 1096 GFP_KERNEL); 1097 struct dce_mem_input *dce110_miv = kzalloc(sizeof(*dce110_miv), 1098 GFP_KERNEL); 1099 struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv), 1100 GFP_KERNEL); 1101 1102 if (!dce110_tgv || !dce110_xfmv || !dce110_miv || !dce110_oppv) { 1103 kfree(dce110_tgv); 1104 kfree(dce110_xfmv); 1105 kfree(dce110_miv); 1106 kfree(dce110_oppv); 1107 return false; 1108 } 1109 1110 dce110_opp_v_construct(dce110_oppv, ctx); 1111 1112 dce110_timing_generator_v_construct(dce110_tgv, ctx); 1113 dce110_mem_input_v_construct(dce110_miv, ctx); 1114 dce110_transform_v_construct(dce110_xfmv, ctx); 1115 1116 pool->opps[pool->pipe_count] = &dce110_oppv->base; 1117 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; 1118 pool->mis[pool->pipe_count] = &dce110_miv->base; 1119 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; 1120 pool->pipe_count++; 1121 1122 /* update the public caps to indicate an underlay is available */ 1123 ctx->dc->caps.max_slave_planes = 1; 1124 ctx->dc->caps.max_slave_planes = 1; 1125 1126 return true; 1127 } 1128 1129 static void bw_calcs_data_update_from_pplib(struct dc *dc) 1130 { 1131 struct dm_pp_clock_levels clks = {0}; 1132 1133 /*do system clock*/ 1134 dm_pp_get_clock_levels_by_type( 1135 dc->ctx, 1136 DM_PP_CLOCK_TYPE_ENGINE_CLK, 1137 &clks); 1138 /* convert all the clock fro kHz to fix point mHz */ 1139 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 1140 clks.clocks_in_khz[clks.num_levels-1], 1000); 1141 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 1142 clks.clocks_in_khz[clks.num_levels/8], 1000); 1143 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 1144 clks.clocks_in_khz[clks.num_levels*2/8], 1000); 1145 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 1146 clks.clocks_in_khz[clks.num_levels*3/8], 1000); 1147 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 1148 clks.clocks_in_khz[clks.num_levels*4/8], 1000); 1149 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 1150 clks.clocks_in_khz[clks.num_levels*5/8], 1000); 1151 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1152 clks.clocks_in_khz[clks.num_levels*6/8], 1000); 1153 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1154 clks.clocks_in_khz[0], 1000); 1155 dc->sclk_lvls = clks; 1156 1157 /*do display clock*/ 1158 dm_pp_get_clock_levels_by_type( 1159 dc->ctx, 1160 DM_PP_CLOCK_TYPE_DISPLAY_CLK, 1161 &clks); 1162 dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed( 1163 clks.clocks_in_khz[clks.num_levels-1], 1000); 1164 dc->bw_vbios->mid_voltage_max_dispclk = bw_frc_to_fixed( 1165 clks.clocks_in_khz[clks.num_levels>>1], 1000); 1166 dc->bw_vbios->low_voltage_max_dispclk = bw_frc_to_fixed( 1167 clks.clocks_in_khz[0], 1000); 1168 1169 /*do memory clock*/ 1170 dm_pp_get_clock_levels_by_type( 1171 dc->ctx, 1172 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1173 &clks); 1174 1175 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1176 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000); 1177 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1178 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER, 1179 1000); 1180 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1181 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER, 1182 1000); 1183 } 1184 1185 const struct resource_caps *dce110_resource_cap( 1186 struct hw_asic_id *asic_id) 1187 { 1188 if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev)) 1189 return &stoney_resource_cap; 1190 else 1191 return &carrizo_resource_cap; 1192 } 1193 1194 static bool construct( 1195 uint8_t num_virtual_links, 1196 struct dc *dc, 1197 struct dce110_resource_pool *pool, 1198 struct hw_asic_id asic_id) 1199 { 1200 unsigned int i; 1201 struct dc_context *ctx = dc->ctx; 1202 struct dc_firmware_info info; 1203 struct dc_bios *bp; 1204 struct dm_pp_static_clock_info static_clk_info = {0}; 1205 1206 ctx->dc_bios->regs = &bios_regs; 1207 1208 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); 1209 pool->base.funcs = &dce110_res_pool_funcs; 1210 1211 /************************************************* 1212 * Resource + asic cap harcoding * 1213 *************************************************/ 1214 1215 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1216 pool->base.underlay_pipe_index = pool->base.pipe_count; 1217 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1218 dc->caps.max_downscale_ratio = 150; 1219 dc->caps.i2c_speed_in_khz = 100; 1220 dc->caps.max_cursor_size = 128; 1221 dc->caps.is_apu = true; 1222 1223 /************************************************* 1224 * Create resources * 1225 *************************************************/ 1226 1227 bp = ctx->dc_bios; 1228 1229 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1230 info.external_clock_source_frequency_for_dp != 0) { 1231 pool->base.dp_clock_source = 1232 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1233 1234 pool->base.clock_sources[0] = 1235 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, 1236 &clk_src_regs[0], false); 1237 pool->base.clock_sources[1] = 1238 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, 1239 &clk_src_regs[1], false); 1240 1241 pool->base.clk_src_count = 2; 1242 1243 /* TODO: find out if CZ support 3 PLLs */ 1244 } 1245 1246 if (pool->base.dp_clock_source == NULL) { 1247 dm_error("DC: failed to create dp clock source!\n"); 1248 BREAK_TO_DEBUGGER(); 1249 goto res_create_fail; 1250 } 1251 1252 for (i = 0; i < pool->base.clk_src_count; i++) { 1253 if (pool->base.clock_sources[i] == NULL) { 1254 dm_error("DC: failed to create clock sources!\n"); 1255 BREAK_TO_DEBUGGER(); 1256 goto res_create_fail; 1257 } 1258 } 1259 1260 pool->base.dccg = dce110_dccg_create(ctx, 1261 &disp_clk_regs, 1262 &disp_clk_shift, 1263 &disp_clk_mask); 1264 if (pool->base.dccg == NULL) { 1265 dm_error("DC: failed to create display clock!\n"); 1266 BREAK_TO_DEBUGGER(); 1267 goto res_create_fail; 1268 } 1269 1270 pool->base.dmcu = dce_dmcu_create(ctx, 1271 &dmcu_regs, 1272 &dmcu_shift, 1273 &dmcu_mask); 1274 if (pool->base.dmcu == NULL) { 1275 dm_error("DC: failed to create dmcu!\n"); 1276 BREAK_TO_DEBUGGER(); 1277 goto res_create_fail; 1278 } 1279 1280 pool->base.abm = dce_abm_create(ctx, 1281 &abm_regs, 1282 &abm_shift, 1283 &abm_mask); 1284 if (pool->base.abm == NULL) { 1285 dm_error("DC: failed to create abm!\n"); 1286 BREAK_TO_DEBUGGER(); 1287 goto res_create_fail; 1288 } 1289 1290 /* get static clock information for PPLIB or firmware, save 1291 * max_clock_state 1292 */ 1293 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 1294 pool->base.dccg->max_clks_state = 1295 static_clk_info.max_clocks_state; 1296 1297 { 1298 struct irq_service_init_data init_data; 1299 init_data.ctx = dc->ctx; 1300 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 1301 if (!pool->base.irqs) 1302 goto res_create_fail; 1303 } 1304 1305 for (i = 0; i < pool->base.pipe_count; i++) { 1306 pool->base.timing_generators[i] = dce110_timing_generator_create( 1307 ctx, i, &dce110_tg_offsets[i]); 1308 if (pool->base.timing_generators[i] == NULL) { 1309 BREAK_TO_DEBUGGER(); 1310 dm_error("DC: failed to create tg!\n"); 1311 goto res_create_fail; 1312 } 1313 1314 pool->base.mis[i] = dce110_mem_input_create(ctx, i); 1315 if (pool->base.mis[i] == NULL) { 1316 BREAK_TO_DEBUGGER(); 1317 dm_error( 1318 "DC: failed to create memory input!\n"); 1319 goto res_create_fail; 1320 } 1321 1322 pool->base.ipps[i] = dce110_ipp_create(ctx, i); 1323 if (pool->base.ipps[i] == NULL) { 1324 BREAK_TO_DEBUGGER(); 1325 dm_error( 1326 "DC: failed to create input pixel processor!\n"); 1327 goto res_create_fail; 1328 } 1329 1330 pool->base.transforms[i] = dce110_transform_create(ctx, i); 1331 if (pool->base.transforms[i] == NULL) { 1332 BREAK_TO_DEBUGGER(); 1333 dm_error( 1334 "DC: failed to create transform!\n"); 1335 goto res_create_fail; 1336 } 1337 1338 pool->base.opps[i] = dce110_opp_create(ctx, i); 1339 if (pool->base.opps[i] == NULL) { 1340 BREAK_TO_DEBUGGER(); 1341 dm_error( 1342 "DC: failed to create output pixel processor!\n"); 1343 goto res_create_fail; 1344 } 1345 } 1346 1347 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1348 pool->base.engines[i] = dce110_aux_engine_create(ctx, i); 1349 if (pool->base.engines[i] == NULL) { 1350 BREAK_TO_DEBUGGER(); 1351 dm_error( 1352 "DC:failed to create aux engine!!\n"); 1353 goto res_create_fail; 1354 } 1355 pool->base.hw_i2cs[i] = dce110_i2c_hw_create(ctx, i); 1356 if (pool->base.hw_i2cs[i] == NULL) { 1357 BREAK_TO_DEBUGGER(); 1358 dm_error( 1359 "DC:failed to create i2c engine!!\n"); 1360 goto res_create_fail; 1361 } 1362 pool->base.sw_i2cs[i] = NULL; 1363 } 1364 1365 if (dc->config.fbc_support) 1366 dc->fbc_compressor = dce110_compressor_create(ctx); 1367 1368 if (!underlay_create(ctx, &pool->base)) 1369 goto res_create_fail; 1370 1371 if (!resource_construct(num_virtual_links, dc, &pool->base, 1372 &res_create_funcs)) 1373 goto res_create_fail; 1374 1375 /* Create hardware sequencer */ 1376 dce110_hw_sequencer_construct(dc); 1377 1378 dc->caps.max_planes = pool->base.pipe_count; 1379 1380 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1381 1382 bw_calcs_data_update_from_pplib(dc); 1383 1384 return true; 1385 1386 res_create_fail: 1387 destruct(pool); 1388 return false; 1389 } 1390 1391 struct resource_pool *dce110_create_resource_pool( 1392 uint8_t num_virtual_links, 1393 struct dc *dc, 1394 struct hw_asic_id asic_id) 1395 { 1396 struct dce110_resource_pool *pool = 1397 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1398 1399 if (!pool) 1400 return NULL; 1401 1402 if (construct(num_virtual_links, dc, pool, asic_id)) 1403 return &pool->base; 1404 1405 BREAK_TO_DEBUGGER(); 1406 return NULL; 1407 } 1408