1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 30 #include "link_encoder.h" 31 #include "stream_encoder.h" 32 33 #include "resource.h" 34 #include "dce110/dce110_resource.h" 35 #include "include/irq_service_interface.h" 36 #include "dce/dce_audio.h" 37 #include "dce110/dce110_timing_generator.h" 38 #include "irq/dce110/irq_service_dce110.h" 39 #include "dce110/dce110_timing_generator_v.h" 40 #include "dce/dce_link_encoder.h" 41 #include "dce/dce_stream_encoder.h" 42 #include "dce/dce_mem_input.h" 43 #include "dce110/dce110_mem_input_v.h" 44 #include "dce/dce_ipp.h" 45 #include "dce/dce_transform.h" 46 #include "dce110/dce110_transform_v.h" 47 #include "dce/dce_opp.h" 48 #include "dce110/dce110_opp_v.h" 49 #include "dce/dce_clock_source.h" 50 #include "dce/dce_hwseq.h" 51 #include "dce110/dce110_hw_sequencer.h" 52 #include "dce/dce_aux.h" 53 #include "dce/dce_abm.h" 54 #include "dce/dce_dmcu.h" 55 #include "dce/dce_i2c.h" 56 57 #define DC_LOGGER \ 58 dc->ctx->logger 59 60 #include "dce110/dce110_compressor.h" 61 62 #include "reg_helper.h" 63 64 #include "dce/dce_11_0_d.h" 65 #include "dce/dce_11_0_sh_mask.h" 66 67 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 68 #include "gmc/gmc_8_2_d.h" 69 #include "gmc/gmc_8_2_sh_mask.h" 70 #endif 71 72 #ifndef mmDP_DPHY_INTERNAL_CTRL 73 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 74 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 75 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 76 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 77 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 78 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 79 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 80 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 81 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 82 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 83 #endif 84 85 #ifndef mmBIOS_SCRATCH_2 86 #define mmBIOS_SCRATCH_2 0x05CB 87 #define mmBIOS_SCRATCH_3 0x05CC 88 #define mmBIOS_SCRATCH_6 0x05CF 89 #endif 90 91 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 92 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 93 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 94 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 95 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 96 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 97 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 98 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 99 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 100 #endif 101 102 #ifndef mmDP_DPHY_FAST_TRAINING 103 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 104 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 105 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 106 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 107 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 108 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 109 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 110 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 111 #endif 112 113 #ifndef DPHY_RX_FAST_TRAINING_CAPABLE 114 #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1 115 #endif 116 117 static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = { 118 { 119 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 120 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 121 }, 122 { 123 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 124 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 125 }, 126 { 127 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 128 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 129 }, 130 { 131 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 132 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 133 }, 134 { 135 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 136 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 137 }, 138 { 139 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 140 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 141 } 142 }; 143 144 /* set register offset */ 145 #define SR(reg_name)\ 146 .reg_name = mm ## reg_name 147 148 /* set register offset with instance */ 149 #define SRI(reg_name, block, id)\ 150 .reg_name = mm ## block ## id ## _ ## reg_name 151 152 static const struct dce_dmcu_registers dmcu_regs = { 153 DMCU_DCE110_COMMON_REG_LIST() 154 }; 155 156 static const struct dce_dmcu_shift dmcu_shift = { 157 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 158 }; 159 160 static const struct dce_dmcu_mask dmcu_mask = { 161 DMCU_MASK_SH_LIST_DCE110(_MASK) 162 }; 163 164 static const struct dce_abm_registers abm_regs = { 165 ABM_DCE110_COMMON_REG_LIST() 166 }; 167 168 static const struct dce_abm_shift abm_shift = { 169 ABM_MASK_SH_LIST_DCE110(__SHIFT) 170 }; 171 172 static const struct dce_abm_mask abm_mask = { 173 ABM_MASK_SH_LIST_DCE110(_MASK) 174 }; 175 176 #define ipp_regs(id)\ 177 [id] = {\ 178 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 179 } 180 181 static const struct dce_ipp_registers ipp_regs[] = { 182 ipp_regs(0), 183 ipp_regs(1), 184 ipp_regs(2) 185 }; 186 187 static const struct dce_ipp_shift ipp_shift = { 188 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 189 }; 190 191 static const struct dce_ipp_mask ipp_mask = { 192 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 193 }; 194 195 #define transform_regs(id)\ 196 [id] = {\ 197 XFM_COMMON_REG_LIST_DCE110(id)\ 198 } 199 200 static const struct dce_transform_registers xfm_regs[] = { 201 transform_regs(0), 202 transform_regs(1), 203 transform_regs(2) 204 }; 205 206 static const struct dce_transform_shift xfm_shift = { 207 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 208 }; 209 210 static const struct dce_transform_mask xfm_mask = { 211 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 212 }; 213 214 #define aux_regs(id)\ 215 [id] = {\ 216 AUX_REG_LIST(id)\ 217 } 218 219 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 220 aux_regs(0), 221 aux_regs(1), 222 aux_regs(2), 223 aux_regs(3), 224 aux_regs(4), 225 aux_regs(5) 226 }; 227 228 #define hpd_regs(id)\ 229 [id] = {\ 230 HPD_REG_LIST(id)\ 231 } 232 233 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 234 hpd_regs(0), 235 hpd_regs(1), 236 hpd_regs(2), 237 hpd_regs(3), 238 hpd_regs(4), 239 hpd_regs(5) 240 }; 241 242 243 #define link_regs(id)\ 244 [id] = {\ 245 LE_DCE110_REG_LIST(id)\ 246 } 247 248 static const struct dce110_link_enc_registers link_enc_regs[] = { 249 link_regs(0), 250 link_regs(1), 251 link_regs(2), 252 link_regs(3), 253 link_regs(4), 254 link_regs(5), 255 link_regs(6), 256 }; 257 258 #define stream_enc_regs(id)\ 259 [id] = {\ 260 SE_COMMON_REG_LIST(id),\ 261 .TMDS_CNTL = 0,\ 262 } 263 264 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 265 stream_enc_regs(0), 266 stream_enc_regs(1), 267 stream_enc_regs(2) 268 }; 269 270 static const struct dce_stream_encoder_shift se_shift = { 271 SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 272 }; 273 274 static const struct dce_stream_encoder_mask se_mask = { 275 SE_COMMON_MASK_SH_LIST_DCE110(_MASK) 276 }; 277 278 #define opp_regs(id)\ 279 [id] = {\ 280 OPP_DCE_110_REG_LIST(id),\ 281 } 282 283 static const struct dce_opp_registers opp_regs[] = { 284 opp_regs(0), 285 opp_regs(1), 286 opp_regs(2), 287 opp_regs(3), 288 opp_regs(4), 289 opp_regs(5) 290 }; 291 292 static const struct dce_opp_shift opp_shift = { 293 OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT) 294 }; 295 296 static const struct dce_opp_mask opp_mask = { 297 OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK) 298 }; 299 300 #define aux_engine_regs(id)\ 301 [id] = {\ 302 AUX_COMMON_REG_LIST(id), \ 303 .AUX_RESET_MASK = 0 \ 304 } 305 306 static const struct dce110_aux_registers aux_engine_regs[] = { 307 aux_engine_regs(0), 308 aux_engine_regs(1), 309 aux_engine_regs(2), 310 aux_engine_regs(3), 311 aux_engine_regs(4), 312 aux_engine_regs(5) 313 }; 314 315 #define audio_regs(id)\ 316 [id] = {\ 317 AUD_COMMON_REG_LIST(id)\ 318 } 319 320 static const struct dce_audio_registers audio_regs[] = { 321 audio_regs(0), 322 audio_regs(1), 323 audio_regs(2), 324 audio_regs(3), 325 audio_regs(4), 326 audio_regs(5), 327 audio_regs(6), 328 }; 329 330 static const struct dce_audio_shift audio_shift = { 331 AUD_COMMON_MASK_SH_LIST(__SHIFT) 332 }; 333 334 static const struct dce_audio_mask audio_mask = { 335 AUD_COMMON_MASK_SH_LIST(_MASK) 336 }; 337 338 /* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */ 339 340 341 #define clk_src_regs(id)\ 342 [id] = {\ 343 CS_COMMON_REG_LIST_DCE_100_110(id),\ 344 } 345 346 static const struct dce110_clk_src_regs clk_src_regs[] = { 347 clk_src_regs(0), 348 clk_src_regs(1), 349 clk_src_regs(2) 350 }; 351 352 static const struct dce110_clk_src_shift cs_shift = { 353 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 354 }; 355 356 static const struct dce110_clk_src_mask cs_mask = { 357 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 358 }; 359 360 static const struct bios_registers bios_regs = { 361 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 362 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 363 }; 364 365 static const struct resource_caps carrizo_resource_cap = { 366 .num_timing_generator = 3, 367 .num_video_plane = 1, 368 .num_audio = 3, 369 .num_stream_encoder = 3, 370 .num_pll = 2, 371 .num_ddc = 3, 372 }; 373 374 static const struct resource_caps stoney_resource_cap = { 375 .num_timing_generator = 2, 376 .num_video_plane = 1, 377 .num_audio = 3, 378 .num_stream_encoder = 3, 379 .num_pll = 2, 380 .num_ddc = 3, 381 }; 382 383 static const struct dc_plane_cap plane_cap = { 384 .type = DC_PLANE_TYPE_DCE_RGB, 385 .blends_with_below = true, 386 .blends_with_above = true, 387 .per_pixel_alpha = 1, 388 389 .pixel_format_support = { 390 .argb8888 = true, 391 .nv12 = false, 392 .fp16 = false 393 }, 394 395 .max_upscale_factor = { 396 .argb8888 = 16000, 397 .nv12 = 1, 398 .fp16 = 1 399 }, 400 401 .max_downscale_factor = { 402 .argb8888 = 250, 403 .nv12 = 1, 404 .fp16 = 1 405 } 406 }; 407 408 static const struct dc_plane_cap underlay_plane_cap = { 409 .type = DC_PLANE_TYPE_DCE_UNDERLAY, 410 .blends_with_above = true, 411 .per_pixel_alpha = 1, 412 413 .pixel_format_support = { 414 .argb8888 = false, 415 .nv12 = true, 416 .fp16 = false 417 }, 418 419 .max_upscale_factor = { 420 .argb8888 = 1, 421 .nv12 = 16000, 422 .fp16 = 1 423 }, 424 425 .max_downscale_factor = { 426 .argb8888 = 1, 427 .nv12 = 250, 428 .fp16 = 1 429 } 430 }; 431 432 #define CTX ctx 433 #define REG(reg) mm ## reg 434 435 #ifndef mmCC_DC_HDMI_STRAPS 436 #define mmCC_DC_HDMI_STRAPS 0x4819 437 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 438 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 439 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 440 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 441 #endif 442 443 static void read_dce_straps( 444 struct dc_context *ctx, 445 struct resource_straps *straps) 446 { 447 REG_GET_2(CC_DC_HDMI_STRAPS, 448 HDMI_DISABLE, &straps->hdmi_disable, 449 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 450 451 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 452 } 453 454 static struct audio *create_audio( 455 struct dc_context *ctx, unsigned int inst) 456 { 457 return dce_audio_create(ctx, inst, 458 &audio_regs[inst], &audio_shift, &audio_mask); 459 } 460 461 static struct timing_generator *dce110_timing_generator_create( 462 struct dc_context *ctx, 463 uint32_t instance, 464 const struct dce110_timing_generator_offsets *offsets) 465 { 466 struct dce110_timing_generator *tg110 = 467 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 468 469 if (!tg110) 470 return NULL; 471 472 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 473 return &tg110->base; 474 } 475 476 static struct stream_encoder *dce110_stream_encoder_create( 477 enum engine_id eng_id, 478 struct dc_context *ctx) 479 { 480 struct dce110_stream_encoder *enc110 = 481 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 482 483 if (!enc110) 484 return NULL; 485 486 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 487 &stream_enc_regs[eng_id], 488 &se_shift, &se_mask); 489 return &enc110->base; 490 } 491 492 #define SRII(reg_name, block, id)\ 493 .reg_name[id] = mm ## block ## id ## _ ## reg_name 494 495 static const struct dce_hwseq_registers hwseq_stoney_reg = { 496 HWSEQ_ST_REG_LIST() 497 }; 498 499 static const struct dce_hwseq_registers hwseq_cz_reg = { 500 HWSEQ_CZ_REG_LIST() 501 }; 502 503 static const struct dce_hwseq_shift hwseq_shift = { 504 HWSEQ_DCE11_MASK_SH_LIST(__SHIFT), 505 }; 506 507 static const struct dce_hwseq_mask hwseq_mask = { 508 HWSEQ_DCE11_MASK_SH_LIST(_MASK), 509 }; 510 511 static struct dce_hwseq *dce110_hwseq_create( 512 struct dc_context *ctx) 513 { 514 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 515 516 if (hws) { 517 hws->ctx = ctx; 518 hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ? 519 &hwseq_stoney_reg : &hwseq_cz_reg; 520 hws->shifts = &hwseq_shift; 521 hws->masks = &hwseq_mask; 522 hws->wa.blnd_crtc_trigger = true; 523 } 524 return hws; 525 } 526 527 static const struct resource_create_funcs res_create_funcs = { 528 .read_dce_straps = read_dce_straps, 529 .create_audio = create_audio, 530 .create_stream_encoder = dce110_stream_encoder_create, 531 .create_hwseq = dce110_hwseq_create, 532 }; 533 534 #define mi_inst_regs(id) { \ 535 MI_DCE11_REG_LIST(id), \ 536 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 537 } 538 static const struct dce_mem_input_registers mi_regs[] = { 539 mi_inst_regs(0), 540 mi_inst_regs(1), 541 mi_inst_regs(2), 542 }; 543 544 static const struct dce_mem_input_shift mi_shifts = { 545 MI_DCE11_MASK_SH_LIST(__SHIFT), 546 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 547 }; 548 549 static const struct dce_mem_input_mask mi_masks = { 550 MI_DCE11_MASK_SH_LIST(_MASK), 551 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 552 }; 553 554 555 static struct mem_input *dce110_mem_input_create( 556 struct dc_context *ctx, 557 uint32_t inst) 558 { 559 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 560 GFP_KERNEL); 561 562 if (!dce_mi) { 563 BREAK_TO_DEBUGGER(); 564 return NULL; 565 } 566 567 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 568 dce_mi->wa.single_head_rdreq_dmif_limit = 3; 569 return &dce_mi->base; 570 } 571 572 static void dce110_transform_destroy(struct transform **xfm) 573 { 574 kfree(TO_DCE_TRANSFORM(*xfm)); 575 *xfm = NULL; 576 } 577 578 static struct transform *dce110_transform_create( 579 struct dc_context *ctx, 580 uint32_t inst) 581 { 582 struct dce_transform *transform = 583 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 584 585 if (!transform) 586 return NULL; 587 588 dce_transform_construct(transform, ctx, inst, 589 &xfm_regs[inst], &xfm_shift, &xfm_mask); 590 return &transform->base; 591 } 592 593 static struct input_pixel_processor *dce110_ipp_create( 594 struct dc_context *ctx, uint32_t inst) 595 { 596 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 597 598 if (!ipp) { 599 BREAK_TO_DEBUGGER(); 600 return NULL; 601 } 602 603 dce_ipp_construct(ipp, ctx, inst, 604 &ipp_regs[inst], &ipp_shift, &ipp_mask); 605 return &ipp->base; 606 } 607 608 static const struct encoder_feature_support link_enc_feature = { 609 .max_hdmi_deep_color = COLOR_DEPTH_121212, 610 .max_hdmi_pixel_clock = 300000, 611 .flags.bits.IS_HBR2_CAPABLE = true, 612 .flags.bits.IS_TPS3_CAPABLE = true 613 }; 614 615 static struct link_encoder *dce110_link_encoder_create( 616 const struct encoder_init_data *enc_init_data) 617 { 618 struct dce110_link_encoder *enc110 = 619 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 620 621 if (!enc110) 622 return NULL; 623 624 dce110_link_encoder_construct(enc110, 625 enc_init_data, 626 &link_enc_feature, 627 &link_enc_regs[enc_init_data->transmitter], 628 &link_enc_aux_regs[enc_init_data->channel - 1], 629 &link_enc_hpd_regs[enc_init_data->hpd_source]); 630 return &enc110->base; 631 } 632 633 static struct output_pixel_processor *dce110_opp_create( 634 struct dc_context *ctx, 635 uint32_t inst) 636 { 637 struct dce110_opp *opp = 638 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 639 640 if (!opp) 641 return NULL; 642 643 dce110_opp_construct(opp, 644 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 645 return &opp->base; 646 } 647 648 struct dce_aux *dce110_aux_engine_create( 649 struct dc_context *ctx, 650 uint32_t inst) 651 { 652 struct aux_engine_dce110 *aux_engine = 653 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 654 655 if (!aux_engine) 656 return NULL; 657 658 dce110_aux_engine_construct(aux_engine, ctx, inst, 659 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 660 &aux_engine_regs[inst]); 661 662 return &aux_engine->base; 663 } 664 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 665 666 static const struct dce_i2c_registers i2c_hw_regs[] = { 667 i2c_inst_regs(1), 668 i2c_inst_regs(2), 669 i2c_inst_regs(3), 670 i2c_inst_regs(4), 671 i2c_inst_regs(5), 672 i2c_inst_regs(6), 673 }; 674 675 static const struct dce_i2c_shift i2c_shifts = { 676 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 677 }; 678 679 static const struct dce_i2c_mask i2c_masks = { 680 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 681 }; 682 683 struct dce_i2c_hw *dce110_i2c_hw_create( 684 struct dc_context *ctx, 685 uint32_t inst) 686 { 687 struct dce_i2c_hw *dce_i2c_hw = 688 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 689 690 if (!dce_i2c_hw) 691 return NULL; 692 693 dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst, 694 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 695 696 return dce_i2c_hw; 697 } 698 struct clock_source *dce110_clock_source_create( 699 struct dc_context *ctx, 700 struct dc_bios *bios, 701 enum clock_source_id id, 702 const struct dce110_clk_src_regs *regs, 703 bool dp_clk_src) 704 { 705 struct dce110_clk_src *clk_src = 706 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 707 708 if (!clk_src) 709 return NULL; 710 711 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 712 regs, &cs_shift, &cs_mask)) { 713 clk_src->base.dp_clk_src = dp_clk_src; 714 return &clk_src->base; 715 } 716 717 kfree(clk_src); 718 BREAK_TO_DEBUGGER(); 719 return NULL; 720 } 721 722 void dce110_clock_source_destroy(struct clock_source **clk_src) 723 { 724 struct dce110_clk_src *dce110_clk_src; 725 726 if (!clk_src) 727 return; 728 729 dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src); 730 731 kfree(dce110_clk_src->dp_ss_params); 732 kfree(dce110_clk_src->hdmi_ss_params); 733 kfree(dce110_clk_src->dvi_ss_params); 734 735 kfree(dce110_clk_src); 736 *clk_src = NULL; 737 } 738 739 static void destruct(struct dce110_resource_pool *pool) 740 { 741 unsigned int i; 742 743 for (i = 0; i < pool->base.pipe_count; i++) { 744 if (pool->base.opps[i] != NULL) 745 dce110_opp_destroy(&pool->base.opps[i]); 746 747 if (pool->base.transforms[i] != NULL) 748 dce110_transform_destroy(&pool->base.transforms[i]); 749 750 if (pool->base.ipps[i] != NULL) 751 dce_ipp_destroy(&pool->base.ipps[i]); 752 753 if (pool->base.mis[i] != NULL) { 754 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 755 pool->base.mis[i] = NULL; 756 } 757 758 if (pool->base.timing_generators[i] != NULL) { 759 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 760 pool->base.timing_generators[i] = NULL; 761 } 762 } 763 764 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 765 if (pool->base.engines[i] != NULL) 766 dce110_engine_destroy(&pool->base.engines[i]); 767 if (pool->base.hw_i2cs[i] != NULL) { 768 kfree(pool->base.hw_i2cs[i]); 769 pool->base.hw_i2cs[i] = NULL; 770 } 771 if (pool->base.sw_i2cs[i] != NULL) { 772 kfree(pool->base.sw_i2cs[i]); 773 pool->base.sw_i2cs[i] = NULL; 774 } 775 } 776 777 for (i = 0; i < pool->base.stream_enc_count; i++) { 778 if (pool->base.stream_enc[i] != NULL) 779 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 780 } 781 782 for (i = 0; i < pool->base.clk_src_count; i++) { 783 if (pool->base.clock_sources[i] != NULL) { 784 dce110_clock_source_destroy(&pool->base.clock_sources[i]); 785 } 786 } 787 788 if (pool->base.dp_clock_source != NULL) 789 dce110_clock_source_destroy(&pool->base.dp_clock_source); 790 791 for (i = 0; i < pool->base.audio_count; i++) { 792 if (pool->base.audios[i] != NULL) { 793 dce_aud_destroy(&pool->base.audios[i]); 794 } 795 } 796 797 if (pool->base.abm != NULL) 798 dce_abm_destroy(&pool->base.abm); 799 800 if (pool->base.dmcu != NULL) 801 dce_dmcu_destroy(&pool->base.dmcu); 802 803 if (pool->base.irqs != NULL) { 804 dal_irq_service_destroy(&pool->base.irqs); 805 } 806 } 807 808 809 static void get_pixel_clock_parameters( 810 const struct pipe_ctx *pipe_ctx, 811 struct pixel_clk_params *pixel_clk_params) 812 { 813 const struct dc_stream_state *stream = pipe_ctx->stream; 814 815 /*TODO: is this halved for YCbCr 420? in that case we might want to move 816 * the pixel clock normalization for hdmi up to here instead of doing it 817 * in pll_adjust_pix_clk 818 */ 819 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 820 pixel_clk_params->encoder_object_id = stream->link->link_enc->id; 821 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 822 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 823 /* TODO: un-hardcode*/ 824 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 825 LINK_RATE_REF_FREQ_IN_KHZ; 826 pixel_clk_params->flags.ENABLE_SS = 0; 827 pixel_clk_params->color_depth = 828 stream->timing.display_color_depth; 829 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 830 pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding == 831 PIXEL_ENCODING_YCBCR420); 832 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 833 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) { 834 pixel_clk_params->color_depth = COLOR_DEPTH_888; 835 } 836 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 837 pixel_clk_params->requested_pix_clk_100hz = pixel_clk_params->requested_pix_clk_100hz / 2; 838 } 839 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 840 pixel_clk_params->requested_pix_clk_100hz *= 2; 841 842 } 843 844 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 845 { 846 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 847 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 848 pipe_ctx->clock_source, 849 &pipe_ctx->stream_res.pix_clk_params, 850 &pipe_ctx->pll_settings); 851 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 852 &pipe_ctx->stream->bit_depth_params); 853 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 854 } 855 856 static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx) 857 { 858 if (pipe_ctx->pipe_idx != underlay_idx) 859 return true; 860 if (!pipe_ctx->plane_state) 861 return false; 862 if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 863 return false; 864 return true; 865 } 866 867 static enum dc_status build_mapped_resource( 868 const struct dc *dc, 869 struct dc_state *context, 870 struct dc_stream_state *stream) 871 { 872 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 873 874 if (!pipe_ctx) 875 return DC_ERROR_UNEXPECTED; 876 877 if (!is_surface_pixel_format_supported(pipe_ctx, 878 dc->res_pool->underlay_pipe_index)) 879 return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; 880 881 dce110_resource_build_pipe_hw_param(pipe_ctx); 882 883 /* TODO: validate audio ASIC caps, encoder */ 884 885 resource_build_info_frame(pipe_ctx); 886 887 return DC_OK; 888 } 889 890 static bool dce110_validate_bandwidth( 891 struct dc *dc, 892 struct dc_state *context, 893 bool fast_validate) 894 { 895 bool result = false; 896 897 DC_LOG_BANDWIDTH_CALCS( 898 "%s: start", 899 __func__); 900 901 if (bw_calcs( 902 dc->ctx, 903 dc->bw_dceip, 904 dc->bw_vbios, 905 context->res_ctx.pipe_ctx, 906 dc->res_pool->pipe_count, 907 &context->bw_ctx.bw.dce)) 908 result = true; 909 910 if (!result) 911 DC_LOG_BANDWIDTH_VALIDATION("%s: %dx%d@%d Bandwidth validation failed!\n", 912 __func__, 913 context->streams[0]->timing.h_addressable, 914 context->streams[0]->timing.v_addressable, 915 context->streams[0]->timing.pix_clk_100hz / 10); 916 917 if (memcmp(&dc->current_state->bw_ctx.bw.dce, 918 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { 919 920 DC_LOG_BANDWIDTH_CALCS( 921 "%s: finish,\n" 922 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 923 "stutMark_b: %d stutMark_a: %d\n" 924 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 925 "stutMark_b: %d stutMark_a: %d\n" 926 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 927 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n" 928 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" 929 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n" 930 , 931 __func__, 932 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark, 933 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark, 934 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, 935 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, 936 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark, 937 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark, 938 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark, 939 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark, 940 context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark, 941 context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark, 942 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark, 943 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark, 944 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark, 945 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark, 946 context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark, 947 context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark, 948 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark, 949 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark, 950 context->bw_ctx.bw.dce.stutter_mode_enable, 951 context->bw_ctx.bw.dce.cpuc_state_change_enable, 952 context->bw_ctx.bw.dce.cpup_state_change_enable, 953 context->bw_ctx.bw.dce.nbp_state_change_enable, 954 context->bw_ctx.bw.dce.all_displays_in_sync, 955 context->bw_ctx.bw.dce.dispclk_khz, 956 context->bw_ctx.bw.dce.sclk_khz, 957 context->bw_ctx.bw.dce.sclk_deep_sleep_khz, 958 context->bw_ctx.bw.dce.yclk_khz, 959 context->bw_ctx.bw.dce.blackout_recovery_time_us); 960 } 961 return result; 962 } 963 964 enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state, 965 struct dc_caps *caps) 966 { 967 if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) || 968 ((plane_state->dst_rect.height * 2) < plane_state->src_rect.height)) 969 return DC_FAIL_SURFACE_VALIDATE; 970 971 return DC_OK; 972 } 973 974 static bool dce110_validate_surface_sets( 975 struct dc_state *context) 976 { 977 int i, j; 978 979 for (i = 0; i < context->stream_count; i++) { 980 if (context->stream_status[i].plane_count == 0) 981 continue; 982 983 if (context->stream_status[i].plane_count > 2) 984 return false; 985 986 for (j = 0; j < context->stream_status[i].plane_count; j++) { 987 struct dc_plane_state *plane = 988 context->stream_status[i].plane_states[j]; 989 990 /* underlay validation */ 991 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 992 993 if ((plane->src_rect.width > 1920 || 994 plane->src_rect.height > 1080)) 995 return false; 996 997 /* we don't have the logic to support underlay 998 * only yet so block the use case where we get 999 * NV12 plane as top layer 1000 */ 1001 if (j == 0) 1002 return false; 1003 1004 /* irrespective of plane format, 1005 * stream should be RGB encoded 1006 */ 1007 if (context->streams[i]->timing.pixel_encoding 1008 != PIXEL_ENCODING_RGB) 1009 return false; 1010 1011 } 1012 1013 } 1014 } 1015 1016 return true; 1017 } 1018 1019 enum dc_status dce110_validate_global( 1020 struct dc *dc, 1021 struct dc_state *context) 1022 { 1023 if (!dce110_validate_surface_sets(context)) 1024 return DC_FAIL_SURFACE_VALIDATE; 1025 1026 return DC_OK; 1027 } 1028 1029 static enum dc_status dce110_add_stream_to_ctx( 1030 struct dc *dc, 1031 struct dc_state *new_ctx, 1032 struct dc_stream_state *dc_stream) 1033 { 1034 enum dc_status result = DC_ERROR_UNEXPECTED; 1035 1036 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1037 1038 if (result == DC_OK) 1039 result = resource_map_clock_resources(dc, new_ctx, dc_stream); 1040 1041 1042 if (result == DC_OK) 1043 result = build_mapped_resource(dc, new_ctx, dc_stream); 1044 1045 return result; 1046 } 1047 1048 static struct pipe_ctx *dce110_acquire_underlay( 1049 struct dc_state *context, 1050 const struct resource_pool *pool, 1051 struct dc_stream_state *stream) 1052 { 1053 struct dc *dc = stream->ctx->dc; 1054 struct resource_context *res_ctx = &context->res_ctx; 1055 unsigned int underlay_idx = pool->underlay_pipe_index; 1056 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; 1057 1058 if (res_ctx->pipe_ctx[underlay_idx].stream) 1059 return NULL; 1060 1061 pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx]; 1062 pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; 1063 /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/ 1064 pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; 1065 pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; 1066 pipe_ctx->pipe_idx = underlay_idx; 1067 1068 pipe_ctx->stream = stream; 1069 1070 if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) { 1071 struct tg_color black_color = {0}; 1072 struct dc_bios *dcb = dc->ctx->dc_bios; 1073 1074 dc->hwss.enable_display_power_gating( 1075 dc, 1076 pipe_ctx->stream_res.tg->inst, 1077 dcb, PIPE_GATING_CONTROL_DISABLE); 1078 1079 /* 1080 * This is for powering on underlay, so crtc does not 1081 * need to be enabled 1082 */ 1083 1084 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg, 1085 &stream->timing, 1086 0, 1087 0, 1088 0, 1089 0, 1090 pipe_ctx->stream->signal, 1091 false); 1092 1093 pipe_ctx->stream_res.tg->funcs->enable_advanced_request( 1094 pipe_ctx->stream_res.tg, 1095 true, 1096 &stream->timing); 1097 1098 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi, 1099 stream->timing.h_total, 1100 stream->timing.v_total, 1101 stream->timing.pix_clk_100hz / 10, 1102 context->stream_count); 1103 1104 color_space_to_black_color(dc, 1105 COLOR_SPACE_YCBCR601, &black_color); 1106 pipe_ctx->stream_res.tg->funcs->set_blank_color( 1107 pipe_ctx->stream_res.tg, 1108 &black_color); 1109 } 1110 1111 return pipe_ctx; 1112 } 1113 1114 static void dce110_destroy_resource_pool(struct resource_pool **pool) 1115 { 1116 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 1117 1118 destruct(dce110_pool); 1119 kfree(dce110_pool); 1120 *pool = NULL; 1121 } 1122 1123 struct stream_encoder *dce110_find_first_free_match_stream_enc_for_link( 1124 struct resource_context *res_ctx, 1125 const struct resource_pool *pool, 1126 struct dc_stream_state *stream) 1127 { 1128 int i; 1129 int j = -1; 1130 struct dc_link *link = stream->link; 1131 1132 for (i = 0; i < pool->stream_enc_count; i++) { 1133 if (!res_ctx->is_stream_enc_acquired[i] && 1134 pool->stream_enc[i]) { 1135 /* Store first available for MST second display 1136 * in daisy chain use case 1137 */ 1138 j = i; 1139 if (pool->stream_enc[i]->id == 1140 link->link_enc->preferred_engine) 1141 return pool->stream_enc[i]; 1142 } 1143 } 1144 1145 /* 1146 * For CZ and later, we can allow DIG FE and BE to differ for all display types 1147 */ 1148 1149 if (j >= 0) 1150 return pool->stream_enc[j]; 1151 1152 return NULL; 1153 } 1154 1155 1156 static const struct resource_funcs dce110_res_pool_funcs = { 1157 .destroy = dce110_destroy_resource_pool, 1158 .link_enc_create = dce110_link_encoder_create, 1159 .validate_bandwidth = dce110_validate_bandwidth, 1160 .validate_plane = dce110_validate_plane, 1161 .acquire_idle_pipe_for_layer = dce110_acquire_underlay, 1162 .add_stream_to_ctx = dce110_add_stream_to_ctx, 1163 .validate_global = dce110_validate_global, 1164 .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link 1165 }; 1166 1167 static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) 1168 { 1169 struct dce110_timing_generator *dce110_tgv = kzalloc(sizeof(*dce110_tgv), 1170 GFP_KERNEL); 1171 struct dce_transform *dce110_xfmv = kzalloc(sizeof(*dce110_xfmv), 1172 GFP_KERNEL); 1173 struct dce_mem_input *dce110_miv = kzalloc(sizeof(*dce110_miv), 1174 GFP_KERNEL); 1175 struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv), 1176 GFP_KERNEL); 1177 1178 if (!dce110_tgv || !dce110_xfmv || !dce110_miv || !dce110_oppv) { 1179 kfree(dce110_tgv); 1180 kfree(dce110_xfmv); 1181 kfree(dce110_miv); 1182 kfree(dce110_oppv); 1183 return false; 1184 } 1185 1186 dce110_opp_v_construct(dce110_oppv, ctx); 1187 1188 dce110_timing_generator_v_construct(dce110_tgv, ctx); 1189 dce110_mem_input_v_construct(dce110_miv, ctx); 1190 dce110_transform_v_construct(dce110_xfmv, ctx); 1191 1192 pool->opps[pool->pipe_count] = &dce110_oppv->base; 1193 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; 1194 pool->mis[pool->pipe_count] = &dce110_miv->base; 1195 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; 1196 pool->pipe_count++; 1197 1198 /* update the public caps to indicate an underlay is available */ 1199 ctx->dc->caps.max_slave_planes = 1; 1200 ctx->dc->caps.max_slave_planes = 1; 1201 1202 return true; 1203 } 1204 1205 static void bw_calcs_data_update_from_pplib(struct dc *dc) 1206 { 1207 struct dm_pp_clock_levels clks = {0}; 1208 1209 /*do system clock*/ 1210 dm_pp_get_clock_levels_by_type( 1211 dc->ctx, 1212 DM_PP_CLOCK_TYPE_ENGINE_CLK, 1213 &clks); 1214 /* convert all the clock fro kHz to fix point mHz */ 1215 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 1216 clks.clocks_in_khz[clks.num_levels-1], 1000); 1217 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 1218 clks.clocks_in_khz[clks.num_levels/8], 1000); 1219 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 1220 clks.clocks_in_khz[clks.num_levels*2/8], 1000); 1221 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 1222 clks.clocks_in_khz[clks.num_levels*3/8], 1000); 1223 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 1224 clks.clocks_in_khz[clks.num_levels*4/8], 1000); 1225 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 1226 clks.clocks_in_khz[clks.num_levels*5/8], 1000); 1227 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1228 clks.clocks_in_khz[clks.num_levels*6/8], 1000); 1229 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1230 clks.clocks_in_khz[0], 1000); 1231 dc->sclk_lvls = clks; 1232 1233 /*do display clock*/ 1234 dm_pp_get_clock_levels_by_type( 1235 dc->ctx, 1236 DM_PP_CLOCK_TYPE_DISPLAY_CLK, 1237 &clks); 1238 dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed( 1239 clks.clocks_in_khz[clks.num_levels-1], 1000); 1240 dc->bw_vbios->mid_voltage_max_dispclk = bw_frc_to_fixed( 1241 clks.clocks_in_khz[clks.num_levels>>1], 1000); 1242 dc->bw_vbios->low_voltage_max_dispclk = bw_frc_to_fixed( 1243 clks.clocks_in_khz[0], 1000); 1244 1245 /*do memory clock*/ 1246 dm_pp_get_clock_levels_by_type( 1247 dc->ctx, 1248 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1249 &clks); 1250 1251 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1252 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER_CZ, 1000); 1253 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1254 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ, 1255 1000); 1256 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1257 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER_CZ, 1258 1000); 1259 } 1260 1261 const struct resource_caps *dce110_resource_cap( 1262 struct hw_asic_id *asic_id) 1263 { 1264 if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev)) 1265 return &stoney_resource_cap; 1266 else 1267 return &carrizo_resource_cap; 1268 } 1269 1270 static bool construct( 1271 uint8_t num_virtual_links, 1272 struct dc *dc, 1273 struct dce110_resource_pool *pool, 1274 struct hw_asic_id asic_id) 1275 { 1276 unsigned int i; 1277 struct dc_context *ctx = dc->ctx; 1278 struct dc_bios *bp; 1279 1280 ctx->dc_bios->regs = &bios_regs; 1281 1282 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); 1283 pool->base.funcs = &dce110_res_pool_funcs; 1284 1285 /************************************************* 1286 * Resource + asic cap harcoding * 1287 *************************************************/ 1288 1289 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1290 pool->base.underlay_pipe_index = pool->base.pipe_count; 1291 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1292 dc->caps.max_downscale_ratio = 150; 1293 dc->caps.i2c_speed_in_khz = 100; 1294 dc->caps.max_cursor_size = 128; 1295 dc->caps.is_apu = true; 1296 1297 /************************************************* 1298 * Create resources * 1299 *************************************************/ 1300 1301 bp = ctx->dc_bios; 1302 1303 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 1304 pool->base.dp_clock_source = 1305 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1306 1307 pool->base.clock_sources[0] = 1308 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, 1309 &clk_src_regs[0], false); 1310 pool->base.clock_sources[1] = 1311 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, 1312 &clk_src_regs[1], false); 1313 1314 pool->base.clk_src_count = 2; 1315 1316 /* TODO: find out if CZ support 3 PLLs */ 1317 } 1318 1319 if (pool->base.dp_clock_source == NULL) { 1320 dm_error("DC: failed to create dp clock source!\n"); 1321 BREAK_TO_DEBUGGER(); 1322 goto res_create_fail; 1323 } 1324 1325 for (i = 0; i < pool->base.clk_src_count; i++) { 1326 if (pool->base.clock_sources[i] == NULL) { 1327 dm_error("DC: failed to create clock sources!\n"); 1328 BREAK_TO_DEBUGGER(); 1329 goto res_create_fail; 1330 } 1331 } 1332 1333 pool->base.dmcu = dce_dmcu_create(ctx, 1334 &dmcu_regs, 1335 &dmcu_shift, 1336 &dmcu_mask); 1337 if (pool->base.dmcu == NULL) { 1338 dm_error("DC: failed to create dmcu!\n"); 1339 BREAK_TO_DEBUGGER(); 1340 goto res_create_fail; 1341 } 1342 1343 pool->base.abm = dce_abm_create(ctx, 1344 &abm_regs, 1345 &abm_shift, 1346 &abm_mask); 1347 if (pool->base.abm == NULL) { 1348 dm_error("DC: failed to create abm!\n"); 1349 BREAK_TO_DEBUGGER(); 1350 goto res_create_fail; 1351 } 1352 1353 { 1354 struct irq_service_init_data init_data; 1355 init_data.ctx = dc->ctx; 1356 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 1357 if (!pool->base.irqs) 1358 goto res_create_fail; 1359 } 1360 1361 for (i = 0; i < pool->base.pipe_count; i++) { 1362 pool->base.timing_generators[i] = dce110_timing_generator_create( 1363 ctx, i, &dce110_tg_offsets[i]); 1364 if (pool->base.timing_generators[i] == NULL) { 1365 BREAK_TO_DEBUGGER(); 1366 dm_error("DC: failed to create tg!\n"); 1367 goto res_create_fail; 1368 } 1369 1370 pool->base.mis[i] = dce110_mem_input_create(ctx, i); 1371 if (pool->base.mis[i] == NULL) { 1372 BREAK_TO_DEBUGGER(); 1373 dm_error( 1374 "DC: failed to create memory input!\n"); 1375 goto res_create_fail; 1376 } 1377 1378 pool->base.ipps[i] = dce110_ipp_create(ctx, i); 1379 if (pool->base.ipps[i] == NULL) { 1380 BREAK_TO_DEBUGGER(); 1381 dm_error( 1382 "DC: failed to create input pixel processor!\n"); 1383 goto res_create_fail; 1384 } 1385 1386 pool->base.transforms[i] = dce110_transform_create(ctx, i); 1387 if (pool->base.transforms[i] == NULL) { 1388 BREAK_TO_DEBUGGER(); 1389 dm_error( 1390 "DC: failed to create transform!\n"); 1391 goto res_create_fail; 1392 } 1393 1394 pool->base.opps[i] = dce110_opp_create(ctx, i); 1395 if (pool->base.opps[i] == NULL) { 1396 BREAK_TO_DEBUGGER(); 1397 dm_error( 1398 "DC: failed to create output pixel processor!\n"); 1399 goto res_create_fail; 1400 } 1401 } 1402 1403 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1404 pool->base.engines[i] = dce110_aux_engine_create(ctx, i); 1405 if (pool->base.engines[i] == NULL) { 1406 BREAK_TO_DEBUGGER(); 1407 dm_error( 1408 "DC:failed to create aux engine!!\n"); 1409 goto res_create_fail; 1410 } 1411 pool->base.hw_i2cs[i] = dce110_i2c_hw_create(ctx, i); 1412 if (pool->base.hw_i2cs[i] == NULL) { 1413 BREAK_TO_DEBUGGER(); 1414 dm_error( 1415 "DC:failed to create i2c engine!!\n"); 1416 goto res_create_fail; 1417 } 1418 pool->base.sw_i2cs[i] = NULL; 1419 } 1420 1421 if (dc->config.fbc_support) 1422 dc->fbc_compressor = dce110_compressor_create(ctx); 1423 1424 if (!underlay_create(ctx, &pool->base)) 1425 goto res_create_fail; 1426 1427 if (!resource_construct(num_virtual_links, dc, &pool->base, 1428 &res_create_funcs)) 1429 goto res_create_fail; 1430 1431 /* Create hardware sequencer */ 1432 dce110_hw_sequencer_construct(dc); 1433 1434 dc->caps.max_planes = pool->base.pipe_count; 1435 1436 for (i = 0; i < pool->base.underlay_pipe_index; ++i) 1437 dc->caps.planes[i] = plane_cap; 1438 1439 dc->caps.planes[pool->base.underlay_pipe_index] = underlay_plane_cap; 1440 1441 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1442 1443 bw_calcs_data_update_from_pplib(dc); 1444 1445 return true; 1446 1447 res_create_fail: 1448 destruct(pool); 1449 return false; 1450 } 1451 1452 struct resource_pool *dce110_create_resource_pool( 1453 uint8_t num_virtual_links, 1454 struct dc *dc, 1455 struct hw_asic_id asic_id) 1456 { 1457 struct dce110_resource_pool *pool = 1458 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1459 1460 if (!pool) 1461 return NULL; 1462 1463 if (construct(num_virtual_links, dc, pool, asic_id)) 1464 return &pool->base; 1465 1466 kfree(pool); 1467 BREAK_TO_DEBUGGER(); 1468 return NULL; 1469 } 1470