1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "link_encoder.h" 29 #include "stream_encoder.h" 30 31 #include "resource.h" 32 #include "dce110/dce110_resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dce/dce_audio.h" 35 #include "dce110/dce110_timing_generator.h" 36 #include "irq/dce110/irq_service_dce110.h" 37 #include "dce110/dce110_timing_generator_v.h" 38 #include "dce/dce_link_encoder.h" 39 #include "dce/dce_stream_encoder.h" 40 #include "dce/dce_mem_input.h" 41 #include "dce110/dce110_mem_input_v.h" 42 #include "dce/dce_ipp.h" 43 #include "dce/dce_transform.h" 44 #include "dce110/dce110_transform_v.h" 45 #include "dce/dce_opp.h" 46 #include "dce110/dce110_opp_v.h" 47 #include "dce/dce_clock_source.h" 48 #include "dce/dce_hwseq.h" 49 #include "dce110/dce110_hw_sequencer.h" 50 #include "dce/dce_aux.h" 51 #include "dce/dce_abm.h" 52 #include "dce/dce_dmcu.h" 53 #include "dce/dce_i2c.h" 54 #include "dce/dce_panel_cntl.h" 55 56 #define DC_LOGGER \ 57 dc->ctx->logger 58 59 #include "dce110/dce110_compressor.h" 60 61 #include "reg_helper.h" 62 63 #include "dce/dce_11_0_d.h" 64 #include "dce/dce_11_0_sh_mask.h" 65 66 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 67 #include "gmc/gmc_8_2_d.h" 68 #include "gmc/gmc_8_2_sh_mask.h" 69 #endif 70 71 #ifndef mmDP_DPHY_INTERNAL_CTRL 72 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 73 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 74 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 75 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 76 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 77 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 78 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 79 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 80 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 81 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 82 #endif 83 84 #ifndef mmBIOS_SCRATCH_2 85 #define mmBIOS_SCRATCH_2 0x05CB 86 #define mmBIOS_SCRATCH_3 0x05CC 87 #define mmBIOS_SCRATCH_6 0x05CF 88 #endif 89 90 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 91 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 92 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 93 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 94 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 95 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 96 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 97 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 98 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 99 #endif 100 101 #ifndef mmDP_DPHY_FAST_TRAINING 102 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 103 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 104 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 105 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 106 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 107 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 108 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 109 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 110 #endif 111 112 #ifndef DPHY_RX_FAST_TRAINING_CAPABLE 113 #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1 114 #endif 115 116 static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = { 117 { 118 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 119 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 120 }, 121 { 122 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 123 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 124 }, 125 { 126 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 127 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 128 }, 129 { 130 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 131 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 132 }, 133 { 134 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 135 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 136 }, 137 { 138 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 139 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 140 } 141 }; 142 143 /* set register offset */ 144 #define SR(reg_name)\ 145 .reg_name = mm ## reg_name 146 147 /* set register offset with instance */ 148 #define SRI(reg_name, block, id)\ 149 .reg_name = mm ## block ## id ## _ ## reg_name 150 151 static const struct dce_dmcu_registers dmcu_regs = { 152 DMCU_DCE110_COMMON_REG_LIST() 153 }; 154 155 static const struct dce_dmcu_shift dmcu_shift = { 156 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 157 }; 158 159 static const struct dce_dmcu_mask dmcu_mask = { 160 DMCU_MASK_SH_LIST_DCE110(_MASK) 161 }; 162 163 static const struct dce_abm_registers abm_regs = { 164 ABM_DCE110_COMMON_REG_LIST() 165 }; 166 167 static const struct dce_abm_shift abm_shift = { 168 ABM_MASK_SH_LIST_DCE110(__SHIFT) 169 }; 170 171 static const struct dce_abm_mask abm_mask = { 172 ABM_MASK_SH_LIST_DCE110(_MASK) 173 }; 174 175 #define ipp_regs(id)\ 176 [id] = {\ 177 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 178 } 179 180 static const struct dce_ipp_registers ipp_regs[] = { 181 ipp_regs(0), 182 ipp_regs(1), 183 ipp_regs(2) 184 }; 185 186 static const struct dce_ipp_shift ipp_shift = { 187 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 188 }; 189 190 static const struct dce_ipp_mask ipp_mask = { 191 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 192 }; 193 194 #define transform_regs(id)\ 195 [id] = {\ 196 XFM_COMMON_REG_LIST_DCE110(id)\ 197 } 198 199 static const struct dce_transform_registers xfm_regs[] = { 200 transform_regs(0), 201 transform_regs(1), 202 transform_regs(2) 203 }; 204 205 static const struct dce_transform_shift xfm_shift = { 206 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 207 }; 208 209 static const struct dce_transform_mask xfm_mask = { 210 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 211 }; 212 213 #define aux_regs(id)\ 214 [id] = {\ 215 AUX_REG_LIST(id)\ 216 } 217 218 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 219 aux_regs(0), 220 aux_regs(1), 221 aux_regs(2), 222 aux_regs(3), 223 aux_regs(4), 224 aux_regs(5) 225 }; 226 227 #define hpd_regs(id)\ 228 [id] = {\ 229 HPD_REG_LIST(id)\ 230 } 231 232 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 233 hpd_regs(0), 234 hpd_regs(1), 235 hpd_regs(2), 236 hpd_regs(3), 237 hpd_regs(4), 238 hpd_regs(5) 239 }; 240 241 242 #define link_regs(id)\ 243 [id] = {\ 244 LE_DCE110_REG_LIST(id)\ 245 } 246 247 static const struct dce110_link_enc_registers link_enc_regs[] = { 248 link_regs(0), 249 link_regs(1), 250 link_regs(2), 251 link_regs(3), 252 link_regs(4), 253 link_regs(5), 254 link_regs(6), 255 }; 256 257 #define stream_enc_regs(id)\ 258 [id] = {\ 259 SE_COMMON_REG_LIST(id),\ 260 .TMDS_CNTL = 0,\ 261 } 262 263 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 264 stream_enc_regs(0), 265 stream_enc_regs(1), 266 stream_enc_regs(2) 267 }; 268 269 static const struct dce_stream_encoder_shift se_shift = { 270 SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 271 }; 272 273 static const struct dce_stream_encoder_mask se_mask = { 274 SE_COMMON_MASK_SH_LIST_DCE110(_MASK) 275 }; 276 277 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 278 { DCE_PANEL_CNTL_REG_LIST() } 279 }; 280 281 static const struct dce_panel_cntl_shift panel_cntl_shift = { 282 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 283 }; 284 285 static const struct dce_panel_cntl_mask panel_cntl_mask = { 286 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 287 }; 288 289 static const struct dce110_aux_registers_shift aux_shift = { 290 DCE_AUX_MASK_SH_LIST(__SHIFT) 291 }; 292 293 static const struct dce110_aux_registers_mask aux_mask = { 294 DCE_AUX_MASK_SH_LIST(_MASK) 295 }; 296 297 #define opp_regs(id)\ 298 [id] = {\ 299 OPP_DCE_110_REG_LIST(id),\ 300 } 301 302 static const struct dce_opp_registers opp_regs[] = { 303 opp_regs(0), 304 opp_regs(1), 305 opp_regs(2), 306 opp_regs(3), 307 opp_regs(4), 308 opp_regs(5) 309 }; 310 311 static const struct dce_opp_shift opp_shift = { 312 OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT) 313 }; 314 315 static const struct dce_opp_mask opp_mask = { 316 OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK) 317 }; 318 319 #define aux_engine_regs(id)\ 320 [id] = {\ 321 AUX_COMMON_REG_LIST(id), \ 322 .AUX_RESET_MASK = 0 \ 323 } 324 325 static const struct dce110_aux_registers aux_engine_regs[] = { 326 aux_engine_regs(0), 327 aux_engine_regs(1), 328 aux_engine_regs(2), 329 aux_engine_regs(3), 330 aux_engine_regs(4), 331 aux_engine_regs(5) 332 }; 333 334 #define audio_regs(id)\ 335 [id] = {\ 336 AUD_COMMON_REG_LIST(id)\ 337 } 338 339 static const struct dce_audio_registers audio_regs[] = { 340 audio_regs(0), 341 audio_regs(1), 342 audio_regs(2), 343 audio_regs(3), 344 audio_regs(4), 345 audio_regs(5), 346 audio_regs(6), 347 }; 348 349 static const struct dce_audio_shift audio_shift = { 350 AUD_COMMON_MASK_SH_LIST(__SHIFT) 351 }; 352 353 static const struct dce_audio_mask audio_mask = { 354 AUD_COMMON_MASK_SH_LIST(_MASK) 355 }; 356 357 /* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */ 358 359 360 #define clk_src_regs(id)\ 361 [id] = {\ 362 CS_COMMON_REG_LIST_DCE_100_110(id),\ 363 } 364 365 static const struct dce110_clk_src_regs clk_src_regs[] = { 366 clk_src_regs(0), 367 clk_src_regs(1), 368 clk_src_regs(2) 369 }; 370 371 static const struct dce110_clk_src_shift cs_shift = { 372 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 373 }; 374 375 static const struct dce110_clk_src_mask cs_mask = { 376 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 377 }; 378 379 static const struct bios_registers bios_regs = { 380 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 381 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 382 }; 383 384 static const struct resource_caps carrizo_resource_cap = { 385 .num_timing_generator = 3, 386 .num_video_plane = 1, 387 .num_audio = 3, 388 .num_stream_encoder = 3, 389 .num_pll = 2, 390 .num_ddc = 3, 391 }; 392 393 static const struct resource_caps stoney_resource_cap = { 394 .num_timing_generator = 2, 395 .num_video_plane = 1, 396 .num_audio = 3, 397 .num_stream_encoder = 3, 398 .num_pll = 2, 399 .num_ddc = 3, 400 }; 401 402 static const struct dc_plane_cap plane_cap = { 403 .type = DC_PLANE_TYPE_DCE_RGB, 404 .blends_with_below = true, 405 .blends_with_above = true, 406 .per_pixel_alpha = 1, 407 408 .pixel_format_support = { 409 .argb8888 = true, 410 .nv12 = false, 411 .fp16 = true 412 }, 413 414 .max_upscale_factor = { 415 .argb8888 = 16000, 416 .nv12 = 1, 417 .fp16 = 1 418 }, 419 420 .max_downscale_factor = { 421 .argb8888 = 250, 422 .nv12 = 1, 423 .fp16 = 1 424 }, 425 64, 426 64 427 }; 428 429 static const struct dc_plane_cap underlay_plane_cap = { 430 .type = DC_PLANE_TYPE_DCE_UNDERLAY, 431 .blends_with_above = true, 432 .per_pixel_alpha = 1, 433 434 .pixel_format_support = { 435 .argb8888 = false, 436 .nv12 = true, 437 .fp16 = false 438 }, 439 440 .max_upscale_factor = { 441 .argb8888 = 1, 442 .nv12 = 16000, 443 .fp16 = 1 444 }, 445 446 .max_downscale_factor = { 447 .argb8888 = 1, 448 .nv12 = 250, 449 .fp16 = 1 450 }, 451 64, 452 64 453 }; 454 455 #define CTX ctx 456 #define REG(reg) mm ## reg 457 458 #ifndef mmCC_DC_HDMI_STRAPS 459 #define mmCC_DC_HDMI_STRAPS 0x4819 460 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 461 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 462 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 463 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 464 #endif 465 466 static int map_transmitter_id_to_phy_instance( 467 enum transmitter transmitter) 468 { 469 switch (transmitter) { 470 case TRANSMITTER_UNIPHY_A: 471 return 0; 472 case TRANSMITTER_UNIPHY_B: 473 return 1; 474 case TRANSMITTER_UNIPHY_C: 475 return 2; 476 case TRANSMITTER_UNIPHY_D: 477 return 3; 478 case TRANSMITTER_UNIPHY_E: 479 return 4; 480 case TRANSMITTER_UNIPHY_F: 481 return 5; 482 case TRANSMITTER_UNIPHY_G: 483 return 6; 484 default: 485 ASSERT(0); 486 return 0; 487 } 488 } 489 490 static void read_dce_straps( 491 struct dc_context *ctx, 492 struct resource_straps *straps) 493 { 494 REG_GET_2(CC_DC_HDMI_STRAPS, 495 HDMI_DISABLE, &straps->hdmi_disable, 496 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 497 498 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 499 } 500 501 static struct audio *create_audio( 502 struct dc_context *ctx, unsigned int inst) 503 { 504 return dce_audio_create(ctx, inst, 505 &audio_regs[inst], &audio_shift, &audio_mask); 506 } 507 508 static struct timing_generator *dce110_timing_generator_create( 509 struct dc_context *ctx, 510 uint32_t instance, 511 const struct dce110_timing_generator_offsets *offsets) 512 { 513 struct dce110_timing_generator *tg110 = 514 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 515 516 if (!tg110) 517 return NULL; 518 519 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 520 return &tg110->base; 521 } 522 523 static struct stream_encoder *dce110_stream_encoder_create( 524 enum engine_id eng_id, 525 struct dc_context *ctx) 526 { 527 struct dce110_stream_encoder *enc110 = 528 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 529 530 if (!enc110) 531 return NULL; 532 533 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 534 &stream_enc_regs[eng_id], 535 &se_shift, &se_mask); 536 return &enc110->base; 537 } 538 539 #define SRII(reg_name, block, id)\ 540 .reg_name[id] = mm ## block ## id ## _ ## reg_name 541 542 static const struct dce_hwseq_registers hwseq_stoney_reg = { 543 HWSEQ_ST_REG_LIST() 544 }; 545 546 static const struct dce_hwseq_registers hwseq_cz_reg = { 547 HWSEQ_CZ_REG_LIST() 548 }; 549 550 static const struct dce_hwseq_shift hwseq_shift = { 551 HWSEQ_DCE11_MASK_SH_LIST(__SHIFT), 552 }; 553 554 static const struct dce_hwseq_mask hwseq_mask = { 555 HWSEQ_DCE11_MASK_SH_LIST(_MASK), 556 }; 557 558 static struct dce_hwseq *dce110_hwseq_create( 559 struct dc_context *ctx) 560 { 561 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 562 563 if (hws) { 564 hws->ctx = ctx; 565 hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ? 566 &hwseq_stoney_reg : &hwseq_cz_reg; 567 hws->shifts = &hwseq_shift; 568 hws->masks = &hwseq_mask; 569 hws->wa.blnd_crtc_trigger = true; 570 } 571 return hws; 572 } 573 574 static const struct resource_create_funcs res_create_funcs = { 575 .read_dce_straps = read_dce_straps, 576 .create_audio = create_audio, 577 .create_stream_encoder = dce110_stream_encoder_create, 578 .create_hwseq = dce110_hwseq_create, 579 }; 580 581 #define mi_inst_regs(id) { \ 582 MI_DCE11_REG_LIST(id), \ 583 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 584 } 585 static const struct dce_mem_input_registers mi_regs[] = { 586 mi_inst_regs(0), 587 mi_inst_regs(1), 588 mi_inst_regs(2), 589 }; 590 591 static const struct dce_mem_input_shift mi_shifts = { 592 MI_DCE11_MASK_SH_LIST(__SHIFT), 593 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 594 }; 595 596 static const struct dce_mem_input_mask mi_masks = { 597 MI_DCE11_MASK_SH_LIST(_MASK), 598 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 599 }; 600 601 602 static struct mem_input *dce110_mem_input_create( 603 struct dc_context *ctx, 604 uint32_t inst) 605 { 606 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 607 GFP_KERNEL); 608 609 if (!dce_mi) { 610 BREAK_TO_DEBUGGER(); 611 return NULL; 612 } 613 614 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 615 dce_mi->wa.single_head_rdreq_dmif_limit = 3; 616 return &dce_mi->base; 617 } 618 619 static void dce110_transform_destroy(struct transform **xfm) 620 { 621 kfree(TO_DCE_TRANSFORM(*xfm)); 622 *xfm = NULL; 623 } 624 625 static struct transform *dce110_transform_create( 626 struct dc_context *ctx, 627 uint32_t inst) 628 { 629 struct dce_transform *transform = 630 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 631 632 if (!transform) 633 return NULL; 634 635 dce_transform_construct(transform, ctx, inst, 636 &xfm_regs[inst], &xfm_shift, &xfm_mask); 637 return &transform->base; 638 } 639 640 static struct input_pixel_processor *dce110_ipp_create( 641 struct dc_context *ctx, uint32_t inst) 642 { 643 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 644 645 if (!ipp) { 646 BREAK_TO_DEBUGGER(); 647 return NULL; 648 } 649 650 dce_ipp_construct(ipp, ctx, inst, 651 &ipp_regs[inst], &ipp_shift, &ipp_mask); 652 return &ipp->base; 653 } 654 655 static const struct encoder_feature_support link_enc_feature = { 656 .max_hdmi_deep_color = COLOR_DEPTH_121212, 657 .max_hdmi_pixel_clock = 300000, 658 .flags.bits.IS_HBR2_CAPABLE = true, 659 .flags.bits.IS_TPS3_CAPABLE = true 660 }; 661 662 static struct link_encoder *dce110_link_encoder_create( 663 const struct encoder_init_data *enc_init_data) 664 { 665 struct dce110_link_encoder *enc110 = 666 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 667 int link_regs_id; 668 669 if (!enc110) 670 return NULL; 671 672 link_regs_id = 673 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 674 675 dce110_link_encoder_construct(enc110, 676 enc_init_data, 677 &link_enc_feature, 678 &link_enc_regs[link_regs_id], 679 &link_enc_aux_regs[enc_init_data->channel - 1], 680 &link_enc_hpd_regs[enc_init_data->hpd_source]); 681 return &enc110->base; 682 } 683 684 static struct panel_cntl *dce110_panel_cntl_create(const struct panel_cntl_init_data *init_data) 685 { 686 struct dce_panel_cntl *panel_cntl = 687 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 688 689 if (!panel_cntl) 690 return NULL; 691 692 dce_panel_cntl_construct(panel_cntl, 693 init_data, 694 &panel_cntl_regs[init_data->inst], 695 &panel_cntl_shift, 696 &panel_cntl_mask); 697 698 return &panel_cntl->base; 699 } 700 701 static struct output_pixel_processor *dce110_opp_create( 702 struct dc_context *ctx, 703 uint32_t inst) 704 { 705 struct dce110_opp *opp = 706 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 707 708 if (!opp) 709 return NULL; 710 711 dce110_opp_construct(opp, 712 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 713 return &opp->base; 714 } 715 716 static struct dce_aux *dce110_aux_engine_create( 717 struct dc_context *ctx, 718 uint32_t inst) 719 { 720 struct aux_engine_dce110 *aux_engine = 721 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 722 723 if (!aux_engine) 724 return NULL; 725 726 dce110_aux_engine_construct(aux_engine, ctx, inst, 727 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 728 &aux_engine_regs[inst], 729 &aux_mask, 730 &aux_shift, 731 ctx->dc->caps.extended_aux_timeout_support); 732 733 return &aux_engine->base; 734 } 735 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 736 737 static const struct dce_i2c_registers i2c_hw_regs[] = { 738 i2c_inst_regs(1), 739 i2c_inst_regs(2), 740 i2c_inst_regs(3), 741 i2c_inst_regs(4), 742 i2c_inst_regs(5), 743 i2c_inst_regs(6), 744 }; 745 746 static const struct dce_i2c_shift i2c_shifts = { 747 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 748 }; 749 750 static const struct dce_i2c_mask i2c_masks = { 751 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 752 }; 753 754 static struct dce_i2c_hw *dce110_i2c_hw_create( 755 struct dc_context *ctx, 756 uint32_t inst) 757 { 758 struct dce_i2c_hw *dce_i2c_hw = 759 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 760 761 if (!dce_i2c_hw) 762 return NULL; 763 764 dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst, 765 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 766 767 return dce_i2c_hw; 768 } 769 static struct clock_source *dce110_clock_source_create( 770 struct dc_context *ctx, 771 struct dc_bios *bios, 772 enum clock_source_id id, 773 const struct dce110_clk_src_regs *regs, 774 bool dp_clk_src) 775 { 776 struct dce110_clk_src *clk_src = 777 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 778 779 if (!clk_src) 780 return NULL; 781 782 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 783 regs, &cs_shift, &cs_mask)) { 784 clk_src->base.dp_clk_src = dp_clk_src; 785 return &clk_src->base; 786 } 787 788 kfree(clk_src); 789 BREAK_TO_DEBUGGER(); 790 return NULL; 791 } 792 793 static void dce110_clock_source_destroy(struct clock_source **clk_src) 794 { 795 struct dce110_clk_src *dce110_clk_src; 796 797 if (!clk_src) 798 return; 799 800 dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src); 801 802 kfree(dce110_clk_src->dp_ss_params); 803 kfree(dce110_clk_src->hdmi_ss_params); 804 kfree(dce110_clk_src->dvi_ss_params); 805 806 kfree(dce110_clk_src); 807 *clk_src = NULL; 808 } 809 810 static void dce110_resource_destruct(struct dce110_resource_pool *pool) 811 { 812 unsigned int i; 813 814 for (i = 0; i < pool->base.pipe_count; i++) { 815 if (pool->base.opps[i] != NULL) 816 dce110_opp_destroy(&pool->base.opps[i]); 817 818 if (pool->base.transforms[i] != NULL) 819 dce110_transform_destroy(&pool->base.transforms[i]); 820 821 if (pool->base.ipps[i] != NULL) 822 dce_ipp_destroy(&pool->base.ipps[i]); 823 824 if (pool->base.mis[i] != NULL) { 825 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 826 pool->base.mis[i] = NULL; 827 } 828 829 if (pool->base.timing_generators[i] != NULL) { 830 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 831 pool->base.timing_generators[i] = NULL; 832 } 833 } 834 835 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 836 if (pool->base.engines[i] != NULL) 837 dce110_engine_destroy(&pool->base.engines[i]); 838 if (pool->base.hw_i2cs[i] != NULL) { 839 kfree(pool->base.hw_i2cs[i]); 840 pool->base.hw_i2cs[i] = NULL; 841 } 842 if (pool->base.sw_i2cs[i] != NULL) { 843 kfree(pool->base.sw_i2cs[i]); 844 pool->base.sw_i2cs[i] = NULL; 845 } 846 } 847 848 for (i = 0; i < pool->base.stream_enc_count; i++) { 849 if (pool->base.stream_enc[i] != NULL) 850 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 851 } 852 853 for (i = 0; i < pool->base.clk_src_count; i++) { 854 if (pool->base.clock_sources[i] != NULL) { 855 dce110_clock_source_destroy(&pool->base.clock_sources[i]); 856 } 857 } 858 859 if (pool->base.dp_clock_source != NULL) 860 dce110_clock_source_destroy(&pool->base.dp_clock_source); 861 862 for (i = 0; i < pool->base.audio_count; i++) { 863 if (pool->base.audios[i] != NULL) { 864 dce_aud_destroy(&pool->base.audios[i]); 865 } 866 } 867 868 if (pool->base.abm != NULL) 869 dce_abm_destroy(&pool->base.abm); 870 871 if (pool->base.dmcu != NULL) 872 dce_dmcu_destroy(&pool->base.dmcu); 873 874 if (pool->base.irqs != NULL) { 875 dal_irq_service_destroy(&pool->base.irqs); 876 } 877 } 878 879 880 static void get_pixel_clock_parameters( 881 const struct pipe_ctx *pipe_ctx, 882 struct pixel_clk_params *pixel_clk_params) 883 { 884 const struct dc_stream_state *stream = pipe_ctx->stream; 885 886 /*TODO: is this halved for YCbCr 420? in that case we might want to move 887 * the pixel clock normalization for hdmi up to here instead of doing it 888 * in pll_adjust_pix_clk 889 */ 890 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 891 pixel_clk_params->encoder_object_id = stream->link->link_enc->id; 892 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 893 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 894 /* TODO: un-hardcode*/ 895 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 896 LINK_RATE_REF_FREQ_IN_KHZ; 897 pixel_clk_params->flags.ENABLE_SS = 0; 898 pixel_clk_params->color_depth = 899 stream->timing.display_color_depth; 900 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 901 pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding == 902 PIXEL_ENCODING_YCBCR420); 903 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 904 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) { 905 pixel_clk_params->color_depth = COLOR_DEPTH_888; 906 } 907 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 908 pixel_clk_params->requested_pix_clk_100hz = pixel_clk_params->requested_pix_clk_100hz / 2; 909 } 910 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 911 pixel_clk_params->requested_pix_clk_100hz *= 2; 912 913 } 914 915 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 916 { 917 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 918 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 919 pipe_ctx->clock_source, 920 &pipe_ctx->stream_res.pix_clk_params, 921 &pipe_ctx->pll_settings); 922 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 923 &pipe_ctx->stream->bit_depth_params); 924 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 925 } 926 927 static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx) 928 { 929 if (pipe_ctx->pipe_idx != underlay_idx) 930 return true; 931 if (!pipe_ctx->plane_state) 932 return false; 933 if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 934 return false; 935 return true; 936 } 937 938 static enum dc_status build_mapped_resource( 939 const struct dc *dc, 940 struct dc_state *context, 941 struct dc_stream_state *stream) 942 { 943 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 944 945 if (!pipe_ctx) 946 return DC_ERROR_UNEXPECTED; 947 948 if (!is_surface_pixel_format_supported(pipe_ctx, 949 dc->res_pool->underlay_pipe_index)) 950 return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; 951 952 dce110_resource_build_pipe_hw_param(pipe_ctx); 953 954 /* TODO: validate audio ASIC caps, encoder */ 955 956 resource_build_info_frame(pipe_ctx); 957 958 return DC_OK; 959 } 960 961 static bool dce110_validate_bandwidth( 962 struct dc *dc, 963 struct dc_state *context, 964 bool fast_validate) 965 { 966 bool result = false; 967 968 DC_LOG_BANDWIDTH_CALCS( 969 "%s: start", 970 __func__); 971 972 if (bw_calcs( 973 dc->ctx, 974 dc->bw_dceip, 975 dc->bw_vbios, 976 context->res_ctx.pipe_ctx, 977 dc->res_pool->pipe_count, 978 &context->bw_ctx.bw.dce)) 979 result = true; 980 981 if (!result) 982 DC_LOG_BANDWIDTH_VALIDATION("%s: %dx%d@%d Bandwidth validation failed!\n", 983 __func__, 984 context->streams[0]->timing.h_addressable, 985 context->streams[0]->timing.v_addressable, 986 context->streams[0]->timing.pix_clk_100hz / 10); 987 988 if (memcmp(&dc->current_state->bw_ctx.bw.dce, 989 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { 990 991 DC_LOG_BANDWIDTH_CALCS( 992 "%s: finish,\n" 993 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 994 "stutMark_b: %d stutMark_a: %d\n" 995 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 996 "stutMark_b: %d stutMark_a: %d\n" 997 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 998 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n" 999 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" 1000 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n" 1001 , 1002 __func__, 1003 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark, 1004 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark, 1005 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, 1006 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, 1007 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark, 1008 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark, 1009 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark, 1010 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark, 1011 context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark, 1012 context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark, 1013 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark, 1014 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark, 1015 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark, 1016 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark, 1017 context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark, 1018 context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark, 1019 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark, 1020 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark, 1021 context->bw_ctx.bw.dce.stutter_mode_enable, 1022 context->bw_ctx.bw.dce.cpuc_state_change_enable, 1023 context->bw_ctx.bw.dce.cpup_state_change_enable, 1024 context->bw_ctx.bw.dce.nbp_state_change_enable, 1025 context->bw_ctx.bw.dce.all_displays_in_sync, 1026 context->bw_ctx.bw.dce.dispclk_khz, 1027 context->bw_ctx.bw.dce.sclk_khz, 1028 context->bw_ctx.bw.dce.sclk_deep_sleep_khz, 1029 context->bw_ctx.bw.dce.yclk_khz, 1030 context->bw_ctx.bw.dce.blackout_recovery_time_us); 1031 } 1032 return result; 1033 } 1034 1035 static enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state, 1036 struct dc_caps *caps) 1037 { 1038 if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) || 1039 ((plane_state->dst_rect.height * 2) < plane_state->src_rect.height)) 1040 return DC_FAIL_SURFACE_VALIDATE; 1041 1042 return DC_OK; 1043 } 1044 1045 static bool dce110_validate_surface_sets( 1046 struct dc_state *context) 1047 { 1048 int i, j; 1049 1050 for (i = 0; i < context->stream_count; i++) { 1051 if (context->stream_status[i].plane_count == 0) 1052 continue; 1053 1054 if (context->stream_status[i].plane_count > 2) 1055 return false; 1056 1057 for (j = 0; j < context->stream_status[i].plane_count; j++) { 1058 struct dc_plane_state *plane = 1059 context->stream_status[i].plane_states[j]; 1060 1061 /* underlay validation */ 1062 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 1063 1064 if ((plane->src_rect.width > 1920 || 1065 plane->src_rect.height > 1080)) 1066 return false; 1067 1068 /* we don't have the logic to support underlay 1069 * only yet so block the use case where we get 1070 * NV12 plane as top layer 1071 */ 1072 if (j == 0) 1073 return false; 1074 1075 /* irrespective of plane format, 1076 * stream should be RGB encoded 1077 */ 1078 if (context->streams[i]->timing.pixel_encoding 1079 != PIXEL_ENCODING_RGB) 1080 return false; 1081 1082 } 1083 1084 } 1085 } 1086 1087 return true; 1088 } 1089 1090 static enum dc_status dce110_validate_global( 1091 struct dc *dc, 1092 struct dc_state *context) 1093 { 1094 if (!dce110_validate_surface_sets(context)) 1095 return DC_FAIL_SURFACE_VALIDATE; 1096 1097 return DC_OK; 1098 } 1099 1100 static enum dc_status dce110_add_stream_to_ctx( 1101 struct dc *dc, 1102 struct dc_state *new_ctx, 1103 struct dc_stream_state *dc_stream) 1104 { 1105 enum dc_status result = DC_ERROR_UNEXPECTED; 1106 1107 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1108 1109 if (result == DC_OK) 1110 result = resource_map_clock_resources(dc, new_ctx, dc_stream); 1111 1112 1113 if (result == DC_OK) 1114 result = build_mapped_resource(dc, new_ctx, dc_stream); 1115 1116 return result; 1117 } 1118 1119 static struct pipe_ctx *dce110_acquire_underlay( 1120 struct dc_state *context, 1121 const struct resource_pool *pool, 1122 struct dc_stream_state *stream) 1123 { 1124 struct dc *dc = stream->ctx->dc; 1125 struct dce_hwseq *hws = dc->hwseq; 1126 struct resource_context *res_ctx = &context->res_ctx; 1127 unsigned int underlay_idx = pool->underlay_pipe_index; 1128 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; 1129 1130 if (res_ctx->pipe_ctx[underlay_idx].stream) 1131 return NULL; 1132 1133 pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx]; 1134 pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; 1135 /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/ 1136 pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; 1137 pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; 1138 pipe_ctx->pipe_idx = underlay_idx; 1139 1140 pipe_ctx->stream = stream; 1141 1142 if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) { 1143 struct tg_color black_color = {0}; 1144 struct dc_bios *dcb = dc->ctx->dc_bios; 1145 1146 hws->funcs.enable_display_power_gating( 1147 dc, 1148 pipe_ctx->stream_res.tg->inst, 1149 dcb, PIPE_GATING_CONTROL_DISABLE); 1150 1151 /* 1152 * This is for powering on underlay, so crtc does not 1153 * need to be enabled 1154 */ 1155 1156 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg, 1157 &stream->timing, 1158 0, 1159 0, 1160 0, 1161 0, 1162 pipe_ctx->stream->signal, 1163 false); 1164 1165 pipe_ctx->stream_res.tg->funcs->enable_advanced_request( 1166 pipe_ctx->stream_res.tg, 1167 true, 1168 &stream->timing); 1169 1170 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi, 1171 stream->timing.h_total, 1172 stream->timing.v_total, 1173 stream->timing.pix_clk_100hz / 10, 1174 context->stream_count); 1175 1176 color_space_to_black_color(dc, 1177 COLOR_SPACE_YCBCR601, &black_color); 1178 pipe_ctx->stream_res.tg->funcs->set_blank_color( 1179 pipe_ctx->stream_res.tg, 1180 &black_color); 1181 } 1182 1183 return pipe_ctx; 1184 } 1185 1186 static void dce110_destroy_resource_pool(struct resource_pool **pool) 1187 { 1188 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 1189 1190 dce110_resource_destruct(dce110_pool); 1191 kfree(dce110_pool); 1192 *pool = NULL; 1193 } 1194 1195 struct stream_encoder *dce110_find_first_free_match_stream_enc_for_link( 1196 struct resource_context *res_ctx, 1197 const struct resource_pool *pool, 1198 struct dc_stream_state *stream) 1199 { 1200 int i; 1201 int j = -1; 1202 struct dc_link *link = stream->link; 1203 1204 for (i = 0; i < pool->stream_enc_count; i++) { 1205 if (!res_ctx->is_stream_enc_acquired[i] && 1206 pool->stream_enc[i]) { 1207 /* Store first available for MST second display 1208 * in daisy chain use case 1209 */ 1210 j = i; 1211 if (pool->stream_enc[i]->id == 1212 link->link_enc->preferred_engine) 1213 return pool->stream_enc[i]; 1214 } 1215 } 1216 1217 /* 1218 * For CZ and later, we can allow DIG FE and BE to differ for all display types 1219 */ 1220 1221 if (j >= 0) 1222 return pool->stream_enc[j]; 1223 1224 return NULL; 1225 } 1226 1227 1228 static const struct resource_funcs dce110_res_pool_funcs = { 1229 .destroy = dce110_destroy_resource_pool, 1230 .link_enc_create = dce110_link_encoder_create, 1231 .panel_cntl_create = dce110_panel_cntl_create, 1232 .validate_bandwidth = dce110_validate_bandwidth, 1233 .validate_plane = dce110_validate_plane, 1234 .acquire_idle_pipe_for_layer = dce110_acquire_underlay, 1235 .add_stream_to_ctx = dce110_add_stream_to_ctx, 1236 .validate_global = dce110_validate_global, 1237 .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link 1238 }; 1239 1240 static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) 1241 { 1242 struct dce110_timing_generator *dce110_tgv = kzalloc(sizeof(*dce110_tgv), 1243 GFP_KERNEL); 1244 struct dce_transform *dce110_xfmv = kzalloc(sizeof(*dce110_xfmv), 1245 GFP_KERNEL); 1246 struct dce_mem_input *dce110_miv = kzalloc(sizeof(*dce110_miv), 1247 GFP_KERNEL); 1248 struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv), 1249 GFP_KERNEL); 1250 1251 if (!dce110_tgv || !dce110_xfmv || !dce110_miv || !dce110_oppv) { 1252 kfree(dce110_tgv); 1253 kfree(dce110_xfmv); 1254 kfree(dce110_miv); 1255 kfree(dce110_oppv); 1256 return false; 1257 } 1258 1259 dce110_opp_v_construct(dce110_oppv, ctx); 1260 1261 dce110_timing_generator_v_construct(dce110_tgv, ctx); 1262 dce110_mem_input_v_construct(dce110_miv, ctx); 1263 dce110_transform_v_construct(dce110_xfmv, ctx); 1264 1265 pool->opps[pool->pipe_count] = &dce110_oppv->base; 1266 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; 1267 pool->mis[pool->pipe_count] = &dce110_miv->base; 1268 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; 1269 pool->pipe_count++; 1270 1271 /* update the public caps to indicate an underlay is available */ 1272 ctx->dc->caps.max_slave_planes = 1; 1273 ctx->dc->caps.max_slave_yuv_planes = 1; 1274 ctx->dc->caps.max_slave_rgb_planes = 0; 1275 1276 return true; 1277 } 1278 1279 static void bw_calcs_data_update_from_pplib(struct dc *dc) 1280 { 1281 struct dm_pp_clock_levels clks = {0}; 1282 1283 /*do system clock*/ 1284 dm_pp_get_clock_levels_by_type( 1285 dc->ctx, 1286 DM_PP_CLOCK_TYPE_ENGINE_CLK, 1287 &clks); 1288 /* convert all the clock fro kHz to fix point mHz */ 1289 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 1290 clks.clocks_in_khz[clks.num_levels-1], 1000); 1291 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 1292 clks.clocks_in_khz[clks.num_levels/8], 1000); 1293 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 1294 clks.clocks_in_khz[clks.num_levels*2/8], 1000); 1295 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 1296 clks.clocks_in_khz[clks.num_levels*3/8], 1000); 1297 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 1298 clks.clocks_in_khz[clks.num_levels*4/8], 1000); 1299 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 1300 clks.clocks_in_khz[clks.num_levels*5/8], 1000); 1301 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1302 clks.clocks_in_khz[clks.num_levels*6/8], 1000); 1303 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1304 clks.clocks_in_khz[0], 1000); 1305 dc->sclk_lvls = clks; 1306 1307 /*do display clock*/ 1308 dm_pp_get_clock_levels_by_type( 1309 dc->ctx, 1310 DM_PP_CLOCK_TYPE_DISPLAY_CLK, 1311 &clks); 1312 dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed( 1313 clks.clocks_in_khz[clks.num_levels-1], 1000); 1314 dc->bw_vbios->mid_voltage_max_dispclk = bw_frc_to_fixed( 1315 clks.clocks_in_khz[clks.num_levels>>1], 1000); 1316 dc->bw_vbios->low_voltage_max_dispclk = bw_frc_to_fixed( 1317 clks.clocks_in_khz[0], 1000); 1318 1319 /*do memory clock*/ 1320 dm_pp_get_clock_levels_by_type( 1321 dc->ctx, 1322 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1323 &clks); 1324 1325 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1326 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER_CZ, 1000); 1327 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1328 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ, 1329 1000); 1330 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1331 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER_CZ, 1332 1000); 1333 } 1334 1335 static const struct resource_caps *dce110_resource_cap( 1336 struct hw_asic_id *asic_id) 1337 { 1338 if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev)) 1339 return &stoney_resource_cap; 1340 else 1341 return &carrizo_resource_cap; 1342 } 1343 1344 static bool dce110_resource_construct( 1345 uint8_t num_virtual_links, 1346 struct dc *dc, 1347 struct dce110_resource_pool *pool, 1348 struct hw_asic_id asic_id) 1349 { 1350 unsigned int i; 1351 struct dc_context *ctx = dc->ctx; 1352 struct dc_bios *bp; 1353 1354 ctx->dc_bios->regs = &bios_regs; 1355 1356 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); 1357 pool->base.funcs = &dce110_res_pool_funcs; 1358 1359 /************************************************* 1360 * Resource + asic cap harcoding * 1361 *************************************************/ 1362 1363 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1364 pool->base.underlay_pipe_index = pool->base.pipe_count; 1365 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1366 dc->caps.max_downscale_ratio = 150; 1367 dc->caps.i2c_speed_in_khz = 40; 1368 dc->caps.i2c_speed_in_khz_hdcp = 40; 1369 dc->caps.max_cursor_size = 128; 1370 dc->caps.min_horizontal_blanking_period = 80; 1371 dc->caps.is_apu = true; 1372 dc->caps.extended_aux_timeout_support = false; 1373 1374 /************************************************* 1375 * Create resources * 1376 *************************************************/ 1377 1378 bp = ctx->dc_bios; 1379 1380 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 1381 pool->base.dp_clock_source = 1382 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1383 1384 pool->base.clock_sources[0] = 1385 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, 1386 &clk_src_regs[0], false); 1387 pool->base.clock_sources[1] = 1388 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, 1389 &clk_src_regs[1], false); 1390 1391 pool->base.clk_src_count = 2; 1392 1393 /* TODO: find out if CZ support 3 PLLs */ 1394 } 1395 1396 if (pool->base.dp_clock_source == NULL) { 1397 dm_error("DC: failed to create dp clock source!\n"); 1398 BREAK_TO_DEBUGGER(); 1399 goto res_create_fail; 1400 } 1401 1402 for (i = 0; i < pool->base.clk_src_count; i++) { 1403 if (pool->base.clock_sources[i] == NULL) { 1404 dm_error("DC: failed to create clock sources!\n"); 1405 BREAK_TO_DEBUGGER(); 1406 goto res_create_fail; 1407 } 1408 } 1409 1410 pool->base.dmcu = dce_dmcu_create(ctx, 1411 &dmcu_regs, 1412 &dmcu_shift, 1413 &dmcu_mask); 1414 if (pool->base.dmcu == NULL) { 1415 dm_error("DC: failed to create dmcu!\n"); 1416 BREAK_TO_DEBUGGER(); 1417 goto res_create_fail; 1418 } 1419 1420 pool->base.abm = dce_abm_create(ctx, 1421 &abm_regs, 1422 &abm_shift, 1423 &abm_mask); 1424 if (pool->base.abm == NULL) { 1425 dm_error("DC: failed to create abm!\n"); 1426 BREAK_TO_DEBUGGER(); 1427 goto res_create_fail; 1428 } 1429 1430 { 1431 struct irq_service_init_data init_data; 1432 init_data.ctx = dc->ctx; 1433 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 1434 if (!pool->base.irqs) 1435 goto res_create_fail; 1436 } 1437 1438 for (i = 0; i < pool->base.pipe_count; i++) { 1439 pool->base.timing_generators[i] = dce110_timing_generator_create( 1440 ctx, i, &dce110_tg_offsets[i]); 1441 if (pool->base.timing_generators[i] == NULL) { 1442 BREAK_TO_DEBUGGER(); 1443 dm_error("DC: failed to create tg!\n"); 1444 goto res_create_fail; 1445 } 1446 1447 pool->base.mis[i] = dce110_mem_input_create(ctx, i); 1448 if (pool->base.mis[i] == NULL) { 1449 BREAK_TO_DEBUGGER(); 1450 dm_error( 1451 "DC: failed to create memory input!\n"); 1452 goto res_create_fail; 1453 } 1454 1455 pool->base.ipps[i] = dce110_ipp_create(ctx, i); 1456 if (pool->base.ipps[i] == NULL) { 1457 BREAK_TO_DEBUGGER(); 1458 dm_error( 1459 "DC: failed to create input pixel processor!\n"); 1460 goto res_create_fail; 1461 } 1462 1463 pool->base.transforms[i] = dce110_transform_create(ctx, i); 1464 if (pool->base.transforms[i] == NULL) { 1465 BREAK_TO_DEBUGGER(); 1466 dm_error( 1467 "DC: failed to create transform!\n"); 1468 goto res_create_fail; 1469 } 1470 1471 pool->base.opps[i] = dce110_opp_create(ctx, i); 1472 if (pool->base.opps[i] == NULL) { 1473 BREAK_TO_DEBUGGER(); 1474 dm_error( 1475 "DC: failed to create output pixel processor!\n"); 1476 goto res_create_fail; 1477 } 1478 } 1479 1480 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1481 pool->base.engines[i] = dce110_aux_engine_create(ctx, i); 1482 if (pool->base.engines[i] == NULL) { 1483 BREAK_TO_DEBUGGER(); 1484 dm_error( 1485 "DC:failed to create aux engine!!\n"); 1486 goto res_create_fail; 1487 } 1488 pool->base.hw_i2cs[i] = dce110_i2c_hw_create(ctx, i); 1489 if (pool->base.hw_i2cs[i] == NULL) { 1490 BREAK_TO_DEBUGGER(); 1491 dm_error( 1492 "DC:failed to create i2c engine!!\n"); 1493 goto res_create_fail; 1494 } 1495 pool->base.sw_i2cs[i] = NULL; 1496 } 1497 1498 if (dc->config.fbc_support) 1499 dc->fbc_compressor = dce110_compressor_create(ctx); 1500 1501 if (!underlay_create(ctx, &pool->base)) 1502 goto res_create_fail; 1503 1504 if (!resource_construct(num_virtual_links, dc, &pool->base, 1505 &res_create_funcs)) 1506 goto res_create_fail; 1507 1508 /* Create hardware sequencer */ 1509 dce110_hw_sequencer_construct(dc); 1510 1511 dc->caps.max_planes = pool->base.pipe_count; 1512 1513 for (i = 0; i < pool->base.underlay_pipe_index; ++i) 1514 dc->caps.planes[i] = plane_cap; 1515 1516 dc->caps.planes[pool->base.underlay_pipe_index] = underlay_plane_cap; 1517 1518 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1519 1520 bw_calcs_data_update_from_pplib(dc); 1521 1522 return true; 1523 1524 res_create_fail: 1525 dce110_resource_destruct(pool); 1526 return false; 1527 } 1528 1529 struct resource_pool *dce110_create_resource_pool( 1530 uint8_t num_virtual_links, 1531 struct dc *dc, 1532 struct hw_asic_id asic_id) 1533 { 1534 struct dce110_resource_pool *pool = 1535 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1536 1537 if (!pool) 1538 return NULL; 1539 1540 if (dce110_resource_construct(num_virtual_links, dc, pool, asic_id)) 1541 return &pool->base; 1542 1543 kfree(pool); 1544 BREAK_TO_DEBUGGER(); 1545 return NULL; 1546 } 1547