1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "link_encoder.h" 29 #include "stream_encoder.h" 30 31 #include "resource.h" 32 #include "dce110/dce110_resource.h" 33 34 #include "dce/dce_clk_mgr.h" 35 #include "include/irq_service_interface.h" 36 #include "dce/dce_audio.h" 37 #include "dce110/dce110_timing_generator.h" 38 #include "irq/dce110/irq_service_dce110.h" 39 #include "dce110/dce110_timing_generator_v.h" 40 #include "dce/dce_link_encoder.h" 41 #include "dce/dce_stream_encoder.h" 42 #include "dce/dce_mem_input.h" 43 #include "dce110/dce110_mem_input_v.h" 44 #include "dce/dce_ipp.h" 45 #include "dce/dce_transform.h" 46 #include "dce110/dce110_transform_v.h" 47 #include "dce/dce_opp.h" 48 #include "dce110/dce110_opp_v.h" 49 #include "dce/dce_clock_source.h" 50 #include "dce/dce_hwseq.h" 51 #include "dce110/dce110_hw_sequencer.h" 52 #include "dce/dce_aux.h" 53 #include "dce/dce_abm.h" 54 #include "dce/dce_dmcu.h" 55 #include "dce/dce_i2c.h" 56 57 #define DC_LOGGER \ 58 dc->ctx->logger 59 60 #include "dce110/dce110_compressor.h" 61 62 #include "reg_helper.h" 63 64 #include "dce/dce_11_0_d.h" 65 #include "dce/dce_11_0_sh_mask.h" 66 67 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 68 #include "gmc/gmc_8_2_d.h" 69 #include "gmc/gmc_8_2_sh_mask.h" 70 #endif 71 72 #ifndef mmDP_DPHY_INTERNAL_CTRL 73 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 74 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 75 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 76 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 77 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 78 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 79 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 80 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 81 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 82 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 83 #endif 84 85 #ifndef mmBIOS_SCRATCH_2 86 #define mmBIOS_SCRATCH_2 0x05CB 87 #define mmBIOS_SCRATCH_3 0x05CC 88 #define mmBIOS_SCRATCH_6 0x05CF 89 #endif 90 91 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 92 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 93 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 94 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 95 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 96 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 97 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 98 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 99 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 100 #endif 101 102 #ifndef mmDP_DPHY_FAST_TRAINING 103 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 104 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 105 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 106 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 107 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 108 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 109 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 110 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 111 #endif 112 113 #ifndef DPHY_RX_FAST_TRAINING_CAPABLE 114 #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1 115 #endif 116 117 static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = { 118 { 119 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 120 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 121 }, 122 { 123 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 124 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 125 }, 126 { 127 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 128 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 129 }, 130 { 131 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 132 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 133 }, 134 { 135 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 136 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 137 }, 138 { 139 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 140 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 141 } 142 }; 143 144 /* set register offset */ 145 #define SR(reg_name)\ 146 .reg_name = mm ## reg_name 147 148 /* set register offset with instance */ 149 #define SRI(reg_name, block, id)\ 150 .reg_name = mm ## block ## id ## _ ## reg_name 151 152 static const struct clk_mgr_registers disp_clk_regs = { 153 CLK_COMMON_REG_LIST_DCE_BASE() 154 }; 155 156 static const struct clk_mgr_shift disp_clk_shift = { 157 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 158 }; 159 160 static const struct clk_mgr_mask disp_clk_mask = { 161 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 162 }; 163 164 static const struct dce_dmcu_registers dmcu_regs = { 165 DMCU_DCE110_COMMON_REG_LIST() 166 }; 167 168 static const struct dce_dmcu_shift dmcu_shift = { 169 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 170 }; 171 172 static const struct dce_dmcu_mask dmcu_mask = { 173 DMCU_MASK_SH_LIST_DCE110(_MASK) 174 }; 175 176 static const struct dce_abm_registers abm_regs = { 177 ABM_DCE110_COMMON_REG_LIST() 178 }; 179 180 static const struct dce_abm_shift abm_shift = { 181 ABM_MASK_SH_LIST_DCE110(__SHIFT) 182 }; 183 184 static const struct dce_abm_mask abm_mask = { 185 ABM_MASK_SH_LIST_DCE110(_MASK) 186 }; 187 188 #define ipp_regs(id)\ 189 [id] = {\ 190 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 191 } 192 193 static const struct dce_ipp_registers ipp_regs[] = { 194 ipp_regs(0), 195 ipp_regs(1), 196 ipp_regs(2) 197 }; 198 199 static const struct dce_ipp_shift ipp_shift = { 200 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 201 }; 202 203 static const struct dce_ipp_mask ipp_mask = { 204 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 205 }; 206 207 #define transform_regs(id)\ 208 [id] = {\ 209 XFM_COMMON_REG_LIST_DCE110(id)\ 210 } 211 212 static const struct dce_transform_registers xfm_regs[] = { 213 transform_regs(0), 214 transform_regs(1), 215 transform_regs(2) 216 }; 217 218 static const struct dce_transform_shift xfm_shift = { 219 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 220 }; 221 222 static const struct dce_transform_mask xfm_mask = { 223 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 224 }; 225 226 #define aux_regs(id)\ 227 [id] = {\ 228 AUX_REG_LIST(id)\ 229 } 230 231 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 232 aux_regs(0), 233 aux_regs(1), 234 aux_regs(2), 235 aux_regs(3), 236 aux_regs(4), 237 aux_regs(5) 238 }; 239 240 #define hpd_regs(id)\ 241 [id] = {\ 242 HPD_REG_LIST(id)\ 243 } 244 245 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 246 hpd_regs(0), 247 hpd_regs(1), 248 hpd_regs(2), 249 hpd_regs(3), 250 hpd_regs(4), 251 hpd_regs(5) 252 }; 253 254 255 #define link_regs(id)\ 256 [id] = {\ 257 LE_DCE110_REG_LIST(id)\ 258 } 259 260 static const struct dce110_link_enc_registers link_enc_regs[] = { 261 link_regs(0), 262 link_regs(1), 263 link_regs(2), 264 link_regs(3), 265 link_regs(4), 266 link_regs(5), 267 link_regs(6), 268 }; 269 270 #define stream_enc_regs(id)\ 271 [id] = {\ 272 SE_COMMON_REG_LIST(id),\ 273 .TMDS_CNTL = 0,\ 274 } 275 276 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 277 stream_enc_regs(0), 278 stream_enc_regs(1), 279 stream_enc_regs(2) 280 }; 281 282 static const struct dce_stream_encoder_shift se_shift = { 283 SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 284 }; 285 286 static const struct dce_stream_encoder_mask se_mask = { 287 SE_COMMON_MASK_SH_LIST_DCE110(_MASK) 288 }; 289 290 #define opp_regs(id)\ 291 [id] = {\ 292 OPP_DCE_110_REG_LIST(id),\ 293 } 294 295 static const struct dce_opp_registers opp_regs[] = { 296 opp_regs(0), 297 opp_regs(1), 298 opp_regs(2), 299 opp_regs(3), 300 opp_regs(4), 301 opp_regs(5) 302 }; 303 304 static const struct dce_opp_shift opp_shift = { 305 OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT) 306 }; 307 308 static const struct dce_opp_mask opp_mask = { 309 OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK) 310 }; 311 312 #define aux_engine_regs(id)\ 313 [id] = {\ 314 AUX_COMMON_REG_LIST(id), \ 315 .AUX_RESET_MASK = 0 \ 316 } 317 318 static const struct dce110_aux_registers aux_engine_regs[] = { 319 aux_engine_regs(0), 320 aux_engine_regs(1), 321 aux_engine_regs(2), 322 aux_engine_regs(3), 323 aux_engine_regs(4), 324 aux_engine_regs(5) 325 }; 326 327 #define audio_regs(id)\ 328 [id] = {\ 329 AUD_COMMON_REG_LIST(id)\ 330 } 331 332 static const struct dce_audio_registers audio_regs[] = { 333 audio_regs(0), 334 audio_regs(1), 335 audio_regs(2), 336 audio_regs(3), 337 audio_regs(4), 338 audio_regs(5), 339 audio_regs(6), 340 }; 341 342 static const struct dce_audio_shift audio_shift = { 343 AUD_COMMON_MASK_SH_LIST(__SHIFT) 344 }; 345 346 static const struct dce_aduio_mask audio_mask = { 347 AUD_COMMON_MASK_SH_LIST(_MASK) 348 }; 349 350 /* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */ 351 352 353 #define clk_src_regs(id)\ 354 [id] = {\ 355 CS_COMMON_REG_LIST_DCE_100_110(id),\ 356 } 357 358 static const struct dce110_clk_src_regs clk_src_regs[] = { 359 clk_src_regs(0), 360 clk_src_regs(1), 361 clk_src_regs(2) 362 }; 363 364 static const struct dce110_clk_src_shift cs_shift = { 365 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 366 }; 367 368 static const struct dce110_clk_src_mask cs_mask = { 369 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 370 }; 371 372 static const struct bios_registers bios_regs = { 373 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 374 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 375 }; 376 377 static const struct resource_caps carrizo_resource_cap = { 378 .num_timing_generator = 3, 379 .num_video_plane = 1, 380 .num_audio = 3, 381 .num_stream_encoder = 3, 382 .num_pll = 2, 383 .num_ddc = 3, 384 }; 385 386 static const struct resource_caps stoney_resource_cap = { 387 .num_timing_generator = 2, 388 .num_video_plane = 1, 389 .num_audio = 3, 390 .num_stream_encoder = 3, 391 .num_pll = 2, 392 .num_ddc = 3, 393 }; 394 395 static const struct dc_plane_cap plane_cap = { 396 .type = DC_PLANE_TYPE_DCE_RGB, 397 .blends_with_below = true, 398 .blends_with_above = true, 399 .per_pixel_alpha = 1, 400 401 .pixel_format_support = { 402 .argb8888 = true, 403 .nv12 = false, 404 .fp16 = false 405 }, 406 407 .max_upscale_factor = { 408 .argb8888 = 16000, 409 .nv12 = 1, 410 .fp16 = 1 411 }, 412 413 .max_downscale_factor = { 414 .argb8888 = 250, 415 .nv12 = 1, 416 .fp16 = 1 417 } 418 }; 419 420 static const struct dc_plane_cap underlay_plane_cap = { 421 .type = DC_PLANE_TYPE_DCE_UNDERLAY, 422 .blends_with_above = true, 423 .per_pixel_alpha = 1, 424 425 .pixel_format_support = { 426 .argb8888 = false, 427 .nv12 = true, 428 .fp16 = false 429 }, 430 431 .max_upscale_factor = { 432 .argb8888 = 1, 433 .nv12 = 16000, 434 .fp16 = 1 435 }, 436 437 .max_downscale_factor = { 438 .argb8888 = 1, 439 .nv12 = 250, 440 .fp16 = 1 441 } 442 }; 443 444 #define CTX ctx 445 #define REG(reg) mm ## reg 446 447 #ifndef mmCC_DC_HDMI_STRAPS 448 #define mmCC_DC_HDMI_STRAPS 0x4819 449 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 450 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 451 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 452 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 453 #endif 454 455 static void read_dce_straps( 456 struct dc_context *ctx, 457 struct resource_straps *straps) 458 { 459 REG_GET_2(CC_DC_HDMI_STRAPS, 460 HDMI_DISABLE, &straps->hdmi_disable, 461 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 462 463 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 464 } 465 466 static struct audio *create_audio( 467 struct dc_context *ctx, unsigned int inst) 468 { 469 return dce_audio_create(ctx, inst, 470 &audio_regs[inst], &audio_shift, &audio_mask); 471 } 472 473 static struct timing_generator *dce110_timing_generator_create( 474 struct dc_context *ctx, 475 uint32_t instance, 476 const struct dce110_timing_generator_offsets *offsets) 477 { 478 struct dce110_timing_generator *tg110 = 479 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 480 481 if (!tg110) 482 return NULL; 483 484 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 485 return &tg110->base; 486 } 487 488 static struct stream_encoder *dce110_stream_encoder_create( 489 enum engine_id eng_id, 490 struct dc_context *ctx) 491 { 492 struct dce110_stream_encoder *enc110 = 493 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 494 495 if (!enc110) 496 return NULL; 497 498 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 499 &stream_enc_regs[eng_id], 500 &se_shift, &se_mask); 501 return &enc110->base; 502 } 503 504 #define SRII(reg_name, block, id)\ 505 .reg_name[id] = mm ## block ## id ## _ ## reg_name 506 507 static const struct dce_hwseq_registers hwseq_stoney_reg = { 508 HWSEQ_ST_REG_LIST() 509 }; 510 511 static const struct dce_hwseq_registers hwseq_cz_reg = { 512 HWSEQ_CZ_REG_LIST() 513 }; 514 515 static const struct dce_hwseq_shift hwseq_shift = { 516 HWSEQ_DCE11_MASK_SH_LIST(__SHIFT), 517 }; 518 519 static const struct dce_hwseq_mask hwseq_mask = { 520 HWSEQ_DCE11_MASK_SH_LIST(_MASK), 521 }; 522 523 static struct dce_hwseq *dce110_hwseq_create( 524 struct dc_context *ctx) 525 { 526 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 527 528 if (hws) { 529 hws->ctx = ctx; 530 hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ? 531 &hwseq_stoney_reg : &hwseq_cz_reg; 532 hws->shifts = &hwseq_shift; 533 hws->masks = &hwseq_mask; 534 hws->wa.blnd_crtc_trigger = true; 535 } 536 return hws; 537 } 538 539 static const struct resource_create_funcs res_create_funcs = { 540 .read_dce_straps = read_dce_straps, 541 .create_audio = create_audio, 542 .create_stream_encoder = dce110_stream_encoder_create, 543 .create_hwseq = dce110_hwseq_create, 544 }; 545 546 #define mi_inst_regs(id) { \ 547 MI_DCE11_REG_LIST(id), \ 548 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 549 } 550 static const struct dce_mem_input_registers mi_regs[] = { 551 mi_inst_regs(0), 552 mi_inst_regs(1), 553 mi_inst_regs(2), 554 }; 555 556 static const struct dce_mem_input_shift mi_shifts = { 557 MI_DCE11_MASK_SH_LIST(__SHIFT), 558 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 559 }; 560 561 static const struct dce_mem_input_mask mi_masks = { 562 MI_DCE11_MASK_SH_LIST(_MASK), 563 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 564 }; 565 566 567 static struct mem_input *dce110_mem_input_create( 568 struct dc_context *ctx, 569 uint32_t inst) 570 { 571 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 572 GFP_KERNEL); 573 574 if (!dce_mi) { 575 BREAK_TO_DEBUGGER(); 576 return NULL; 577 } 578 579 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 580 dce_mi->wa.single_head_rdreq_dmif_limit = 3; 581 return &dce_mi->base; 582 } 583 584 static void dce110_transform_destroy(struct transform **xfm) 585 { 586 kfree(TO_DCE_TRANSFORM(*xfm)); 587 *xfm = NULL; 588 } 589 590 static struct transform *dce110_transform_create( 591 struct dc_context *ctx, 592 uint32_t inst) 593 { 594 struct dce_transform *transform = 595 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 596 597 if (!transform) 598 return NULL; 599 600 dce_transform_construct(transform, ctx, inst, 601 &xfm_regs[inst], &xfm_shift, &xfm_mask); 602 return &transform->base; 603 } 604 605 static struct input_pixel_processor *dce110_ipp_create( 606 struct dc_context *ctx, uint32_t inst) 607 { 608 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 609 610 if (!ipp) { 611 BREAK_TO_DEBUGGER(); 612 return NULL; 613 } 614 615 dce_ipp_construct(ipp, ctx, inst, 616 &ipp_regs[inst], &ipp_shift, &ipp_mask); 617 return &ipp->base; 618 } 619 620 static const struct encoder_feature_support link_enc_feature = { 621 .max_hdmi_deep_color = COLOR_DEPTH_121212, 622 .max_hdmi_pixel_clock = 300000, 623 .flags.bits.IS_HBR2_CAPABLE = true, 624 .flags.bits.IS_TPS3_CAPABLE = true 625 }; 626 627 static struct link_encoder *dce110_link_encoder_create( 628 const struct encoder_init_data *enc_init_data) 629 { 630 struct dce110_link_encoder *enc110 = 631 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 632 633 if (!enc110) 634 return NULL; 635 636 dce110_link_encoder_construct(enc110, 637 enc_init_data, 638 &link_enc_feature, 639 &link_enc_regs[enc_init_data->transmitter], 640 &link_enc_aux_regs[enc_init_data->channel - 1], 641 &link_enc_hpd_regs[enc_init_data->hpd_source]); 642 return &enc110->base; 643 } 644 645 static struct output_pixel_processor *dce110_opp_create( 646 struct dc_context *ctx, 647 uint32_t inst) 648 { 649 struct dce110_opp *opp = 650 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 651 652 if (!opp) 653 return NULL; 654 655 dce110_opp_construct(opp, 656 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 657 return &opp->base; 658 } 659 660 struct dce_aux *dce110_aux_engine_create( 661 struct dc_context *ctx, 662 uint32_t inst) 663 { 664 struct aux_engine_dce110 *aux_engine = 665 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 666 667 if (!aux_engine) 668 return NULL; 669 670 dce110_aux_engine_construct(aux_engine, ctx, inst, 671 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 672 &aux_engine_regs[inst]); 673 674 return &aux_engine->base; 675 } 676 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 677 678 static const struct dce_i2c_registers i2c_hw_regs[] = { 679 i2c_inst_regs(1), 680 i2c_inst_regs(2), 681 i2c_inst_regs(3), 682 i2c_inst_regs(4), 683 i2c_inst_regs(5), 684 i2c_inst_regs(6), 685 }; 686 687 static const struct dce_i2c_shift i2c_shifts = { 688 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 689 }; 690 691 static const struct dce_i2c_mask i2c_masks = { 692 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 693 }; 694 695 struct dce_i2c_hw *dce110_i2c_hw_create( 696 struct dc_context *ctx, 697 uint32_t inst) 698 { 699 struct dce_i2c_hw *dce_i2c_hw = 700 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 701 702 if (!dce_i2c_hw) 703 return NULL; 704 705 dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst, 706 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 707 708 return dce_i2c_hw; 709 } 710 struct clock_source *dce110_clock_source_create( 711 struct dc_context *ctx, 712 struct dc_bios *bios, 713 enum clock_source_id id, 714 const struct dce110_clk_src_regs *regs, 715 bool dp_clk_src) 716 { 717 struct dce110_clk_src *clk_src = 718 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 719 720 if (!clk_src) 721 return NULL; 722 723 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 724 regs, &cs_shift, &cs_mask)) { 725 clk_src->base.dp_clk_src = dp_clk_src; 726 return &clk_src->base; 727 } 728 729 BREAK_TO_DEBUGGER(); 730 return NULL; 731 } 732 733 void dce110_clock_source_destroy(struct clock_source **clk_src) 734 { 735 struct dce110_clk_src *dce110_clk_src; 736 737 if (!clk_src) 738 return; 739 740 dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src); 741 742 kfree(dce110_clk_src->dp_ss_params); 743 kfree(dce110_clk_src->hdmi_ss_params); 744 kfree(dce110_clk_src->dvi_ss_params); 745 746 kfree(dce110_clk_src); 747 *clk_src = NULL; 748 } 749 750 static void destruct(struct dce110_resource_pool *pool) 751 { 752 unsigned int i; 753 754 for (i = 0; i < pool->base.pipe_count; i++) { 755 if (pool->base.opps[i] != NULL) 756 dce110_opp_destroy(&pool->base.opps[i]); 757 758 if (pool->base.transforms[i] != NULL) 759 dce110_transform_destroy(&pool->base.transforms[i]); 760 761 if (pool->base.ipps[i] != NULL) 762 dce_ipp_destroy(&pool->base.ipps[i]); 763 764 if (pool->base.mis[i] != NULL) { 765 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 766 pool->base.mis[i] = NULL; 767 } 768 769 if (pool->base.timing_generators[i] != NULL) { 770 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 771 pool->base.timing_generators[i] = NULL; 772 } 773 } 774 775 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 776 if (pool->base.engines[i] != NULL) 777 dce110_engine_destroy(&pool->base.engines[i]); 778 if (pool->base.hw_i2cs[i] != NULL) { 779 kfree(pool->base.hw_i2cs[i]); 780 pool->base.hw_i2cs[i] = NULL; 781 } 782 if (pool->base.sw_i2cs[i] != NULL) { 783 kfree(pool->base.sw_i2cs[i]); 784 pool->base.sw_i2cs[i] = NULL; 785 } 786 } 787 788 for (i = 0; i < pool->base.stream_enc_count; i++) { 789 if (pool->base.stream_enc[i] != NULL) 790 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 791 } 792 793 for (i = 0; i < pool->base.clk_src_count; i++) { 794 if (pool->base.clock_sources[i] != NULL) { 795 dce110_clock_source_destroy(&pool->base.clock_sources[i]); 796 } 797 } 798 799 if (pool->base.dp_clock_source != NULL) 800 dce110_clock_source_destroy(&pool->base.dp_clock_source); 801 802 for (i = 0; i < pool->base.audio_count; i++) { 803 if (pool->base.audios[i] != NULL) { 804 dce_aud_destroy(&pool->base.audios[i]); 805 } 806 } 807 808 if (pool->base.abm != NULL) 809 dce_abm_destroy(&pool->base.abm); 810 811 if (pool->base.dmcu != NULL) 812 dce_dmcu_destroy(&pool->base.dmcu); 813 814 if (pool->base.clk_mgr != NULL) 815 dce_clk_mgr_destroy(&pool->base.clk_mgr); 816 817 if (pool->base.irqs != NULL) { 818 dal_irq_service_destroy(&pool->base.irqs); 819 } 820 } 821 822 823 static void get_pixel_clock_parameters( 824 const struct pipe_ctx *pipe_ctx, 825 struct pixel_clk_params *pixel_clk_params) 826 { 827 const struct dc_stream_state *stream = pipe_ctx->stream; 828 829 /*TODO: is this halved for YCbCr 420? in that case we might want to move 830 * the pixel clock normalization for hdmi up to here instead of doing it 831 * in pll_adjust_pix_clk 832 */ 833 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 834 pixel_clk_params->encoder_object_id = stream->link->link_enc->id; 835 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 836 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 837 /* TODO: un-hardcode*/ 838 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 839 LINK_RATE_REF_FREQ_IN_KHZ; 840 pixel_clk_params->flags.ENABLE_SS = 0; 841 pixel_clk_params->color_depth = 842 stream->timing.display_color_depth; 843 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 844 pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding == 845 PIXEL_ENCODING_YCBCR420); 846 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 847 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) { 848 pixel_clk_params->color_depth = COLOR_DEPTH_888; 849 } 850 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 851 pixel_clk_params->requested_pix_clk_100hz = pixel_clk_params->requested_pix_clk_100hz / 2; 852 } 853 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 854 pixel_clk_params->requested_pix_clk_100hz *= 2; 855 856 } 857 858 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 859 { 860 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 861 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 862 pipe_ctx->clock_source, 863 &pipe_ctx->stream_res.pix_clk_params, 864 &pipe_ctx->pll_settings); 865 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 866 &pipe_ctx->stream->bit_depth_params); 867 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 868 } 869 870 static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx) 871 { 872 if (pipe_ctx->pipe_idx != underlay_idx) 873 return true; 874 if (!pipe_ctx->plane_state) 875 return false; 876 if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 877 return false; 878 return true; 879 } 880 881 static enum dc_status build_mapped_resource( 882 const struct dc *dc, 883 struct dc_state *context, 884 struct dc_stream_state *stream) 885 { 886 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 887 888 if (!pipe_ctx) 889 return DC_ERROR_UNEXPECTED; 890 891 if (!is_surface_pixel_format_supported(pipe_ctx, 892 dc->res_pool->underlay_pipe_index)) 893 return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; 894 895 dce110_resource_build_pipe_hw_param(pipe_ctx); 896 897 /* TODO: validate audio ASIC caps, encoder */ 898 899 resource_build_info_frame(pipe_ctx); 900 901 return DC_OK; 902 } 903 904 static bool dce110_validate_bandwidth( 905 struct dc *dc, 906 struct dc_state *context, 907 bool fast_validate) 908 { 909 bool result = false; 910 911 DC_LOG_BANDWIDTH_CALCS( 912 "%s: start", 913 __func__); 914 915 if (bw_calcs( 916 dc->ctx, 917 dc->bw_dceip, 918 dc->bw_vbios, 919 context->res_ctx.pipe_ctx, 920 dc->res_pool->pipe_count, 921 &context->bw_ctx.bw.dce)) 922 result = true; 923 924 if (!result) 925 DC_LOG_BANDWIDTH_VALIDATION("%s: %dx%d@%d Bandwidth validation failed!\n", 926 __func__, 927 context->streams[0]->timing.h_addressable, 928 context->streams[0]->timing.v_addressable, 929 context->streams[0]->timing.pix_clk_100hz / 10); 930 931 if (memcmp(&dc->current_state->bw_ctx.bw.dce, 932 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { 933 934 DC_LOG_BANDWIDTH_CALCS( 935 "%s: finish,\n" 936 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 937 "stutMark_b: %d stutMark_a: %d\n" 938 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 939 "stutMark_b: %d stutMark_a: %d\n" 940 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 941 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n" 942 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" 943 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n" 944 , 945 __func__, 946 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark, 947 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark, 948 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, 949 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, 950 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark, 951 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark, 952 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark, 953 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark, 954 context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark, 955 context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark, 956 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark, 957 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark, 958 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark, 959 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark, 960 context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark, 961 context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark, 962 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark, 963 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark, 964 context->bw_ctx.bw.dce.stutter_mode_enable, 965 context->bw_ctx.bw.dce.cpuc_state_change_enable, 966 context->bw_ctx.bw.dce.cpup_state_change_enable, 967 context->bw_ctx.bw.dce.nbp_state_change_enable, 968 context->bw_ctx.bw.dce.all_displays_in_sync, 969 context->bw_ctx.bw.dce.dispclk_khz, 970 context->bw_ctx.bw.dce.sclk_khz, 971 context->bw_ctx.bw.dce.sclk_deep_sleep_khz, 972 context->bw_ctx.bw.dce.yclk_khz, 973 context->bw_ctx.bw.dce.blackout_recovery_time_us); 974 } 975 return result; 976 } 977 978 enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state, 979 struct dc_caps *caps) 980 { 981 if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) || 982 ((plane_state->dst_rect.height * 2) < plane_state->src_rect.height)) 983 return DC_FAIL_SURFACE_VALIDATE; 984 985 return DC_OK; 986 } 987 988 static bool dce110_validate_surface_sets( 989 struct dc_state *context) 990 { 991 int i, j; 992 993 for (i = 0; i < context->stream_count; i++) { 994 if (context->stream_status[i].plane_count == 0) 995 continue; 996 997 if (context->stream_status[i].plane_count > 2) 998 return false; 999 1000 for (j = 0; j < context->stream_status[i].plane_count; j++) { 1001 struct dc_plane_state *plane = 1002 context->stream_status[i].plane_states[j]; 1003 1004 /* underlay validation */ 1005 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 1006 1007 if ((plane->src_rect.width > 1920 || 1008 plane->src_rect.height > 1080)) 1009 return false; 1010 1011 /* we don't have the logic to support underlay 1012 * only yet so block the use case where we get 1013 * NV12 plane as top layer 1014 */ 1015 if (j == 0) 1016 return false; 1017 1018 /* irrespective of plane format, 1019 * stream should be RGB encoded 1020 */ 1021 if (context->streams[i]->timing.pixel_encoding 1022 != PIXEL_ENCODING_RGB) 1023 return false; 1024 1025 } 1026 1027 } 1028 } 1029 1030 return true; 1031 } 1032 1033 enum dc_status dce110_validate_global( 1034 struct dc *dc, 1035 struct dc_state *context) 1036 { 1037 if (!dce110_validate_surface_sets(context)) 1038 return DC_FAIL_SURFACE_VALIDATE; 1039 1040 return DC_OK; 1041 } 1042 1043 static enum dc_status dce110_add_stream_to_ctx( 1044 struct dc *dc, 1045 struct dc_state *new_ctx, 1046 struct dc_stream_state *dc_stream) 1047 { 1048 enum dc_status result = DC_ERROR_UNEXPECTED; 1049 1050 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1051 1052 if (result == DC_OK) 1053 result = resource_map_clock_resources(dc, new_ctx, dc_stream); 1054 1055 1056 if (result == DC_OK) 1057 result = build_mapped_resource(dc, new_ctx, dc_stream); 1058 1059 return result; 1060 } 1061 1062 static struct pipe_ctx *dce110_acquire_underlay( 1063 struct dc_state *context, 1064 const struct resource_pool *pool, 1065 struct dc_stream_state *stream) 1066 { 1067 struct dc *dc = stream->ctx->dc; 1068 struct resource_context *res_ctx = &context->res_ctx; 1069 unsigned int underlay_idx = pool->underlay_pipe_index; 1070 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; 1071 1072 if (res_ctx->pipe_ctx[underlay_idx].stream) 1073 return NULL; 1074 1075 pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx]; 1076 pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; 1077 /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/ 1078 pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; 1079 pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; 1080 pipe_ctx->pipe_idx = underlay_idx; 1081 1082 pipe_ctx->stream = stream; 1083 1084 if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) { 1085 struct tg_color black_color = {0}; 1086 struct dc_bios *dcb = dc->ctx->dc_bios; 1087 1088 dc->hwss.enable_display_power_gating( 1089 dc, 1090 pipe_ctx->stream_res.tg->inst, 1091 dcb, PIPE_GATING_CONTROL_DISABLE); 1092 1093 /* 1094 * This is for powering on underlay, so crtc does not 1095 * need to be enabled 1096 */ 1097 1098 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg, 1099 &stream->timing, 1100 false); 1101 1102 pipe_ctx->stream_res.tg->funcs->enable_advanced_request( 1103 pipe_ctx->stream_res.tg, 1104 true, 1105 &stream->timing); 1106 1107 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi, 1108 stream->timing.h_total, 1109 stream->timing.v_total, 1110 stream->timing.pix_clk_100hz / 10, 1111 context->stream_count); 1112 1113 color_space_to_black_color(dc, 1114 COLOR_SPACE_YCBCR601, &black_color); 1115 pipe_ctx->stream_res.tg->funcs->set_blank_color( 1116 pipe_ctx->stream_res.tg, 1117 &black_color); 1118 } 1119 1120 return pipe_ctx; 1121 } 1122 1123 static void dce110_destroy_resource_pool(struct resource_pool **pool) 1124 { 1125 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 1126 1127 destruct(dce110_pool); 1128 kfree(dce110_pool); 1129 *pool = NULL; 1130 } 1131 1132 1133 static const struct resource_funcs dce110_res_pool_funcs = { 1134 .destroy = dce110_destroy_resource_pool, 1135 .link_enc_create = dce110_link_encoder_create, 1136 .validate_bandwidth = dce110_validate_bandwidth, 1137 .validate_plane = dce110_validate_plane, 1138 .acquire_idle_pipe_for_layer = dce110_acquire_underlay, 1139 .add_stream_to_ctx = dce110_add_stream_to_ctx, 1140 .validate_global = dce110_validate_global 1141 }; 1142 1143 static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) 1144 { 1145 struct dce110_timing_generator *dce110_tgv = kzalloc(sizeof(*dce110_tgv), 1146 GFP_KERNEL); 1147 struct dce_transform *dce110_xfmv = kzalloc(sizeof(*dce110_xfmv), 1148 GFP_KERNEL); 1149 struct dce_mem_input *dce110_miv = kzalloc(sizeof(*dce110_miv), 1150 GFP_KERNEL); 1151 struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv), 1152 GFP_KERNEL); 1153 1154 if (!dce110_tgv || !dce110_xfmv || !dce110_miv || !dce110_oppv) { 1155 kfree(dce110_tgv); 1156 kfree(dce110_xfmv); 1157 kfree(dce110_miv); 1158 kfree(dce110_oppv); 1159 return false; 1160 } 1161 1162 dce110_opp_v_construct(dce110_oppv, ctx); 1163 1164 dce110_timing_generator_v_construct(dce110_tgv, ctx); 1165 dce110_mem_input_v_construct(dce110_miv, ctx); 1166 dce110_transform_v_construct(dce110_xfmv, ctx); 1167 1168 pool->opps[pool->pipe_count] = &dce110_oppv->base; 1169 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; 1170 pool->mis[pool->pipe_count] = &dce110_miv->base; 1171 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; 1172 pool->pipe_count++; 1173 1174 /* update the public caps to indicate an underlay is available */ 1175 ctx->dc->caps.max_slave_planes = 1; 1176 ctx->dc->caps.max_slave_planes = 1; 1177 1178 return true; 1179 } 1180 1181 static void bw_calcs_data_update_from_pplib(struct dc *dc) 1182 { 1183 struct dm_pp_clock_levels clks = {0}; 1184 1185 /*do system clock*/ 1186 dm_pp_get_clock_levels_by_type( 1187 dc->ctx, 1188 DM_PP_CLOCK_TYPE_ENGINE_CLK, 1189 &clks); 1190 /* convert all the clock fro kHz to fix point mHz */ 1191 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 1192 clks.clocks_in_khz[clks.num_levels-1], 1000); 1193 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 1194 clks.clocks_in_khz[clks.num_levels/8], 1000); 1195 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 1196 clks.clocks_in_khz[clks.num_levels*2/8], 1000); 1197 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 1198 clks.clocks_in_khz[clks.num_levels*3/8], 1000); 1199 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 1200 clks.clocks_in_khz[clks.num_levels*4/8], 1000); 1201 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 1202 clks.clocks_in_khz[clks.num_levels*5/8], 1000); 1203 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1204 clks.clocks_in_khz[clks.num_levels*6/8], 1000); 1205 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1206 clks.clocks_in_khz[0], 1000); 1207 dc->sclk_lvls = clks; 1208 1209 /*do display clock*/ 1210 dm_pp_get_clock_levels_by_type( 1211 dc->ctx, 1212 DM_PP_CLOCK_TYPE_DISPLAY_CLK, 1213 &clks); 1214 dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed( 1215 clks.clocks_in_khz[clks.num_levels-1], 1000); 1216 dc->bw_vbios->mid_voltage_max_dispclk = bw_frc_to_fixed( 1217 clks.clocks_in_khz[clks.num_levels>>1], 1000); 1218 dc->bw_vbios->low_voltage_max_dispclk = bw_frc_to_fixed( 1219 clks.clocks_in_khz[0], 1000); 1220 1221 /*do memory clock*/ 1222 dm_pp_get_clock_levels_by_type( 1223 dc->ctx, 1224 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1225 &clks); 1226 1227 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1228 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER_CZ, 1000); 1229 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1230 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ, 1231 1000); 1232 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1233 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER_CZ, 1234 1000); 1235 } 1236 1237 const struct resource_caps *dce110_resource_cap( 1238 struct hw_asic_id *asic_id) 1239 { 1240 if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev)) 1241 return &stoney_resource_cap; 1242 else 1243 return &carrizo_resource_cap; 1244 } 1245 1246 static bool construct( 1247 uint8_t num_virtual_links, 1248 struct dc *dc, 1249 struct dce110_resource_pool *pool, 1250 struct hw_asic_id asic_id) 1251 { 1252 unsigned int i; 1253 struct dc_context *ctx = dc->ctx; 1254 struct dc_firmware_info info; 1255 struct dc_bios *bp; 1256 1257 ctx->dc_bios->regs = &bios_regs; 1258 1259 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); 1260 pool->base.funcs = &dce110_res_pool_funcs; 1261 1262 /************************************************* 1263 * Resource + asic cap harcoding * 1264 *************************************************/ 1265 1266 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1267 pool->base.underlay_pipe_index = pool->base.pipe_count; 1268 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1269 dc->caps.max_downscale_ratio = 150; 1270 dc->caps.i2c_speed_in_khz = 100; 1271 dc->caps.max_cursor_size = 128; 1272 dc->caps.is_apu = true; 1273 1274 /************************************************* 1275 * Create resources * 1276 *************************************************/ 1277 1278 bp = ctx->dc_bios; 1279 1280 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1281 info.external_clock_source_frequency_for_dp != 0) { 1282 pool->base.dp_clock_source = 1283 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1284 1285 pool->base.clock_sources[0] = 1286 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, 1287 &clk_src_regs[0], false); 1288 pool->base.clock_sources[1] = 1289 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, 1290 &clk_src_regs[1], false); 1291 1292 pool->base.clk_src_count = 2; 1293 1294 /* TODO: find out if CZ support 3 PLLs */ 1295 } 1296 1297 if (pool->base.dp_clock_source == NULL) { 1298 dm_error("DC: failed to create dp clock source!\n"); 1299 BREAK_TO_DEBUGGER(); 1300 goto res_create_fail; 1301 } 1302 1303 for (i = 0; i < pool->base.clk_src_count; i++) { 1304 if (pool->base.clock_sources[i] == NULL) { 1305 dm_error("DC: failed to create clock sources!\n"); 1306 BREAK_TO_DEBUGGER(); 1307 goto res_create_fail; 1308 } 1309 } 1310 1311 pool->base.clk_mgr = dce110_clk_mgr_create(ctx, 1312 &disp_clk_regs, 1313 &disp_clk_shift, 1314 &disp_clk_mask); 1315 if (pool->base.clk_mgr == NULL) { 1316 dm_error("DC: failed to create display clock!\n"); 1317 BREAK_TO_DEBUGGER(); 1318 goto res_create_fail; 1319 } 1320 1321 pool->base.dmcu = dce_dmcu_create(ctx, 1322 &dmcu_regs, 1323 &dmcu_shift, 1324 &dmcu_mask); 1325 if (pool->base.dmcu == NULL) { 1326 dm_error("DC: failed to create dmcu!\n"); 1327 BREAK_TO_DEBUGGER(); 1328 goto res_create_fail; 1329 } 1330 1331 pool->base.abm = dce_abm_create(ctx, 1332 &abm_regs, 1333 &abm_shift, 1334 &abm_mask); 1335 if (pool->base.abm == NULL) { 1336 dm_error("DC: failed to create abm!\n"); 1337 BREAK_TO_DEBUGGER(); 1338 goto res_create_fail; 1339 } 1340 1341 { 1342 struct irq_service_init_data init_data; 1343 init_data.ctx = dc->ctx; 1344 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 1345 if (!pool->base.irqs) 1346 goto res_create_fail; 1347 } 1348 1349 for (i = 0; i < pool->base.pipe_count; i++) { 1350 pool->base.timing_generators[i] = dce110_timing_generator_create( 1351 ctx, i, &dce110_tg_offsets[i]); 1352 if (pool->base.timing_generators[i] == NULL) { 1353 BREAK_TO_DEBUGGER(); 1354 dm_error("DC: failed to create tg!\n"); 1355 goto res_create_fail; 1356 } 1357 1358 pool->base.mis[i] = dce110_mem_input_create(ctx, i); 1359 if (pool->base.mis[i] == NULL) { 1360 BREAK_TO_DEBUGGER(); 1361 dm_error( 1362 "DC: failed to create memory input!\n"); 1363 goto res_create_fail; 1364 } 1365 1366 pool->base.ipps[i] = dce110_ipp_create(ctx, i); 1367 if (pool->base.ipps[i] == NULL) { 1368 BREAK_TO_DEBUGGER(); 1369 dm_error( 1370 "DC: failed to create input pixel processor!\n"); 1371 goto res_create_fail; 1372 } 1373 1374 pool->base.transforms[i] = dce110_transform_create(ctx, i); 1375 if (pool->base.transforms[i] == NULL) { 1376 BREAK_TO_DEBUGGER(); 1377 dm_error( 1378 "DC: failed to create transform!\n"); 1379 goto res_create_fail; 1380 } 1381 1382 pool->base.opps[i] = dce110_opp_create(ctx, i); 1383 if (pool->base.opps[i] == NULL) { 1384 BREAK_TO_DEBUGGER(); 1385 dm_error( 1386 "DC: failed to create output pixel processor!\n"); 1387 goto res_create_fail; 1388 } 1389 } 1390 1391 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1392 pool->base.engines[i] = dce110_aux_engine_create(ctx, i); 1393 if (pool->base.engines[i] == NULL) { 1394 BREAK_TO_DEBUGGER(); 1395 dm_error( 1396 "DC:failed to create aux engine!!\n"); 1397 goto res_create_fail; 1398 } 1399 pool->base.hw_i2cs[i] = dce110_i2c_hw_create(ctx, i); 1400 if (pool->base.hw_i2cs[i] == NULL) { 1401 BREAK_TO_DEBUGGER(); 1402 dm_error( 1403 "DC:failed to create i2c engine!!\n"); 1404 goto res_create_fail; 1405 } 1406 pool->base.sw_i2cs[i] = NULL; 1407 } 1408 1409 if (dc->config.fbc_support) 1410 dc->fbc_compressor = dce110_compressor_create(ctx); 1411 1412 if (!underlay_create(ctx, &pool->base)) 1413 goto res_create_fail; 1414 1415 if (!resource_construct(num_virtual_links, dc, &pool->base, 1416 &res_create_funcs)) 1417 goto res_create_fail; 1418 1419 /* Create hardware sequencer */ 1420 dce110_hw_sequencer_construct(dc); 1421 1422 dc->caps.max_planes = pool->base.pipe_count; 1423 1424 for (i = 0; i < pool->base.underlay_pipe_index; ++i) 1425 dc->caps.planes[i] = plane_cap; 1426 1427 dc->caps.planes[pool->base.underlay_pipe_index] = underlay_plane_cap; 1428 1429 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1430 1431 bw_calcs_data_update_from_pplib(dc); 1432 1433 return true; 1434 1435 res_create_fail: 1436 destruct(pool); 1437 return false; 1438 } 1439 1440 struct resource_pool *dce110_create_resource_pool( 1441 uint8_t num_virtual_links, 1442 struct dc *dc, 1443 struct hw_asic_id asic_id) 1444 { 1445 struct dce110_resource_pool *pool = 1446 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1447 1448 if (!pool) 1449 return NULL; 1450 1451 if (construct(num_virtual_links, dc, pool, asic_id)) 1452 return &pool->base; 1453 1454 BREAK_TO_DEBUGGER(); 1455 return NULL; 1456 } 1457