1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "link_encoder.h" 29 #include "stream_encoder.h" 30 31 #include "resource.h" 32 #include "dce110/dce110_resource.h" 33 34 #include "include/irq_service_interface.h" 35 #include "dce/dce_audio.h" 36 #include "dce110/dce110_timing_generator.h" 37 #include "irq/dce110/irq_service_dce110.h" 38 #include "dce110/dce110_timing_generator_v.h" 39 #include "dce/dce_link_encoder.h" 40 #include "dce/dce_stream_encoder.h" 41 #include "dce/dce_mem_input.h" 42 #include "dce110/dce110_mem_input_v.h" 43 #include "dce/dce_ipp.h" 44 #include "dce/dce_transform.h" 45 #include "dce110/dce110_transform_v.h" 46 #include "dce/dce_opp.h" 47 #include "dce110/dce110_opp_v.h" 48 #include "dce/dce_clocks.h" 49 #include "dce/dce_clock_source.h" 50 #include "dce/dce_hwseq.h" 51 #include "dce110/dce110_hw_sequencer.h" 52 #include "dce/dce_abm.h" 53 #include "dce/dce_dmcu.h" 54 55 #ifdef ENABLE_FBC 56 #include "dce110/dce110_compressor.h" 57 #endif 58 59 #include "reg_helper.h" 60 61 #include "dce/dce_11_0_d.h" 62 #include "dce/dce_11_0_sh_mask.h" 63 64 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 65 #include "gmc/gmc_8_2_d.h" 66 #include "gmc/gmc_8_2_sh_mask.h" 67 #endif 68 69 #ifndef mmDP_DPHY_INTERNAL_CTRL 70 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 71 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 72 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 73 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 74 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 75 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 76 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 77 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 78 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 79 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 80 #endif 81 82 #ifndef mmBIOS_SCRATCH_2 83 #define mmBIOS_SCRATCH_2 0x05CB 84 #define mmBIOS_SCRATCH_6 0x05CF 85 #endif 86 87 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 88 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 89 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 90 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 91 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 92 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 93 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 94 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 95 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 96 #endif 97 98 #ifndef mmDP_DPHY_FAST_TRAINING 99 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 100 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 101 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 102 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 103 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 104 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 105 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 106 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 107 #endif 108 109 #ifndef DPHY_RX_FAST_TRAINING_CAPABLE 110 #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1 111 #endif 112 113 static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = { 114 { 115 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 116 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 117 }, 118 { 119 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 120 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 121 }, 122 { 123 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 124 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 125 }, 126 { 127 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 128 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 129 }, 130 { 131 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 132 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 133 }, 134 { 135 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 136 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 137 } 138 }; 139 140 /* set register offset */ 141 #define SR(reg_name)\ 142 .reg_name = mm ## reg_name 143 144 /* set register offset with instance */ 145 #define SRI(reg_name, block, id)\ 146 .reg_name = mm ## block ## id ## _ ## reg_name 147 148 static const struct dce_disp_clk_registers disp_clk_regs = { 149 CLK_COMMON_REG_LIST_DCE_BASE() 150 }; 151 152 static const struct dce_disp_clk_shift disp_clk_shift = { 153 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 154 }; 155 156 static const struct dce_disp_clk_mask disp_clk_mask = { 157 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 158 }; 159 160 static const struct dce_dmcu_registers dmcu_regs = { 161 DMCU_DCE110_COMMON_REG_LIST() 162 }; 163 164 static const struct dce_dmcu_shift dmcu_shift = { 165 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 166 }; 167 168 static const struct dce_dmcu_mask dmcu_mask = { 169 DMCU_MASK_SH_LIST_DCE110(_MASK) 170 }; 171 172 static const struct dce_abm_registers abm_regs = { 173 ABM_DCE110_COMMON_REG_LIST() 174 }; 175 176 static const struct dce_abm_shift abm_shift = { 177 ABM_MASK_SH_LIST_DCE110(__SHIFT) 178 }; 179 180 static const struct dce_abm_mask abm_mask = { 181 ABM_MASK_SH_LIST_DCE110(_MASK) 182 }; 183 184 #define ipp_regs(id)\ 185 [id] = {\ 186 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 187 } 188 189 static const struct dce_ipp_registers ipp_regs[] = { 190 ipp_regs(0), 191 ipp_regs(1), 192 ipp_regs(2) 193 }; 194 195 static const struct dce_ipp_shift ipp_shift = { 196 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 197 }; 198 199 static const struct dce_ipp_mask ipp_mask = { 200 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 201 }; 202 203 #define transform_regs(id)\ 204 [id] = {\ 205 XFM_COMMON_REG_LIST_DCE110(id)\ 206 } 207 208 static const struct dce_transform_registers xfm_regs[] = { 209 transform_regs(0), 210 transform_regs(1), 211 transform_regs(2) 212 }; 213 214 static const struct dce_transform_shift xfm_shift = { 215 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 216 }; 217 218 static const struct dce_transform_mask xfm_mask = { 219 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 220 }; 221 222 #define aux_regs(id)\ 223 [id] = {\ 224 AUX_REG_LIST(id)\ 225 } 226 227 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 228 aux_regs(0), 229 aux_regs(1), 230 aux_regs(2), 231 aux_regs(3), 232 aux_regs(4), 233 aux_regs(5) 234 }; 235 236 #define hpd_regs(id)\ 237 [id] = {\ 238 HPD_REG_LIST(id)\ 239 } 240 241 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 242 hpd_regs(0), 243 hpd_regs(1), 244 hpd_regs(2), 245 hpd_regs(3), 246 hpd_regs(4), 247 hpd_regs(5) 248 }; 249 250 251 #define link_regs(id)\ 252 [id] = {\ 253 LE_DCE110_REG_LIST(id)\ 254 } 255 256 static const struct dce110_link_enc_registers link_enc_regs[] = { 257 link_regs(0), 258 link_regs(1), 259 link_regs(2), 260 link_regs(3), 261 link_regs(4), 262 link_regs(5), 263 link_regs(6), 264 }; 265 266 #define stream_enc_regs(id)\ 267 [id] = {\ 268 SE_COMMON_REG_LIST(id),\ 269 .TMDS_CNTL = 0,\ 270 } 271 272 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 273 stream_enc_regs(0), 274 stream_enc_regs(1), 275 stream_enc_regs(2) 276 }; 277 278 static const struct dce_stream_encoder_shift se_shift = { 279 SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 280 }; 281 282 static const struct dce_stream_encoder_mask se_mask = { 283 SE_COMMON_MASK_SH_LIST_DCE110(_MASK) 284 }; 285 286 #define opp_regs(id)\ 287 [id] = {\ 288 OPP_DCE_110_REG_LIST(id),\ 289 } 290 291 static const struct dce_opp_registers opp_regs[] = { 292 opp_regs(0), 293 opp_regs(1), 294 opp_regs(2), 295 opp_regs(3), 296 opp_regs(4), 297 opp_regs(5) 298 }; 299 300 static const struct dce_opp_shift opp_shift = { 301 OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT) 302 }; 303 304 static const struct dce_opp_mask opp_mask = { 305 OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK) 306 }; 307 308 #define audio_regs(id)\ 309 [id] = {\ 310 AUD_COMMON_REG_LIST(id)\ 311 } 312 313 static const struct dce_audio_registers audio_regs[] = { 314 audio_regs(0), 315 audio_regs(1), 316 audio_regs(2), 317 audio_regs(3), 318 audio_regs(4), 319 audio_regs(5), 320 audio_regs(6), 321 }; 322 323 static const struct dce_audio_shift audio_shift = { 324 AUD_COMMON_MASK_SH_LIST(__SHIFT) 325 }; 326 327 static const struct dce_aduio_mask audio_mask = { 328 AUD_COMMON_MASK_SH_LIST(_MASK) 329 }; 330 331 /* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */ 332 333 334 #define clk_src_regs(id)\ 335 [id] = {\ 336 CS_COMMON_REG_LIST_DCE_100_110(id),\ 337 } 338 339 static const struct dce110_clk_src_regs clk_src_regs[] = { 340 clk_src_regs(0), 341 clk_src_regs(1), 342 clk_src_regs(2) 343 }; 344 345 static const struct dce110_clk_src_shift cs_shift = { 346 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 347 }; 348 349 static const struct dce110_clk_src_mask cs_mask = { 350 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 351 }; 352 353 static const struct bios_registers bios_regs = { 354 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 355 }; 356 357 static const struct resource_caps carrizo_resource_cap = { 358 .num_timing_generator = 3, 359 .num_video_plane = 1, 360 .num_audio = 3, 361 .num_stream_encoder = 3, 362 .num_pll = 2, 363 }; 364 365 static const struct resource_caps stoney_resource_cap = { 366 .num_timing_generator = 2, 367 .num_video_plane = 1, 368 .num_audio = 3, 369 .num_stream_encoder = 3, 370 .num_pll = 2, 371 }; 372 373 #define CTX ctx 374 #define REG(reg) mm ## reg 375 376 #ifndef mmCC_DC_HDMI_STRAPS 377 #define mmCC_DC_HDMI_STRAPS 0x4819 378 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 379 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 380 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 381 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 382 #endif 383 384 static void read_dce_straps( 385 struct dc_context *ctx, 386 struct resource_straps *straps) 387 { 388 REG_GET_2(CC_DC_HDMI_STRAPS, 389 HDMI_DISABLE, &straps->hdmi_disable, 390 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 391 392 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 393 } 394 395 static struct audio *create_audio( 396 struct dc_context *ctx, unsigned int inst) 397 { 398 return dce_audio_create(ctx, inst, 399 &audio_regs[inst], &audio_shift, &audio_mask); 400 } 401 402 static struct timing_generator *dce110_timing_generator_create( 403 struct dc_context *ctx, 404 uint32_t instance, 405 const struct dce110_timing_generator_offsets *offsets) 406 { 407 struct dce110_timing_generator *tg110 = 408 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 409 410 if (!tg110) 411 return NULL; 412 413 if (dce110_timing_generator_construct(tg110, ctx, instance, offsets)) 414 return &tg110->base; 415 416 BREAK_TO_DEBUGGER(); 417 kfree(tg110); 418 return NULL; 419 } 420 421 static struct stream_encoder *dce110_stream_encoder_create( 422 enum engine_id eng_id, 423 struct dc_context *ctx) 424 { 425 struct dce110_stream_encoder *enc110 = 426 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 427 428 if (!enc110) 429 return NULL; 430 431 if (dce110_stream_encoder_construct( 432 enc110, ctx, ctx->dc_bios, eng_id, 433 &stream_enc_regs[eng_id], &se_shift, &se_mask)) 434 return &enc110->base; 435 436 BREAK_TO_DEBUGGER(); 437 kfree(enc110); 438 return NULL; 439 } 440 441 #define SRII(reg_name, block, id)\ 442 .reg_name[id] = mm ## block ## id ## _ ## reg_name 443 444 static const struct dce_hwseq_registers hwseq_stoney_reg = { 445 HWSEQ_ST_REG_LIST() 446 }; 447 448 static const struct dce_hwseq_registers hwseq_cz_reg = { 449 HWSEQ_CZ_REG_LIST() 450 }; 451 452 static const struct dce_hwseq_shift hwseq_shift = { 453 HWSEQ_DCE11_MASK_SH_LIST(__SHIFT), 454 }; 455 456 static const struct dce_hwseq_mask hwseq_mask = { 457 HWSEQ_DCE11_MASK_SH_LIST(_MASK), 458 }; 459 460 static struct dce_hwseq *dce110_hwseq_create( 461 struct dc_context *ctx) 462 { 463 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 464 465 if (hws) { 466 hws->ctx = ctx; 467 hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ? 468 &hwseq_stoney_reg : &hwseq_cz_reg; 469 hws->shifts = &hwseq_shift; 470 hws->masks = &hwseq_mask; 471 hws->wa.blnd_crtc_trigger = true; 472 } 473 return hws; 474 } 475 476 static const struct resource_create_funcs res_create_funcs = { 477 .read_dce_straps = read_dce_straps, 478 .create_audio = create_audio, 479 .create_stream_encoder = dce110_stream_encoder_create, 480 .create_hwseq = dce110_hwseq_create, 481 }; 482 483 #define mi_inst_regs(id) { \ 484 MI_DCE11_REG_LIST(id), \ 485 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 486 } 487 static const struct dce_mem_input_registers mi_regs[] = { 488 mi_inst_regs(0), 489 mi_inst_regs(1), 490 mi_inst_regs(2), 491 }; 492 493 static const struct dce_mem_input_shift mi_shifts = { 494 MI_DCE11_MASK_SH_LIST(__SHIFT), 495 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 496 }; 497 498 static const struct dce_mem_input_mask mi_masks = { 499 MI_DCE11_MASK_SH_LIST(_MASK), 500 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 501 }; 502 503 504 static struct mem_input *dce110_mem_input_create( 505 struct dc_context *ctx, 506 uint32_t inst) 507 { 508 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 509 GFP_KERNEL); 510 511 if (!dce_mi) { 512 BREAK_TO_DEBUGGER(); 513 return NULL; 514 } 515 516 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 517 dce_mi->wa.single_head_rdreq_dmif_limit = 3; 518 return &dce_mi->base; 519 } 520 521 static void dce110_transform_destroy(struct transform **xfm) 522 { 523 kfree(TO_DCE_TRANSFORM(*xfm)); 524 *xfm = NULL; 525 } 526 527 static struct transform *dce110_transform_create( 528 struct dc_context *ctx, 529 uint32_t inst) 530 { 531 struct dce_transform *transform = 532 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 533 534 if (!transform) 535 return NULL; 536 537 if (dce_transform_construct(transform, ctx, inst, 538 &xfm_regs[inst], &xfm_shift, &xfm_mask)) 539 return &transform->base; 540 541 BREAK_TO_DEBUGGER(); 542 kfree(transform); 543 return NULL; 544 } 545 546 static struct input_pixel_processor *dce110_ipp_create( 547 struct dc_context *ctx, uint32_t inst) 548 { 549 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 550 551 if (!ipp) { 552 BREAK_TO_DEBUGGER(); 553 return NULL; 554 } 555 556 dce_ipp_construct(ipp, ctx, inst, 557 &ipp_regs[inst], &ipp_shift, &ipp_mask); 558 return &ipp->base; 559 } 560 561 static const struct encoder_feature_support link_enc_feature = { 562 .max_hdmi_deep_color = COLOR_DEPTH_121212, 563 .max_hdmi_pixel_clock = 594000, 564 .flags.bits.IS_HBR2_CAPABLE = true, 565 .flags.bits.IS_TPS3_CAPABLE = true, 566 .flags.bits.IS_YCBCR_CAPABLE = true 567 }; 568 569 static struct link_encoder *dce110_link_encoder_create( 570 const struct encoder_init_data *enc_init_data) 571 { 572 struct dce110_link_encoder *enc110 = 573 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 574 575 if (!enc110) 576 return NULL; 577 578 if (dce110_link_encoder_construct( 579 enc110, 580 enc_init_data, 581 &link_enc_feature, 582 &link_enc_regs[enc_init_data->transmitter], 583 &link_enc_aux_regs[enc_init_data->channel - 1], 584 &link_enc_hpd_regs[enc_init_data->hpd_source])) { 585 586 return &enc110->base; 587 } 588 589 BREAK_TO_DEBUGGER(); 590 kfree(enc110); 591 return NULL; 592 } 593 594 static struct output_pixel_processor *dce110_opp_create( 595 struct dc_context *ctx, 596 uint32_t inst) 597 { 598 struct dce110_opp *opp = 599 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 600 601 if (!opp) 602 return NULL; 603 604 if (dce110_opp_construct(opp, 605 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask)) 606 return &opp->base; 607 608 BREAK_TO_DEBUGGER(); 609 kfree(opp); 610 return NULL; 611 } 612 613 struct clock_source *dce110_clock_source_create( 614 struct dc_context *ctx, 615 struct dc_bios *bios, 616 enum clock_source_id id, 617 const struct dce110_clk_src_regs *regs, 618 bool dp_clk_src) 619 { 620 struct dce110_clk_src *clk_src = 621 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 622 623 if (!clk_src) 624 return NULL; 625 626 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 627 regs, &cs_shift, &cs_mask)) { 628 clk_src->base.dp_clk_src = dp_clk_src; 629 return &clk_src->base; 630 } 631 632 BREAK_TO_DEBUGGER(); 633 return NULL; 634 } 635 636 void dce110_clock_source_destroy(struct clock_source **clk_src) 637 { 638 struct dce110_clk_src *dce110_clk_src; 639 640 if (!clk_src) 641 return; 642 643 dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src); 644 645 if (dce110_clk_src->dp_ss_params) 646 kfree(dce110_clk_src->dp_ss_params); 647 648 if (dce110_clk_src->hdmi_ss_params) 649 kfree(dce110_clk_src->hdmi_ss_params); 650 651 if (dce110_clk_src->dvi_ss_params) 652 kfree(dce110_clk_src->dvi_ss_params); 653 654 kfree(dce110_clk_src); 655 *clk_src = NULL; 656 } 657 658 static void destruct(struct dce110_resource_pool *pool) 659 { 660 unsigned int i; 661 662 for (i = 0; i < pool->base.pipe_count; i++) { 663 if (pool->base.opps[i] != NULL) 664 dce110_opp_destroy(&pool->base.opps[i]); 665 666 if (pool->base.transforms[i] != NULL) 667 dce110_transform_destroy(&pool->base.transforms[i]); 668 669 if (pool->base.ipps[i] != NULL) 670 dce_ipp_destroy(&pool->base.ipps[i]); 671 672 if (pool->base.mis[i] != NULL) { 673 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 674 pool->base.mis[i] = NULL; 675 } 676 677 if (pool->base.timing_generators[i] != NULL) { 678 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 679 pool->base.timing_generators[i] = NULL; 680 } 681 } 682 683 for (i = 0; i < pool->base.stream_enc_count; i++) { 684 if (pool->base.stream_enc[i] != NULL) 685 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 686 } 687 688 for (i = 0; i < pool->base.clk_src_count; i++) { 689 if (pool->base.clock_sources[i] != NULL) { 690 dce110_clock_source_destroy(&pool->base.clock_sources[i]); 691 } 692 } 693 694 if (pool->base.dp_clock_source != NULL) 695 dce110_clock_source_destroy(&pool->base.dp_clock_source); 696 697 for (i = 0; i < pool->base.audio_count; i++) { 698 if (pool->base.audios[i] != NULL) { 699 dce_aud_destroy(&pool->base.audios[i]); 700 } 701 } 702 703 if (pool->base.abm != NULL) 704 dce_abm_destroy(&pool->base.abm); 705 706 if (pool->base.dmcu != NULL) 707 dce_dmcu_destroy(&pool->base.dmcu); 708 709 if (pool->base.display_clock != NULL) 710 dce_disp_clk_destroy(&pool->base.display_clock); 711 712 if (pool->base.irqs != NULL) { 713 dal_irq_service_destroy(&pool->base.irqs); 714 } 715 } 716 717 718 static void get_pixel_clock_parameters( 719 const struct pipe_ctx *pipe_ctx, 720 struct pixel_clk_params *pixel_clk_params) 721 { 722 const struct dc_stream_state *stream = pipe_ctx->stream; 723 724 /*TODO: is this halved for YCbCr 420? in that case we might want to move 725 * the pixel clock normalization for hdmi up to here instead of doing it 726 * in pll_adjust_pix_clk 727 */ 728 pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz; 729 pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id; 730 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 731 pixel_clk_params->controller_id = pipe_ctx->pipe_idx + 1; 732 /* TODO: un-hardcode*/ 733 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 734 LINK_RATE_REF_FREQ_IN_KHZ; 735 pixel_clk_params->flags.ENABLE_SS = 0; 736 pixel_clk_params->color_depth = 737 stream->timing.display_color_depth; 738 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 739 pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding == 740 PIXEL_ENCODING_YCBCR420); 741 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 742 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) { 743 pixel_clk_params->color_depth = COLOR_DEPTH_888; 744 } 745 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 746 pixel_clk_params->requested_pix_clk = pixel_clk_params->requested_pix_clk / 2; 747 } 748 } 749 750 enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 751 { 752 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 753 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 754 pipe_ctx->clock_source, 755 &pipe_ctx->stream_res.pix_clk_params, 756 &pipe_ctx->pll_settings); 757 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 758 &pipe_ctx->stream->bit_depth_params); 759 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 760 761 return DC_OK; 762 } 763 764 static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx) 765 { 766 if (pipe_ctx->pipe_idx != underlay_idx) 767 return true; 768 if (!pipe_ctx->plane_state) 769 return false; 770 if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 771 return false; 772 return true; 773 } 774 775 static enum dc_status build_mapped_resource( 776 const struct dc *dc, 777 struct dc_state *context, 778 struct dc_stream_state *stream) 779 { 780 enum dc_status status = DC_OK; 781 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 782 783 if (!pipe_ctx) 784 return DC_ERROR_UNEXPECTED; 785 786 if (!is_surface_pixel_format_supported(pipe_ctx, 787 dc->res_pool->underlay_pipe_index)) 788 return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; 789 790 status = dce110_resource_build_pipe_hw_param(pipe_ctx); 791 792 if (status != DC_OK) 793 return status; 794 795 /* TODO: validate audio ASIC caps, encoder */ 796 797 resource_build_info_frame(pipe_ctx); 798 799 return DC_OK; 800 } 801 802 static bool dce110_validate_bandwidth( 803 struct dc *dc, 804 struct dc_state *context) 805 { 806 bool result = false; 807 808 dm_logger_write( 809 dc->ctx->logger, LOG_BANDWIDTH_CALCS, 810 "%s: start", 811 __func__); 812 813 if (bw_calcs( 814 dc->ctx, 815 dc->bw_dceip, 816 dc->bw_vbios, 817 context->res_ctx.pipe_ctx, 818 dc->res_pool->pipe_count, 819 &context->bw.dce)) 820 result = true; 821 822 if (!result) 823 dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION, 824 "%s: %dx%d@%d Bandwidth validation failed!\n", 825 __func__, 826 context->streams[0]->timing.h_addressable, 827 context->streams[0]->timing.v_addressable, 828 context->streams[0]->timing.pix_clk_khz); 829 830 if (memcmp(&dc->current_state->bw.dce, 831 &context->bw.dce, sizeof(context->bw.dce))) { 832 struct log_entry log_entry; 833 dm_logger_open( 834 dc->ctx->logger, 835 &log_entry, 836 LOG_BANDWIDTH_CALCS); 837 dm_logger_append(&log_entry, "%s: finish,\n" 838 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 839 "stutMark_b: %d stutMark_a: %d\n", 840 __func__, 841 context->bw.dce.nbp_state_change_wm_ns[0].b_mark, 842 context->bw.dce.nbp_state_change_wm_ns[0].a_mark, 843 context->bw.dce.urgent_wm_ns[0].b_mark, 844 context->bw.dce.urgent_wm_ns[0].a_mark, 845 context->bw.dce.stutter_exit_wm_ns[0].b_mark, 846 context->bw.dce.stutter_exit_wm_ns[0].a_mark); 847 dm_logger_append(&log_entry, 848 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 849 "stutMark_b: %d stutMark_a: %d\n", 850 context->bw.dce.nbp_state_change_wm_ns[1].b_mark, 851 context->bw.dce.nbp_state_change_wm_ns[1].a_mark, 852 context->bw.dce.urgent_wm_ns[1].b_mark, 853 context->bw.dce.urgent_wm_ns[1].a_mark, 854 context->bw.dce.stutter_exit_wm_ns[1].b_mark, 855 context->bw.dce.stutter_exit_wm_ns[1].a_mark); 856 dm_logger_append(&log_entry, 857 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 858 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n", 859 context->bw.dce.nbp_state_change_wm_ns[2].b_mark, 860 context->bw.dce.nbp_state_change_wm_ns[2].a_mark, 861 context->bw.dce.urgent_wm_ns[2].b_mark, 862 context->bw.dce.urgent_wm_ns[2].a_mark, 863 context->bw.dce.stutter_exit_wm_ns[2].b_mark, 864 context->bw.dce.stutter_exit_wm_ns[2].a_mark, 865 context->bw.dce.stutter_mode_enable); 866 dm_logger_append(&log_entry, 867 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" 868 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n", 869 context->bw.dce.cpuc_state_change_enable, 870 context->bw.dce.cpup_state_change_enable, 871 context->bw.dce.nbp_state_change_enable, 872 context->bw.dce.all_displays_in_sync, 873 context->bw.dce.dispclk_khz, 874 context->bw.dce.sclk_khz, 875 context->bw.dce.sclk_deep_sleep_khz, 876 context->bw.dce.yclk_khz, 877 context->bw.dce.blackout_recovery_time_us); 878 dm_logger_close(&log_entry); 879 } 880 return result; 881 } 882 883 static bool dce110_validate_surface_sets( 884 struct dc_state *context) 885 { 886 int i; 887 888 for (i = 0; i < context->stream_count; i++) { 889 if (context->stream_status[i].plane_count == 0) 890 continue; 891 892 if (context->stream_status[i].plane_count > 2) 893 return false; 894 895 if ((context->stream_status[i].plane_states[i]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) && 896 (context->stream_status[i].plane_states[i]->src_rect.width > 1920 || 897 context->stream_status[i].plane_states[i]->src_rect.height > 1080)) 898 return false; 899 900 /* irrespective of plane format, stream should be RGB encoded */ 901 if (context->streams[i]->timing.pixel_encoding != PIXEL_ENCODING_RGB) 902 return false; 903 } 904 905 return true; 906 } 907 908 enum dc_status dce110_validate_global( 909 struct dc *dc, 910 struct dc_state *context) 911 { 912 if (!dce110_validate_surface_sets(context)) 913 return DC_FAIL_SURFACE_VALIDATE; 914 915 return DC_OK; 916 } 917 918 static enum dc_status dce110_add_stream_to_ctx( 919 struct dc *dc, 920 struct dc_state *new_ctx, 921 struct dc_stream_state *dc_stream) 922 { 923 enum dc_status result = DC_ERROR_UNEXPECTED; 924 925 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 926 927 if (result == DC_OK) 928 result = resource_map_clock_resources(dc, new_ctx, dc_stream); 929 930 931 if (result == DC_OK) 932 result = build_mapped_resource(dc, new_ctx, dc_stream); 933 934 return result; 935 } 936 937 static enum dc_status dce110_validate_guaranteed( 938 struct dc *dc, 939 struct dc_stream_state *dc_stream, 940 struct dc_state *context) 941 { 942 enum dc_status result = DC_ERROR_UNEXPECTED; 943 944 context->streams[0] = dc_stream; 945 dc_stream_retain(context->streams[0]); 946 context->stream_count++; 947 948 result = resource_map_pool_resources(dc, context, dc_stream); 949 950 if (result == DC_OK) 951 result = resource_map_clock_resources(dc, context, dc_stream); 952 953 if (result == DC_OK) 954 result = build_mapped_resource(dc, context, dc_stream); 955 956 if (result == DC_OK) { 957 validate_guaranteed_copy_streams( 958 context, dc->caps.max_streams); 959 result = resource_build_scaling_params_for_context(dc, context); 960 } 961 962 if (result == DC_OK) 963 if (!dce110_validate_bandwidth(dc, context)) 964 result = DC_FAIL_BANDWIDTH_VALIDATE; 965 966 return result; 967 } 968 969 static struct pipe_ctx *dce110_acquire_underlay( 970 struct dc_state *context, 971 const struct resource_pool *pool, 972 struct dc_stream_state *stream) 973 { 974 struct dc *dc = stream->ctx->dc; 975 struct resource_context *res_ctx = &context->res_ctx; 976 unsigned int underlay_idx = pool->underlay_pipe_index; 977 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; 978 979 if (res_ctx->pipe_ctx[underlay_idx].stream) 980 return NULL; 981 982 pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx]; 983 pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; 984 /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/ 985 pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; 986 pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; 987 pipe_ctx->pipe_idx = underlay_idx; 988 989 pipe_ctx->stream = stream; 990 991 if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) { 992 struct tg_color black_color = {0}; 993 struct dc_bios *dcb = dc->ctx->dc_bios; 994 995 dc->hwss.enable_display_power_gating( 996 dc, 997 pipe_ctx->pipe_idx, 998 dcb, PIPE_GATING_CONTROL_DISABLE); 999 1000 /* 1001 * This is for powering on underlay, so crtc does not 1002 * need to be enabled 1003 */ 1004 1005 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg, 1006 &stream->timing, 1007 false); 1008 1009 pipe_ctx->stream_res.tg->funcs->enable_advanced_request( 1010 pipe_ctx->stream_res.tg, 1011 true, 1012 &stream->timing); 1013 1014 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi, 1015 stream->timing.h_total, 1016 stream->timing.v_total, 1017 stream->timing.pix_clk_khz, 1018 context->stream_count); 1019 1020 color_space_to_black_color(dc, 1021 COLOR_SPACE_YCBCR601, &black_color); 1022 pipe_ctx->stream_res.tg->funcs->set_blank_color( 1023 pipe_ctx->stream_res.tg, 1024 &black_color); 1025 } 1026 1027 return pipe_ctx; 1028 } 1029 1030 static void dce110_destroy_resource_pool(struct resource_pool **pool) 1031 { 1032 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 1033 1034 destruct(dce110_pool); 1035 kfree(dce110_pool); 1036 *pool = NULL; 1037 } 1038 1039 1040 static const struct resource_funcs dce110_res_pool_funcs = { 1041 .destroy = dce110_destroy_resource_pool, 1042 .link_enc_create = dce110_link_encoder_create, 1043 .validate_guaranteed = dce110_validate_guaranteed, 1044 .validate_bandwidth = dce110_validate_bandwidth, 1045 .acquire_idle_pipe_for_layer = dce110_acquire_underlay, 1046 .add_stream_to_ctx = dce110_add_stream_to_ctx, 1047 .validate_global = dce110_validate_global 1048 }; 1049 1050 static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) 1051 { 1052 struct dce110_timing_generator *dce110_tgv = kzalloc(sizeof(*dce110_tgv), 1053 GFP_KERNEL); 1054 struct dce_transform *dce110_xfmv = kzalloc(sizeof(*dce110_xfmv), 1055 GFP_KERNEL); 1056 struct dce_mem_input *dce110_miv = kzalloc(sizeof(*dce110_miv), 1057 GFP_KERNEL); 1058 struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv), 1059 GFP_KERNEL); 1060 1061 if ((dce110_tgv == NULL) || 1062 (dce110_xfmv == NULL) || 1063 (dce110_miv == NULL) || 1064 (dce110_oppv == NULL)) 1065 return false; 1066 1067 if (!dce110_opp_v_construct(dce110_oppv, ctx)) 1068 return false; 1069 1070 dce110_timing_generator_v_construct(dce110_tgv, ctx); 1071 dce110_mem_input_v_construct(dce110_miv, ctx); 1072 dce110_transform_v_construct(dce110_xfmv, ctx); 1073 1074 pool->opps[pool->pipe_count] = &dce110_oppv->base; 1075 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; 1076 pool->mis[pool->pipe_count] = &dce110_miv->base; 1077 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; 1078 pool->pipe_count++; 1079 1080 /* update the public caps to indicate an underlay is available */ 1081 ctx->dc->caps.max_slave_planes = 1; 1082 ctx->dc->caps.max_slave_planes = 1; 1083 1084 return true; 1085 } 1086 1087 static void bw_calcs_data_update_from_pplib(struct dc *dc) 1088 { 1089 struct dm_pp_clock_levels clks = {0}; 1090 1091 /*do system clock*/ 1092 dm_pp_get_clock_levels_by_type( 1093 dc->ctx, 1094 DM_PP_CLOCK_TYPE_ENGINE_CLK, 1095 &clks); 1096 /* convert all the clock fro kHz to fix point mHz */ 1097 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 1098 clks.clocks_in_khz[clks.num_levels-1], 1000); 1099 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 1100 clks.clocks_in_khz[clks.num_levels/8], 1000); 1101 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 1102 clks.clocks_in_khz[clks.num_levels*2/8], 1000); 1103 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 1104 clks.clocks_in_khz[clks.num_levels*3/8], 1000); 1105 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 1106 clks.clocks_in_khz[clks.num_levels*4/8], 1000); 1107 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 1108 clks.clocks_in_khz[clks.num_levels*5/8], 1000); 1109 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1110 clks.clocks_in_khz[clks.num_levels*6/8], 1000); 1111 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1112 clks.clocks_in_khz[0], 1000); 1113 dc->sclk_lvls = clks; 1114 1115 /*do display clock*/ 1116 dm_pp_get_clock_levels_by_type( 1117 dc->ctx, 1118 DM_PP_CLOCK_TYPE_DISPLAY_CLK, 1119 &clks); 1120 dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed( 1121 clks.clocks_in_khz[clks.num_levels-1], 1000); 1122 dc->bw_vbios->mid_voltage_max_dispclk = bw_frc_to_fixed( 1123 clks.clocks_in_khz[clks.num_levels>>1], 1000); 1124 dc->bw_vbios->low_voltage_max_dispclk = bw_frc_to_fixed( 1125 clks.clocks_in_khz[0], 1000); 1126 1127 /*do memory clock*/ 1128 dm_pp_get_clock_levels_by_type( 1129 dc->ctx, 1130 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1131 &clks); 1132 1133 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1134 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000); 1135 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1136 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER, 1137 1000); 1138 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1139 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER, 1140 1000); 1141 } 1142 1143 const struct resource_caps *dce110_resource_cap( 1144 struct hw_asic_id *asic_id) 1145 { 1146 if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev)) 1147 return &stoney_resource_cap; 1148 else 1149 return &carrizo_resource_cap; 1150 } 1151 1152 static bool construct( 1153 uint8_t num_virtual_links, 1154 struct dc *dc, 1155 struct dce110_resource_pool *pool, 1156 struct hw_asic_id asic_id) 1157 { 1158 unsigned int i; 1159 struct dc_context *ctx = dc->ctx; 1160 struct dc_firmware_info info; 1161 struct dc_bios *bp; 1162 struct dm_pp_static_clock_info static_clk_info = {0}; 1163 1164 ctx->dc_bios->regs = &bios_regs; 1165 1166 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); 1167 pool->base.funcs = &dce110_res_pool_funcs; 1168 1169 /************************************************* 1170 * Resource + asic cap harcoding * 1171 *************************************************/ 1172 1173 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1174 pool->base.underlay_pipe_index = pool->base.pipe_count; 1175 1176 dc->caps.max_downscale_ratio = 150; 1177 dc->caps.i2c_speed_in_khz = 100; 1178 dc->caps.max_cursor_size = 128; 1179 1180 /************************************************* 1181 * Create resources * 1182 *************************************************/ 1183 1184 bp = ctx->dc_bios; 1185 1186 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1187 info.external_clock_source_frequency_for_dp != 0) { 1188 pool->base.dp_clock_source = 1189 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1190 1191 pool->base.clock_sources[0] = 1192 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, 1193 &clk_src_regs[0], false); 1194 pool->base.clock_sources[1] = 1195 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, 1196 &clk_src_regs[1], false); 1197 1198 pool->base.clk_src_count = 2; 1199 1200 /* TODO: find out if CZ support 3 PLLs */ 1201 } 1202 1203 if (pool->base.dp_clock_source == NULL) { 1204 dm_error("DC: failed to create dp clock source!\n"); 1205 BREAK_TO_DEBUGGER(); 1206 goto res_create_fail; 1207 } 1208 1209 for (i = 0; i < pool->base.clk_src_count; i++) { 1210 if (pool->base.clock_sources[i] == NULL) { 1211 dm_error("DC: failed to create clock sources!\n"); 1212 BREAK_TO_DEBUGGER(); 1213 goto res_create_fail; 1214 } 1215 } 1216 1217 pool->base.display_clock = dce110_disp_clk_create(ctx, 1218 &disp_clk_regs, 1219 &disp_clk_shift, 1220 &disp_clk_mask); 1221 if (pool->base.display_clock == NULL) { 1222 dm_error("DC: failed to create display clock!\n"); 1223 BREAK_TO_DEBUGGER(); 1224 goto res_create_fail; 1225 } 1226 1227 pool->base.dmcu = dce_dmcu_create(ctx, 1228 &dmcu_regs, 1229 &dmcu_shift, 1230 &dmcu_mask); 1231 if (pool->base.dmcu == NULL) { 1232 dm_error("DC: failed to create dmcu!\n"); 1233 BREAK_TO_DEBUGGER(); 1234 goto res_create_fail; 1235 } 1236 1237 pool->base.abm = dce_abm_create(ctx, 1238 &abm_regs, 1239 &abm_shift, 1240 &abm_mask); 1241 if (pool->base.abm == NULL) { 1242 dm_error("DC: failed to create abm!\n"); 1243 BREAK_TO_DEBUGGER(); 1244 goto res_create_fail; 1245 } 1246 1247 /* get static clock information for PPLIB or firmware, save 1248 * max_clock_state 1249 */ 1250 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 1251 pool->base.display_clock->max_clks_state = 1252 static_clk_info.max_clocks_state; 1253 1254 { 1255 struct irq_service_init_data init_data; 1256 init_data.ctx = dc->ctx; 1257 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 1258 if (!pool->base.irqs) 1259 goto res_create_fail; 1260 } 1261 1262 for (i = 0; i < pool->base.pipe_count; i++) { 1263 pool->base.timing_generators[i] = dce110_timing_generator_create( 1264 ctx, i, &dce110_tg_offsets[i]); 1265 if (pool->base.timing_generators[i] == NULL) { 1266 BREAK_TO_DEBUGGER(); 1267 dm_error("DC: failed to create tg!\n"); 1268 goto res_create_fail; 1269 } 1270 1271 pool->base.mis[i] = dce110_mem_input_create(ctx, i); 1272 if (pool->base.mis[i] == NULL) { 1273 BREAK_TO_DEBUGGER(); 1274 dm_error( 1275 "DC: failed to create memory input!\n"); 1276 goto res_create_fail; 1277 } 1278 1279 pool->base.ipps[i] = dce110_ipp_create(ctx, i); 1280 if (pool->base.ipps[i] == NULL) { 1281 BREAK_TO_DEBUGGER(); 1282 dm_error( 1283 "DC: failed to create input pixel processor!\n"); 1284 goto res_create_fail; 1285 } 1286 1287 pool->base.transforms[i] = dce110_transform_create(ctx, i); 1288 if (pool->base.transforms[i] == NULL) { 1289 BREAK_TO_DEBUGGER(); 1290 dm_error( 1291 "DC: failed to create transform!\n"); 1292 goto res_create_fail; 1293 } 1294 1295 pool->base.opps[i] = dce110_opp_create(ctx, i); 1296 if (pool->base.opps[i] == NULL) { 1297 BREAK_TO_DEBUGGER(); 1298 dm_error( 1299 "DC: failed to create output pixel processor!\n"); 1300 goto res_create_fail; 1301 } 1302 } 1303 1304 #ifdef ENABLE_FBC 1305 dc->fbc_compressor = dce110_compressor_create(ctx); 1306 1307 1308 1309 #endif 1310 if (!underlay_create(ctx, &pool->base)) 1311 goto res_create_fail; 1312 1313 if (!resource_construct(num_virtual_links, dc, &pool->base, 1314 &res_create_funcs)) 1315 goto res_create_fail; 1316 1317 /* Create hardware sequencer */ 1318 if (!dce110_hw_sequencer_construct(dc)) 1319 goto res_create_fail; 1320 1321 dc->caps.max_planes = pool->base.pipe_count; 1322 1323 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1324 1325 bw_calcs_data_update_from_pplib(dc); 1326 1327 return true; 1328 1329 res_create_fail: 1330 destruct(pool); 1331 return false; 1332 } 1333 1334 struct resource_pool *dce110_create_resource_pool( 1335 uint8_t num_virtual_links, 1336 struct dc *dc, 1337 struct hw_asic_id asic_id) 1338 { 1339 struct dce110_resource_pool *pool = 1340 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1341 1342 if (!pool) 1343 return NULL; 1344 1345 if (construct(num_virtual_links, dc, pool, asic_id)) 1346 return &pool->base; 1347 1348 BREAK_TO_DEBUGGER(); 1349 return NULL; 1350 } 1351