1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "link_encoder.h" 29 #include "stream_encoder.h" 30 31 #include "resource.h" 32 #include "dce110/dce110_resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dce/dce_audio.h" 35 #include "dce110/dce110_timing_generator.h" 36 #include "irq/dce110/irq_service_dce110.h" 37 #include "dce110/dce110_timing_generator_v.h" 38 #include "dce/dce_link_encoder.h" 39 #include "dce/dce_stream_encoder.h" 40 #include "dce/dce_mem_input.h" 41 #include "dce110/dce110_mem_input_v.h" 42 #include "dce/dce_ipp.h" 43 #include "dce/dce_transform.h" 44 #include "dce110/dce110_transform_v.h" 45 #include "dce/dce_opp.h" 46 #include "dce110/dce110_opp_v.h" 47 #include "dce/dce_clock_source.h" 48 #include "dce/dce_hwseq.h" 49 #include "dce110/dce110_hw_sequencer.h" 50 #include "dce/dce_aux.h" 51 #include "dce/dce_abm.h" 52 #include "dce/dce_dmcu.h" 53 #include "dce/dce_i2c.h" 54 #include "dce/dce_panel_cntl.h" 55 56 #define DC_LOGGER \ 57 dc->ctx->logger 58 59 #include "dce110/dce110_compressor.h" 60 61 #include "reg_helper.h" 62 63 #include "dce/dce_11_0_d.h" 64 #include "dce/dce_11_0_sh_mask.h" 65 66 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 67 #include "gmc/gmc_8_2_d.h" 68 #include "gmc/gmc_8_2_sh_mask.h" 69 #endif 70 71 #ifndef mmDP_DPHY_INTERNAL_CTRL 72 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 73 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 74 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 75 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 76 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 77 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 78 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 79 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 80 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 81 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 82 #endif 83 84 #ifndef mmBIOS_SCRATCH_2 85 #define mmBIOS_SCRATCH_2 0x05CB 86 #define mmBIOS_SCRATCH_3 0x05CC 87 #define mmBIOS_SCRATCH_6 0x05CF 88 #endif 89 90 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 91 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 92 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 93 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 94 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 95 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 96 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 97 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 98 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 99 #endif 100 101 #ifndef mmDP_DPHY_FAST_TRAINING 102 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 103 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 104 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 105 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 106 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 107 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 108 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 109 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 110 #endif 111 112 #ifndef DPHY_RX_FAST_TRAINING_CAPABLE 113 #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1 114 #endif 115 116 static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = { 117 { 118 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 119 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 120 }, 121 { 122 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 123 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 124 }, 125 { 126 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 127 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 128 }, 129 { 130 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 131 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 132 }, 133 { 134 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 135 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 136 }, 137 { 138 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 139 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 140 } 141 }; 142 143 /* set register offset */ 144 #define SR(reg_name)\ 145 .reg_name = mm ## reg_name 146 147 /* set register offset with instance */ 148 #define SRI(reg_name, block, id)\ 149 .reg_name = mm ## block ## id ## _ ## reg_name 150 151 static const struct dce_dmcu_registers dmcu_regs = { 152 DMCU_DCE110_COMMON_REG_LIST() 153 }; 154 155 static const struct dce_dmcu_shift dmcu_shift = { 156 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 157 }; 158 159 static const struct dce_dmcu_mask dmcu_mask = { 160 DMCU_MASK_SH_LIST_DCE110(_MASK) 161 }; 162 163 static const struct dce_abm_registers abm_regs = { 164 ABM_DCE110_COMMON_REG_LIST() 165 }; 166 167 static const struct dce_abm_shift abm_shift = { 168 ABM_MASK_SH_LIST_DCE110(__SHIFT) 169 }; 170 171 static const struct dce_abm_mask abm_mask = { 172 ABM_MASK_SH_LIST_DCE110(_MASK) 173 }; 174 175 #define ipp_regs(id)\ 176 [id] = {\ 177 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 178 } 179 180 static const struct dce_ipp_registers ipp_regs[] = { 181 ipp_regs(0), 182 ipp_regs(1), 183 ipp_regs(2) 184 }; 185 186 static const struct dce_ipp_shift ipp_shift = { 187 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 188 }; 189 190 static const struct dce_ipp_mask ipp_mask = { 191 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 192 }; 193 194 #define transform_regs(id)\ 195 [id] = {\ 196 XFM_COMMON_REG_LIST_DCE110(id)\ 197 } 198 199 static const struct dce_transform_registers xfm_regs[] = { 200 transform_regs(0), 201 transform_regs(1), 202 transform_regs(2) 203 }; 204 205 static const struct dce_transform_shift xfm_shift = { 206 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 207 }; 208 209 static const struct dce_transform_mask xfm_mask = { 210 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 211 }; 212 213 #define aux_regs(id)\ 214 [id] = {\ 215 AUX_REG_LIST(id)\ 216 } 217 218 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 219 aux_regs(0), 220 aux_regs(1), 221 aux_regs(2), 222 aux_regs(3), 223 aux_regs(4), 224 aux_regs(5) 225 }; 226 227 #define hpd_regs(id)\ 228 [id] = {\ 229 HPD_REG_LIST(id)\ 230 } 231 232 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 233 hpd_regs(0), 234 hpd_regs(1), 235 hpd_regs(2), 236 hpd_regs(3), 237 hpd_regs(4), 238 hpd_regs(5) 239 }; 240 241 242 #define link_regs(id)\ 243 [id] = {\ 244 LE_DCE110_REG_LIST(id)\ 245 } 246 247 static const struct dce110_link_enc_registers link_enc_regs[] = { 248 link_regs(0), 249 link_regs(1), 250 link_regs(2), 251 link_regs(3), 252 link_regs(4), 253 link_regs(5), 254 link_regs(6), 255 }; 256 257 #define stream_enc_regs(id)\ 258 [id] = {\ 259 SE_COMMON_REG_LIST(id),\ 260 .TMDS_CNTL = 0,\ 261 } 262 263 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 264 stream_enc_regs(0), 265 stream_enc_regs(1), 266 stream_enc_regs(2) 267 }; 268 269 static const struct dce_stream_encoder_shift se_shift = { 270 SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 271 }; 272 273 static const struct dce_stream_encoder_mask se_mask = { 274 SE_COMMON_MASK_SH_LIST_DCE110(_MASK) 275 }; 276 277 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 278 { DCE_PANEL_CNTL_REG_LIST() } 279 }; 280 281 static const struct dce_panel_cntl_shift panel_cntl_shift = { 282 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 283 }; 284 285 static const struct dce_panel_cntl_mask panel_cntl_mask = { 286 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 287 }; 288 289 static const struct dce110_aux_registers_shift aux_shift = { 290 DCE_AUX_MASK_SH_LIST(__SHIFT) 291 }; 292 293 static const struct dce110_aux_registers_mask aux_mask = { 294 DCE_AUX_MASK_SH_LIST(_MASK) 295 }; 296 297 #define opp_regs(id)\ 298 [id] = {\ 299 OPP_DCE_110_REG_LIST(id),\ 300 } 301 302 static const struct dce_opp_registers opp_regs[] = { 303 opp_regs(0), 304 opp_regs(1), 305 opp_regs(2), 306 opp_regs(3), 307 opp_regs(4), 308 opp_regs(5) 309 }; 310 311 static const struct dce_opp_shift opp_shift = { 312 OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT) 313 }; 314 315 static const struct dce_opp_mask opp_mask = { 316 OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK) 317 }; 318 319 #define aux_engine_regs(id)\ 320 [id] = {\ 321 AUX_COMMON_REG_LIST(id), \ 322 .AUX_RESET_MASK = 0 \ 323 } 324 325 static const struct dce110_aux_registers aux_engine_regs[] = { 326 aux_engine_regs(0), 327 aux_engine_regs(1), 328 aux_engine_regs(2), 329 aux_engine_regs(3), 330 aux_engine_regs(4), 331 aux_engine_regs(5) 332 }; 333 334 #define audio_regs(id)\ 335 [id] = {\ 336 AUD_COMMON_REG_LIST(id)\ 337 } 338 339 static const struct dce_audio_registers audio_regs[] = { 340 audio_regs(0), 341 audio_regs(1), 342 audio_regs(2), 343 audio_regs(3), 344 audio_regs(4), 345 audio_regs(5), 346 audio_regs(6), 347 }; 348 349 static const struct dce_audio_shift audio_shift = { 350 AUD_COMMON_MASK_SH_LIST(__SHIFT) 351 }; 352 353 static const struct dce_audio_mask audio_mask = { 354 AUD_COMMON_MASK_SH_LIST(_MASK) 355 }; 356 357 /* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */ 358 359 360 #define clk_src_regs(id)\ 361 [id] = {\ 362 CS_COMMON_REG_LIST_DCE_100_110(id),\ 363 } 364 365 static const struct dce110_clk_src_regs clk_src_regs[] = { 366 clk_src_regs(0), 367 clk_src_regs(1), 368 clk_src_regs(2) 369 }; 370 371 static const struct dce110_clk_src_shift cs_shift = { 372 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 373 }; 374 375 static const struct dce110_clk_src_mask cs_mask = { 376 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 377 }; 378 379 static const struct bios_registers bios_regs = { 380 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 381 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 382 }; 383 384 static const struct resource_caps carrizo_resource_cap = { 385 .num_timing_generator = 3, 386 .num_video_plane = 1, 387 .num_audio = 3, 388 .num_stream_encoder = 3, 389 .num_pll = 2, 390 .num_ddc = 3, 391 }; 392 393 static const struct resource_caps stoney_resource_cap = { 394 .num_timing_generator = 2, 395 .num_video_plane = 1, 396 .num_audio = 3, 397 .num_stream_encoder = 3, 398 .num_pll = 2, 399 .num_ddc = 3, 400 }; 401 402 static const struct dc_plane_cap plane_cap = { 403 .type = DC_PLANE_TYPE_DCE_RGB, 404 .per_pixel_alpha = 1, 405 406 .pixel_format_support = { 407 .argb8888 = true, 408 .nv12 = false, 409 .fp16 = true 410 }, 411 412 .max_upscale_factor = { 413 .argb8888 = 16000, 414 .nv12 = 1, 415 .fp16 = 1 416 }, 417 418 .max_downscale_factor = { 419 .argb8888 = 250, 420 .nv12 = 1, 421 .fp16 = 1 422 }, 423 64, 424 64 425 }; 426 427 static const struct dc_plane_cap underlay_plane_cap = { 428 .type = DC_PLANE_TYPE_DCE_UNDERLAY, 429 .per_pixel_alpha = 1, 430 431 .pixel_format_support = { 432 .argb8888 = false, 433 .nv12 = true, 434 .fp16 = false 435 }, 436 437 .max_upscale_factor = { 438 .argb8888 = 1, 439 .nv12 = 16000, 440 .fp16 = 1 441 }, 442 443 .max_downscale_factor = { 444 .argb8888 = 1, 445 .nv12 = 250, 446 .fp16 = 1 447 }, 448 64, 449 64 450 }; 451 452 #define CTX ctx 453 #define REG(reg) mm ## reg 454 455 #ifndef mmCC_DC_HDMI_STRAPS 456 #define mmCC_DC_HDMI_STRAPS 0x4819 457 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 458 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 459 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 460 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 461 #endif 462 463 static int map_transmitter_id_to_phy_instance( 464 enum transmitter transmitter) 465 { 466 switch (transmitter) { 467 case TRANSMITTER_UNIPHY_A: 468 return 0; 469 case TRANSMITTER_UNIPHY_B: 470 return 1; 471 case TRANSMITTER_UNIPHY_C: 472 return 2; 473 case TRANSMITTER_UNIPHY_D: 474 return 3; 475 case TRANSMITTER_UNIPHY_E: 476 return 4; 477 case TRANSMITTER_UNIPHY_F: 478 return 5; 479 case TRANSMITTER_UNIPHY_G: 480 return 6; 481 default: 482 ASSERT(0); 483 return 0; 484 } 485 } 486 487 static void read_dce_straps( 488 struct dc_context *ctx, 489 struct resource_straps *straps) 490 { 491 REG_GET_2(CC_DC_HDMI_STRAPS, 492 HDMI_DISABLE, &straps->hdmi_disable, 493 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 494 495 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 496 } 497 498 static struct audio *create_audio( 499 struct dc_context *ctx, unsigned int inst) 500 { 501 return dce_audio_create(ctx, inst, 502 &audio_regs[inst], &audio_shift, &audio_mask); 503 } 504 505 static struct timing_generator *dce110_timing_generator_create( 506 struct dc_context *ctx, 507 uint32_t instance, 508 const struct dce110_timing_generator_offsets *offsets) 509 { 510 struct dce110_timing_generator *tg110 = 511 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 512 513 if (!tg110) 514 return NULL; 515 516 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 517 return &tg110->base; 518 } 519 520 static struct stream_encoder *dce110_stream_encoder_create( 521 enum engine_id eng_id, 522 struct dc_context *ctx) 523 { 524 struct dce110_stream_encoder *enc110 = 525 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 526 527 if (!enc110) 528 return NULL; 529 530 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 531 &stream_enc_regs[eng_id], 532 &se_shift, &se_mask); 533 return &enc110->base; 534 } 535 536 #define SRII(reg_name, block, id)\ 537 .reg_name[id] = mm ## block ## id ## _ ## reg_name 538 539 static const struct dce_hwseq_registers hwseq_stoney_reg = { 540 HWSEQ_ST_REG_LIST() 541 }; 542 543 static const struct dce_hwseq_registers hwseq_cz_reg = { 544 HWSEQ_CZ_REG_LIST() 545 }; 546 547 static const struct dce_hwseq_shift hwseq_shift = { 548 HWSEQ_DCE11_MASK_SH_LIST(__SHIFT), 549 }; 550 551 static const struct dce_hwseq_mask hwseq_mask = { 552 HWSEQ_DCE11_MASK_SH_LIST(_MASK), 553 }; 554 555 static struct dce_hwseq *dce110_hwseq_create( 556 struct dc_context *ctx) 557 { 558 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 559 560 if (hws) { 561 hws->ctx = ctx; 562 hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ? 563 &hwseq_stoney_reg : &hwseq_cz_reg; 564 hws->shifts = &hwseq_shift; 565 hws->masks = &hwseq_mask; 566 hws->wa.blnd_crtc_trigger = true; 567 } 568 return hws; 569 } 570 571 static const struct resource_create_funcs res_create_funcs = { 572 .read_dce_straps = read_dce_straps, 573 .create_audio = create_audio, 574 .create_stream_encoder = dce110_stream_encoder_create, 575 .create_hwseq = dce110_hwseq_create, 576 }; 577 578 #define mi_inst_regs(id) { \ 579 MI_DCE11_REG_LIST(id), \ 580 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 581 } 582 static const struct dce_mem_input_registers mi_regs[] = { 583 mi_inst_regs(0), 584 mi_inst_regs(1), 585 mi_inst_regs(2), 586 }; 587 588 static const struct dce_mem_input_shift mi_shifts = { 589 MI_DCE11_MASK_SH_LIST(__SHIFT), 590 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 591 }; 592 593 static const struct dce_mem_input_mask mi_masks = { 594 MI_DCE11_MASK_SH_LIST(_MASK), 595 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 596 }; 597 598 599 static struct mem_input *dce110_mem_input_create( 600 struct dc_context *ctx, 601 uint32_t inst) 602 { 603 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 604 GFP_KERNEL); 605 606 if (!dce_mi) { 607 BREAK_TO_DEBUGGER(); 608 return NULL; 609 } 610 611 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 612 dce_mi->wa.single_head_rdreq_dmif_limit = 3; 613 return &dce_mi->base; 614 } 615 616 static void dce110_transform_destroy(struct transform **xfm) 617 { 618 kfree(TO_DCE_TRANSFORM(*xfm)); 619 *xfm = NULL; 620 } 621 622 static struct transform *dce110_transform_create( 623 struct dc_context *ctx, 624 uint32_t inst) 625 { 626 struct dce_transform *transform = 627 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 628 629 if (!transform) 630 return NULL; 631 632 dce_transform_construct(transform, ctx, inst, 633 &xfm_regs[inst], &xfm_shift, &xfm_mask); 634 return &transform->base; 635 } 636 637 static struct input_pixel_processor *dce110_ipp_create( 638 struct dc_context *ctx, uint32_t inst) 639 { 640 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 641 642 if (!ipp) { 643 BREAK_TO_DEBUGGER(); 644 return NULL; 645 } 646 647 dce_ipp_construct(ipp, ctx, inst, 648 &ipp_regs[inst], &ipp_shift, &ipp_mask); 649 return &ipp->base; 650 } 651 652 static const struct encoder_feature_support link_enc_feature = { 653 .max_hdmi_deep_color = COLOR_DEPTH_121212, 654 .max_hdmi_pixel_clock = 300000, 655 .flags.bits.IS_HBR2_CAPABLE = true, 656 .flags.bits.IS_TPS3_CAPABLE = true 657 }; 658 659 static struct link_encoder *dce110_link_encoder_create( 660 struct dc_context *ctx, 661 const struct encoder_init_data *enc_init_data) 662 { 663 struct dce110_link_encoder *enc110 = 664 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 665 int link_regs_id; 666 667 if (!enc110) 668 return NULL; 669 670 link_regs_id = 671 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 672 673 dce110_link_encoder_construct(enc110, 674 enc_init_data, 675 &link_enc_feature, 676 &link_enc_regs[link_regs_id], 677 &link_enc_aux_regs[enc_init_data->channel - 1], 678 &link_enc_hpd_regs[enc_init_data->hpd_source]); 679 return &enc110->base; 680 } 681 682 static struct panel_cntl *dce110_panel_cntl_create(const struct panel_cntl_init_data *init_data) 683 { 684 struct dce_panel_cntl *panel_cntl = 685 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 686 687 if (!panel_cntl) 688 return NULL; 689 690 dce_panel_cntl_construct(panel_cntl, 691 init_data, 692 &panel_cntl_regs[init_data->inst], 693 &panel_cntl_shift, 694 &panel_cntl_mask); 695 696 return &panel_cntl->base; 697 } 698 699 static struct output_pixel_processor *dce110_opp_create( 700 struct dc_context *ctx, 701 uint32_t inst) 702 { 703 struct dce110_opp *opp = 704 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 705 706 if (!opp) 707 return NULL; 708 709 dce110_opp_construct(opp, 710 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 711 return &opp->base; 712 } 713 714 static struct dce_aux *dce110_aux_engine_create( 715 struct dc_context *ctx, 716 uint32_t inst) 717 { 718 struct aux_engine_dce110 *aux_engine = 719 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 720 721 if (!aux_engine) 722 return NULL; 723 724 dce110_aux_engine_construct(aux_engine, ctx, inst, 725 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 726 &aux_engine_regs[inst], 727 &aux_mask, 728 &aux_shift, 729 ctx->dc->caps.extended_aux_timeout_support); 730 731 return &aux_engine->base; 732 } 733 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 734 735 static const struct dce_i2c_registers i2c_hw_regs[] = { 736 i2c_inst_regs(1), 737 i2c_inst_regs(2), 738 i2c_inst_regs(3), 739 i2c_inst_regs(4), 740 i2c_inst_regs(5), 741 i2c_inst_regs(6), 742 }; 743 744 static const struct dce_i2c_shift i2c_shifts = { 745 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 746 }; 747 748 static const struct dce_i2c_mask i2c_masks = { 749 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 750 }; 751 752 static struct dce_i2c_hw *dce110_i2c_hw_create( 753 struct dc_context *ctx, 754 uint32_t inst) 755 { 756 struct dce_i2c_hw *dce_i2c_hw = 757 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 758 759 if (!dce_i2c_hw) 760 return NULL; 761 762 dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst, 763 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 764 765 return dce_i2c_hw; 766 } 767 static struct clock_source *dce110_clock_source_create( 768 struct dc_context *ctx, 769 struct dc_bios *bios, 770 enum clock_source_id id, 771 const struct dce110_clk_src_regs *regs, 772 bool dp_clk_src) 773 { 774 struct dce110_clk_src *clk_src = 775 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 776 777 if (!clk_src) 778 return NULL; 779 780 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 781 regs, &cs_shift, &cs_mask)) { 782 clk_src->base.dp_clk_src = dp_clk_src; 783 return &clk_src->base; 784 } 785 786 kfree(clk_src); 787 BREAK_TO_DEBUGGER(); 788 return NULL; 789 } 790 791 static void dce110_clock_source_destroy(struct clock_source **clk_src) 792 { 793 struct dce110_clk_src *dce110_clk_src; 794 795 if (!clk_src) 796 return; 797 798 dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src); 799 800 kfree(dce110_clk_src->dp_ss_params); 801 kfree(dce110_clk_src->hdmi_ss_params); 802 kfree(dce110_clk_src->dvi_ss_params); 803 804 kfree(dce110_clk_src); 805 *clk_src = NULL; 806 } 807 808 static void dce110_resource_destruct(struct dce110_resource_pool *pool) 809 { 810 unsigned int i; 811 812 for (i = 0; i < pool->base.pipe_count; i++) { 813 if (pool->base.opps[i] != NULL) 814 dce110_opp_destroy(&pool->base.opps[i]); 815 816 if (pool->base.transforms[i] != NULL) 817 dce110_transform_destroy(&pool->base.transforms[i]); 818 819 if (pool->base.ipps[i] != NULL) 820 dce_ipp_destroy(&pool->base.ipps[i]); 821 822 if (pool->base.mis[i] != NULL) { 823 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 824 pool->base.mis[i] = NULL; 825 } 826 827 if (pool->base.timing_generators[i] != NULL) { 828 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 829 pool->base.timing_generators[i] = NULL; 830 } 831 } 832 833 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 834 if (pool->base.engines[i] != NULL) 835 dce110_engine_destroy(&pool->base.engines[i]); 836 if (pool->base.hw_i2cs[i] != NULL) { 837 kfree(pool->base.hw_i2cs[i]); 838 pool->base.hw_i2cs[i] = NULL; 839 } 840 if (pool->base.sw_i2cs[i] != NULL) { 841 kfree(pool->base.sw_i2cs[i]); 842 pool->base.sw_i2cs[i] = NULL; 843 } 844 } 845 846 for (i = 0; i < pool->base.stream_enc_count; i++) { 847 if (pool->base.stream_enc[i] != NULL) 848 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 849 } 850 851 for (i = 0; i < pool->base.clk_src_count; i++) { 852 if (pool->base.clock_sources[i] != NULL) { 853 dce110_clock_source_destroy(&pool->base.clock_sources[i]); 854 } 855 } 856 857 if (pool->base.dp_clock_source != NULL) 858 dce110_clock_source_destroy(&pool->base.dp_clock_source); 859 860 for (i = 0; i < pool->base.audio_count; i++) { 861 if (pool->base.audios[i] != NULL) { 862 dce_aud_destroy(&pool->base.audios[i]); 863 } 864 } 865 866 if (pool->base.abm != NULL) 867 dce_abm_destroy(&pool->base.abm); 868 869 if (pool->base.dmcu != NULL) 870 dce_dmcu_destroy(&pool->base.dmcu); 871 872 if (pool->base.irqs != NULL) { 873 dal_irq_service_destroy(&pool->base.irqs); 874 } 875 } 876 877 878 static void get_pixel_clock_parameters( 879 const struct pipe_ctx *pipe_ctx, 880 struct pixel_clk_params *pixel_clk_params) 881 { 882 const struct dc_stream_state *stream = pipe_ctx->stream; 883 884 /*TODO: is this halved for YCbCr 420? in that case we might want to move 885 * the pixel clock normalization for hdmi up to here instead of doing it 886 * in pll_adjust_pix_clk 887 */ 888 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 889 pixel_clk_params->encoder_object_id = stream->link->link_enc->id; 890 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 891 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 892 /* TODO: un-hardcode*/ 893 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 894 LINK_RATE_REF_FREQ_IN_KHZ; 895 pixel_clk_params->flags.ENABLE_SS = 0; 896 pixel_clk_params->color_depth = 897 stream->timing.display_color_depth; 898 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 899 pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding == 900 PIXEL_ENCODING_YCBCR420); 901 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 902 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) { 903 pixel_clk_params->color_depth = COLOR_DEPTH_888; 904 } 905 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 906 pixel_clk_params->requested_pix_clk_100hz = pixel_clk_params->requested_pix_clk_100hz / 2; 907 } 908 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 909 pixel_clk_params->requested_pix_clk_100hz *= 2; 910 911 } 912 913 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 914 { 915 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 916 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 917 pipe_ctx->clock_source, 918 &pipe_ctx->stream_res.pix_clk_params, 919 &pipe_ctx->pll_settings); 920 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 921 &pipe_ctx->stream->bit_depth_params); 922 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 923 } 924 925 static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx) 926 { 927 if (pipe_ctx->pipe_idx != underlay_idx) 928 return true; 929 if (!pipe_ctx->plane_state) 930 return false; 931 if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 932 return false; 933 return true; 934 } 935 936 static enum dc_status build_mapped_resource( 937 const struct dc *dc, 938 struct dc_state *context, 939 struct dc_stream_state *stream) 940 { 941 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 942 943 if (!pipe_ctx) 944 return DC_ERROR_UNEXPECTED; 945 946 if (!is_surface_pixel_format_supported(pipe_ctx, 947 dc->res_pool->underlay_pipe_index)) 948 return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; 949 950 dce110_resource_build_pipe_hw_param(pipe_ctx); 951 952 /* TODO: validate audio ASIC caps, encoder */ 953 954 resource_build_info_frame(pipe_ctx); 955 956 return DC_OK; 957 } 958 959 static bool dce110_validate_bandwidth( 960 struct dc *dc, 961 struct dc_state *context, 962 bool fast_validate) 963 { 964 bool result = false; 965 966 DC_LOG_BANDWIDTH_CALCS( 967 "%s: start", 968 __func__); 969 970 if (bw_calcs( 971 dc->ctx, 972 dc->bw_dceip, 973 dc->bw_vbios, 974 context->res_ctx.pipe_ctx, 975 dc->res_pool->pipe_count, 976 &context->bw_ctx.bw.dce)) 977 result = true; 978 979 if (!result) 980 DC_LOG_BANDWIDTH_VALIDATION("%s: %dx%d@%d Bandwidth validation failed!\n", 981 __func__, 982 context->streams[0]->timing.h_addressable, 983 context->streams[0]->timing.v_addressable, 984 context->streams[0]->timing.pix_clk_100hz / 10); 985 986 if (memcmp(&dc->current_state->bw_ctx.bw.dce, 987 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { 988 989 DC_LOG_BANDWIDTH_CALCS( 990 "%s: finish,\n" 991 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 992 "stutMark_b: %d stutMark_a: %d\n" 993 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 994 "stutMark_b: %d stutMark_a: %d\n" 995 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 996 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n" 997 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" 998 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n" 999 , 1000 __func__, 1001 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark, 1002 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark, 1003 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, 1004 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, 1005 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark, 1006 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark, 1007 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark, 1008 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark, 1009 context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark, 1010 context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark, 1011 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark, 1012 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark, 1013 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark, 1014 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark, 1015 context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark, 1016 context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark, 1017 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark, 1018 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark, 1019 context->bw_ctx.bw.dce.stutter_mode_enable, 1020 context->bw_ctx.bw.dce.cpuc_state_change_enable, 1021 context->bw_ctx.bw.dce.cpup_state_change_enable, 1022 context->bw_ctx.bw.dce.nbp_state_change_enable, 1023 context->bw_ctx.bw.dce.all_displays_in_sync, 1024 context->bw_ctx.bw.dce.dispclk_khz, 1025 context->bw_ctx.bw.dce.sclk_khz, 1026 context->bw_ctx.bw.dce.sclk_deep_sleep_khz, 1027 context->bw_ctx.bw.dce.yclk_khz, 1028 context->bw_ctx.bw.dce.blackout_recovery_time_us); 1029 } 1030 return result; 1031 } 1032 1033 static enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state, 1034 struct dc_caps *caps) 1035 { 1036 if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) || 1037 ((plane_state->dst_rect.height * 2) < plane_state->src_rect.height)) 1038 return DC_FAIL_SURFACE_VALIDATE; 1039 1040 return DC_OK; 1041 } 1042 1043 static bool dce110_validate_surface_sets( 1044 struct dc_state *context) 1045 { 1046 int i, j; 1047 1048 for (i = 0; i < context->stream_count; i++) { 1049 if (context->stream_status[i].plane_count == 0) 1050 continue; 1051 1052 if (context->stream_status[i].plane_count > 2) 1053 return false; 1054 1055 for (j = 0; j < context->stream_status[i].plane_count; j++) { 1056 struct dc_plane_state *plane = 1057 context->stream_status[i].plane_states[j]; 1058 1059 /* underlay validation */ 1060 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 1061 1062 if ((plane->src_rect.width > 1920 || 1063 plane->src_rect.height > 1080)) 1064 return false; 1065 1066 /* we don't have the logic to support underlay 1067 * only yet so block the use case where we get 1068 * NV12 plane as top layer 1069 */ 1070 if (j == 0) 1071 return false; 1072 1073 /* irrespective of plane format, 1074 * stream should be RGB encoded 1075 */ 1076 if (context->streams[i]->timing.pixel_encoding 1077 != PIXEL_ENCODING_RGB) 1078 return false; 1079 1080 } 1081 1082 } 1083 } 1084 1085 return true; 1086 } 1087 1088 static enum dc_status dce110_validate_global( 1089 struct dc *dc, 1090 struct dc_state *context) 1091 { 1092 if (!dce110_validate_surface_sets(context)) 1093 return DC_FAIL_SURFACE_VALIDATE; 1094 1095 return DC_OK; 1096 } 1097 1098 static enum dc_status dce110_add_stream_to_ctx( 1099 struct dc *dc, 1100 struct dc_state *new_ctx, 1101 struct dc_stream_state *dc_stream) 1102 { 1103 enum dc_status result = DC_ERROR_UNEXPECTED; 1104 1105 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1106 1107 if (result == DC_OK) 1108 result = resource_map_clock_resources(dc, new_ctx, dc_stream); 1109 1110 1111 if (result == DC_OK) 1112 result = build_mapped_resource(dc, new_ctx, dc_stream); 1113 1114 return result; 1115 } 1116 1117 static struct pipe_ctx *dce110_acquire_underlay( 1118 struct dc_state *context, 1119 const struct resource_pool *pool, 1120 struct dc_stream_state *stream) 1121 { 1122 struct dc *dc = stream->ctx->dc; 1123 struct dce_hwseq *hws = dc->hwseq; 1124 struct resource_context *res_ctx = &context->res_ctx; 1125 unsigned int underlay_idx = pool->underlay_pipe_index; 1126 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; 1127 1128 if (res_ctx->pipe_ctx[underlay_idx].stream) 1129 return NULL; 1130 1131 pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx]; 1132 pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; 1133 /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/ 1134 pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; 1135 pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; 1136 pipe_ctx->pipe_idx = underlay_idx; 1137 1138 pipe_ctx->stream = stream; 1139 1140 if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) { 1141 struct tg_color black_color = {0}; 1142 struct dc_bios *dcb = dc->ctx->dc_bios; 1143 1144 hws->funcs.enable_display_power_gating( 1145 dc, 1146 pipe_ctx->stream_res.tg->inst, 1147 dcb, PIPE_GATING_CONTROL_DISABLE); 1148 1149 /* 1150 * This is for powering on underlay, so crtc does not 1151 * need to be enabled 1152 */ 1153 1154 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg, 1155 &stream->timing, 1156 0, 1157 0, 1158 0, 1159 0, 1160 pipe_ctx->stream->signal, 1161 false); 1162 1163 pipe_ctx->stream_res.tg->funcs->enable_advanced_request( 1164 pipe_ctx->stream_res.tg, 1165 true, 1166 &stream->timing); 1167 1168 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi, 1169 stream->timing.h_total, 1170 stream->timing.v_total, 1171 stream->timing.pix_clk_100hz / 10, 1172 context->stream_count); 1173 1174 color_space_to_black_color(dc, 1175 COLOR_SPACE_YCBCR601, &black_color); 1176 pipe_ctx->stream_res.tg->funcs->set_blank_color( 1177 pipe_ctx->stream_res.tg, 1178 &black_color); 1179 } 1180 1181 return pipe_ctx; 1182 } 1183 1184 static void dce110_destroy_resource_pool(struct resource_pool **pool) 1185 { 1186 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 1187 1188 dce110_resource_destruct(dce110_pool); 1189 kfree(dce110_pool); 1190 *pool = NULL; 1191 } 1192 1193 struct stream_encoder *dce110_find_first_free_match_stream_enc_for_link( 1194 struct resource_context *res_ctx, 1195 const struct resource_pool *pool, 1196 struct dc_stream_state *stream) 1197 { 1198 int i; 1199 int j = -1; 1200 struct dc_link *link = stream->link; 1201 1202 for (i = 0; i < pool->stream_enc_count; i++) { 1203 if (!res_ctx->is_stream_enc_acquired[i] && 1204 pool->stream_enc[i]) { 1205 /* Store first available for MST second display 1206 * in daisy chain use case 1207 */ 1208 j = i; 1209 if (pool->stream_enc[i]->id == 1210 link->link_enc->preferred_engine) 1211 return pool->stream_enc[i]; 1212 } 1213 } 1214 1215 /* 1216 * For CZ and later, we can allow DIG FE and BE to differ for all display types 1217 */ 1218 1219 if (j >= 0) 1220 return pool->stream_enc[j]; 1221 1222 return NULL; 1223 } 1224 1225 1226 static const struct resource_funcs dce110_res_pool_funcs = { 1227 .destroy = dce110_destroy_resource_pool, 1228 .link_enc_create = dce110_link_encoder_create, 1229 .panel_cntl_create = dce110_panel_cntl_create, 1230 .validate_bandwidth = dce110_validate_bandwidth, 1231 .validate_plane = dce110_validate_plane, 1232 .acquire_idle_pipe_for_layer = dce110_acquire_underlay, 1233 .add_stream_to_ctx = dce110_add_stream_to_ctx, 1234 .validate_global = dce110_validate_global, 1235 .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link 1236 }; 1237 1238 static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) 1239 { 1240 struct dce110_timing_generator *dce110_tgv = kzalloc(sizeof(*dce110_tgv), 1241 GFP_KERNEL); 1242 struct dce_transform *dce110_xfmv = kzalloc(sizeof(*dce110_xfmv), 1243 GFP_KERNEL); 1244 struct dce_mem_input *dce110_miv = kzalloc(sizeof(*dce110_miv), 1245 GFP_KERNEL); 1246 struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv), 1247 GFP_KERNEL); 1248 1249 if (!dce110_tgv || !dce110_xfmv || !dce110_miv || !dce110_oppv) { 1250 kfree(dce110_tgv); 1251 kfree(dce110_xfmv); 1252 kfree(dce110_miv); 1253 kfree(dce110_oppv); 1254 return false; 1255 } 1256 1257 dce110_opp_v_construct(dce110_oppv, ctx); 1258 1259 dce110_timing_generator_v_construct(dce110_tgv, ctx); 1260 dce110_mem_input_v_construct(dce110_miv, ctx); 1261 dce110_transform_v_construct(dce110_xfmv, ctx); 1262 1263 pool->opps[pool->pipe_count] = &dce110_oppv->base; 1264 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; 1265 pool->mis[pool->pipe_count] = &dce110_miv->base; 1266 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; 1267 pool->pipe_count++; 1268 1269 /* update the public caps to indicate an underlay is available */ 1270 ctx->dc->caps.max_slave_planes = 1; 1271 ctx->dc->caps.max_slave_yuv_planes = 1; 1272 ctx->dc->caps.max_slave_rgb_planes = 0; 1273 1274 return true; 1275 } 1276 1277 static void bw_calcs_data_update_from_pplib(struct dc *dc) 1278 { 1279 struct dm_pp_clock_levels clks = {0}; 1280 1281 /*do system clock*/ 1282 dm_pp_get_clock_levels_by_type( 1283 dc->ctx, 1284 DM_PP_CLOCK_TYPE_ENGINE_CLK, 1285 &clks); 1286 /* convert all the clock fro kHz to fix point mHz */ 1287 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 1288 clks.clocks_in_khz[clks.num_levels-1], 1000); 1289 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 1290 clks.clocks_in_khz[clks.num_levels/8], 1000); 1291 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 1292 clks.clocks_in_khz[clks.num_levels*2/8], 1000); 1293 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 1294 clks.clocks_in_khz[clks.num_levels*3/8], 1000); 1295 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 1296 clks.clocks_in_khz[clks.num_levels*4/8], 1000); 1297 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 1298 clks.clocks_in_khz[clks.num_levels*5/8], 1000); 1299 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1300 clks.clocks_in_khz[clks.num_levels*6/8], 1000); 1301 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1302 clks.clocks_in_khz[0], 1000); 1303 dc->sclk_lvls = clks; 1304 1305 /*do display clock*/ 1306 dm_pp_get_clock_levels_by_type( 1307 dc->ctx, 1308 DM_PP_CLOCK_TYPE_DISPLAY_CLK, 1309 &clks); 1310 dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed( 1311 clks.clocks_in_khz[clks.num_levels-1], 1000); 1312 dc->bw_vbios->mid_voltage_max_dispclk = bw_frc_to_fixed( 1313 clks.clocks_in_khz[clks.num_levels>>1], 1000); 1314 dc->bw_vbios->low_voltage_max_dispclk = bw_frc_to_fixed( 1315 clks.clocks_in_khz[0], 1000); 1316 1317 /*do memory clock*/ 1318 dm_pp_get_clock_levels_by_type( 1319 dc->ctx, 1320 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1321 &clks); 1322 1323 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1324 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER_CZ, 1000); 1325 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1326 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ, 1327 1000); 1328 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1329 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER_CZ, 1330 1000); 1331 } 1332 1333 static const struct resource_caps *dce110_resource_cap( 1334 struct hw_asic_id *asic_id) 1335 { 1336 if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev)) 1337 return &stoney_resource_cap; 1338 else 1339 return &carrizo_resource_cap; 1340 } 1341 1342 static bool dce110_resource_construct( 1343 uint8_t num_virtual_links, 1344 struct dc *dc, 1345 struct dce110_resource_pool *pool, 1346 struct hw_asic_id asic_id) 1347 { 1348 unsigned int i; 1349 struct dc_context *ctx = dc->ctx; 1350 struct dc_bios *bp; 1351 1352 ctx->dc_bios->regs = &bios_regs; 1353 1354 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); 1355 pool->base.funcs = &dce110_res_pool_funcs; 1356 1357 /************************************************* 1358 * Resource + asic cap harcoding * 1359 *************************************************/ 1360 1361 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1362 pool->base.underlay_pipe_index = pool->base.pipe_count; 1363 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1364 dc->caps.max_downscale_ratio = 150; 1365 dc->caps.i2c_speed_in_khz = 40; 1366 dc->caps.i2c_speed_in_khz_hdcp = 40; 1367 dc->caps.max_cursor_size = 128; 1368 dc->caps.min_horizontal_blanking_period = 80; 1369 dc->caps.is_apu = true; 1370 dc->caps.extended_aux_timeout_support = false; 1371 1372 /************************************************* 1373 * Create resources * 1374 *************************************************/ 1375 1376 bp = ctx->dc_bios; 1377 1378 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 1379 pool->base.dp_clock_source = 1380 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1381 1382 pool->base.clock_sources[0] = 1383 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, 1384 &clk_src_regs[0], false); 1385 pool->base.clock_sources[1] = 1386 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, 1387 &clk_src_regs[1], false); 1388 1389 pool->base.clk_src_count = 2; 1390 1391 /* TODO: find out if CZ support 3 PLLs */ 1392 } 1393 1394 if (pool->base.dp_clock_source == NULL) { 1395 dm_error("DC: failed to create dp clock source!\n"); 1396 BREAK_TO_DEBUGGER(); 1397 goto res_create_fail; 1398 } 1399 1400 for (i = 0; i < pool->base.clk_src_count; i++) { 1401 if (pool->base.clock_sources[i] == NULL) { 1402 dm_error("DC: failed to create clock sources!\n"); 1403 BREAK_TO_DEBUGGER(); 1404 goto res_create_fail; 1405 } 1406 } 1407 1408 pool->base.dmcu = dce_dmcu_create(ctx, 1409 &dmcu_regs, 1410 &dmcu_shift, 1411 &dmcu_mask); 1412 if (pool->base.dmcu == NULL) { 1413 dm_error("DC: failed to create dmcu!\n"); 1414 BREAK_TO_DEBUGGER(); 1415 goto res_create_fail; 1416 } 1417 1418 pool->base.abm = dce_abm_create(ctx, 1419 &abm_regs, 1420 &abm_shift, 1421 &abm_mask); 1422 if (pool->base.abm == NULL) { 1423 dm_error("DC: failed to create abm!\n"); 1424 BREAK_TO_DEBUGGER(); 1425 goto res_create_fail; 1426 } 1427 1428 { 1429 struct irq_service_init_data init_data; 1430 init_data.ctx = dc->ctx; 1431 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 1432 if (!pool->base.irqs) 1433 goto res_create_fail; 1434 } 1435 1436 for (i = 0; i < pool->base.pipe_count; i++) { 1437 pool->base.timing_generators[i] = dce110_timing_generator_create( 1438 ctx, i, &dce110_tg_offsets[i]); 1439 if (pool->base.timing_generators[i] == NULL) { 1440 BREAK_TO_DEBUGGER(); 1441 dm_error("DC: failed to create tg!\n"); 1442 goto res_create_fail; 1443 } 1444 1445 pool->base.mis[i] = dce110_mem_input_create(ctx, i); 1446 if (pool->base.mis[i] == NULL) { 1447 BREAK_TO_DEBUGGER(); 1448 dm_error( 1449 "DC: failed to create memory input!\n"); 1450 goto res_create_fail; 1451 } 1452 1453 pool->base.ipps[i] = dce110_ipp_create(ctx, i); 1454 if (pool->base.ipps[i] == NULL) { 1455 BREAK_TO_DEBUGGER(); 1456 dm_error( 1457 "DC: failed to create input pixel processor!\n"); 1458 goto res_create_fail; 1459 } 1460 1461 pool->base.transforms[i] = dce110_transform_create(ctx, i); 1462 if (pool->base.transforms[i] == NULL) { 1463 BREAK_TO_DEBUGGER(); 1464 dm_error( 1465 "DC: failed to create transform!\n"); 1466 goto res_create_fail; 1467 } 1468 1469 pool->base.opps[i] = dce110_opp_create(ctx, i); 1470 if (pool->base.opps[i] == NULL) { 1471 BREAK_TO_DEBUGGER(); 1472 dm_error( 1473 "DC: failed to create output pixel processor!\n"); 1474 goto res_create_fail; 1475 } 1476 } 1477 1478 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1479 pool->base.engines[i] = dce110_aux_engine_create(ctx, i); 1480 if (pool->base.engines[i] == NULL) { 1481 BREAK_TO_DEBUGGER(); 1482 dm_error( 1483 "DC:failed to create aux engine!!\n"); 1484 goto res_create_fail; 1485 } 1486 pool->base.hw_i2cs[i] = dce110_i2c_hw_create(ctx, i); 1487 if (pool->base.hw_i2cs[i] == NULL) { 1488 BREAK_TO_DEBUGGER(); 1489 dm_error( 1490 "DC:failed to create i2c engine!!\n"); 1491 goto res_create_fail; 1492 } 1493 pool->base.sw_i2cs[i] = NULL; 1494 } 1495 1496 if (dc->config.fbc_support) 1497 dc->fbc_compressor = dce110_compressor_create(ctx); 1498 1499 if (!underlay_create(ctx, &pool->base)) 1500 goto res_create_fail; 1501 1502 if (!resource_construct(num_virtual_links, dc, &pool->base, 1503 &res_create_funcs)) 1504 goto res_create_fail; 1505 1506 /* Create hardware sequencer */ 1507 dce110_hw_sequencer_construct(dc); 1508 1509 dc->caps.max_planes = pool->base.pipe_count; 1510 1511 for (i = 0; i < pool->base.underlay_pipe_index; ++i) 1512 dc->caps.planes[i] = plane_cap; 1513 1514 dc->caps.planes[pool->base.underlay_pipe_index] = underlay_plane_cap; 1515 1516 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1517 1518 bw_calcs_data_update_from_pplib(dc); 1519 1520 return true; 1521 1522 res_create_fail: 1523 dce110_resource_destruct(pool); 1524 return false; 1525 } 1526 1527 struct resource_pool *dce110_create_resource_pool( 1528 uint8_t num_virtual_links, 1529 struct dc *dc, 1530 struct hw_asic_id asic_id) 1531 { 1532 struct dce110_resource_pool *pool = 1533 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1534 1535 if (!pool) 1536 return NULL; 1537 1538 if (dce110_resource_construct(num_virtual_links, dc, pool, asic_id)) 1539 return &pool->base; 1540 1541 kfree(pool); 1542 BREAK_TO_DEBUGGER(); 1543 return NULL; 1544 } 1545