1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include "dm_services.h" 26 27 #include "link_encoder.h" 28 #include "stream_encoder.h" 29 30 #include "resource.h" 31 #include "include/irq_service_interface.h" 32 #include "../virtual/virtual_stream_encoder.h" 33 #include "dce110/dce110_resource.h" 34 #include "dce110/dce110_timing_generator.h" 35 #include "irq/dce110/irq_service_dce110.h" 36 #include "dce/dce_link_encoder.h" 37 #include "dce/dce_stream_encoder.h" 38 39 #include "dce/dce_mem_input.h" 40 #include "dce/dce_ipp.h" 41 #include "dce/dce_transform.h" 42 #include "dce/dce_opp.h" 43 #include "dce/dce_clocks.h" 44 #include "dce/dce_clock_source.h" 45 #include "dce/dce_audio.h" 46 #include "dce/dce_hwseq.h" 47 #include "dce100/dce100_hw_sequencer.h" 48 49 #include "reg_helper.h" 50 51 #include "dce/dce_10_0_d.h" 52 #include "dce/dce_10_0_sh_mask.h" 53 54 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 55 #include "gmc/gmc_8_2_d.h" 56 #include "gmc/gmc_8_2_sh_mask.h" 57 #endif 58 59 #ifndef mmDP_DPHY_INTERNAL_CTRL 60 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 61 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 62 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 63 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 64 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 65 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 66 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 67 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 68 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 69 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 70 #endif 71 72 #ifndef mmBIOS_SCRATCH_2 73 #define mmBIOS_SCRATCH_2 0x05CB 74 #define mmBIOS_SCRATCH_6 0x05CF 75 #endif 76 77 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 78 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 79 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 80 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 81 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 82 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 83 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 84 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 85 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 86 #endif 87 88 #ifndef mmDP_DPHY_FAST_TRAINING 89 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 90 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 91 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 92 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 93 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 94 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 95 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 96 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 97 #endif 98 99 static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = { 100 { 101 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 102 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 103 }, 104 { 105 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 106 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 107 }, 108 { 109 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 110 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 111 }, 112 { 113 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 114 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 115 }, 116 { 117 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 118 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 119 }, 120 { 121 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 122 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 123 } 124 }; 125 126 /* set register offset */ 127 #define SR(reg_name)\ 128 .reg_name = mm ## reg_name 129 130 /* set register offset with instance */ 131 #define SRI(reg_name, block, id)\ 132 .reg_name = mm ## block ## id ## _ ## reg_name 133 134 135 static const struct dce_disp_clk_registers disp_clk_regs = { 136 CLK_COMMON_REG_LIST_DCE_BASE() 137 }; 138 139 static const struct dce_disp_clk_shift disp_clk_shift = { 140 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 141 }; 142 143 static const struct dce_disp_clk_mask disp_clk_mask = { 144 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 145 }; 146 147 #define ipp_regs(id)\ 148 [id] = {\ 149 IPP_DCE100_REG_LIST_DCE_BASE(id)\ 150 } 151 152 static const struct dce_ipp_registers ipp_regs[] = { 153 ipp_regs(0), 154 ipp_regs(1), 155 ipp_regs(2), 156 ipp_regs(3), 157 ipp_regs(4), 158 ipp_regs(5) 159 }; 160 161 static const struct dce_ipp_shift ipp_shift = { 162 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 163 }; 164 165 static const struct dce_ipp_mask ipp_mask = { 166 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 167 }; 168 169 #define transform_regs(id)\ 170 [id] = {\ 171 XFM_COMMON_REG_LIST_DCE100(id)\ 172 } 173 174 static const struct dce_transform_registers xfm_regs[] = { 175 transform_regs(0), 176 transform_regs(1), 177 transform_regs(2), 178 transform_regs(3), 179 transform_regs(4), 180 transform_regs(5) 181 }; 182 183 static const struct dce_transform_shift xfm_shift = { 184 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 185 }; 186 187 static const struct dce_transform_mask xfm_mask = { 188 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 189 }; 190 191 #define aux_regs(id)\ 192 [id] = {\ 193 AUX_REG_LIST(id)\ 194 } 195 196 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 197 aux_regs(0), 198 aux_regs(1), 199 aux_regs(2), 200 aux_regs(3), 201 aux_regs(4), 202 aux_regs(5) 203 }; 204 205 #define hpd_regs(id)\ 206 [id] = {\ 207 HPD_REG_LIST(id)\ 208 } 209 210 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 211 hpd_regs(0), 212 hpd_regs(1), 213 hpd_regs(2), 214 hpd_regs(3), 215 hpd_regs(4), 216 hpd_regs(5) 217 }; 218 219 #define link_regs(id)\ 220 [id] = {\ 221 LE_DCE100_REG_LIST(id)\ 222 } 223 224 static const struct dce110_link_enc_registers link_enc_regs[] = { 225 link_regs(0), 226 link_regs(1), 227 link_regs(2), 228 link_regs(3), 229 link_regs(4), 230 link_regs(5), 231 link_regs(6), 232 }; 233 234 #define stream_enc_regs(id)\ 235 [id] = {\ 236 SE_COMMON_REG_LIST_DCE_BASE(id),\ 237 .AFMT_CNTL = 0,\ 238 } 239 240 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 241 stream_enc_regs(0), 242 stream_enc_regs(1), 243 stream_enc_regs(2), 244 stream_enc_regs(3), 245 stream_enc_regs(4), 246 stream_enc_regs(5), 247 stream_enc_regs(6) 248 }; 249 250 static const struct dce_stream_encoder_shift se_shift = { 251 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) 252 }; 253 254 static const struct dce_stream_encoder_mask se_mask = { 255 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) 256 }; 257 258 #define opp_regs(id)\ 259 [id] = {\ 260 OPP_DCE_100_REG_LIST(id),\ 261 } 262 263 static const struct dce_opp_registers opp_regs[] = { 264 opp_regs(0), 265 opp_regs(1), 266 opp_regs(2), 267 opp_regs(3), 268 opp_regs(4), 269 opp_regs(5) 270 }; 271 272 static const struct dce_opp_shift opp_shift = { 273 OPP_COMMON_MASK_SH_LIST_DCE_100(__SHIFT) 274 }; 275 276 static const struct dce_opp_mask opp_mask = { 277 OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK) 278 }; 279 280 281 #define audio_regs(id)\ 282 [id] = {\ 283 AUD_COMMON_REG_LIST(id)\ 284 } 285 286 static const struct dce_audio_registers audio_regs[] = { 287 audio_regs(0), 288 audio_regs(1), 289 audio_regs(2), 290 audio_regs(3), 291 audio_regs(4), 292 audio_regs(5), 293 audio_regs(6), 294 }; 295 296 static const struct dce_audio_shift audio_shift = { 297 AUD_COMMON_MASK_SH_LIST(__SHIFT) 298 }; 299 300 static const struct dce_aduio_mask audio_mask = { 301 AUD_COMMON_MASK_SH_LIST(_MASK) 302 }; 303 304 #define clk_src_regs(id)\ 305 [id] = {\ 306 CS_COMMON_REG_LIST_DCE_100_110(id),\ 307 } 308 309 static const struct dce110_clk_src_regs clk_src_regs[] = { 310 clk_src_regs(0), 311 clk_src_regs(1), 312 clk_src_regs(2) 313 }; 314 315 static const struct dce110_clk_src_shift cs_shift = { 316 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 317 }; 318 319 static const struct dce110_clk_src_mask cs_mask = { 320 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 321 }; 322 323 324 325 #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03 326 327 static const struct bios_registers bios_regs = { 328 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 329 }; 330 331 static const struct resource_caps res_cap = { 332 .num_timing_generator = 6, 333 .num_audio = 6, 334 .num_stream_encoder = 6, 335 .num_pll = 3 336 }; 337 338 #define CTX ctx 339 #define REG(reg) mm ## reg 340 341 #ifndef mmCC_DC_HDMI_STRAPS 342 #define mmCC_DC_HDMI_STRAPS 0x1918 343 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 344 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 345 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 346 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 347 #endif 348 349 static void read_dce_straps( 350 struct dc_context *ctx, 351 struct resource_straps *straps) 352 { 353 REG_GET_2(CC_DC_HDMI_STRAPS, 354 HDMI_DISABLE, &straps->hdmi_disable, 355 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 356 357 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 358 } 359 360 static struct audio *create_audio( 361 struct dc_context *ctx, unsigned int inst) 362 { 363 return dce_audio_create(ctx, inst, 364 &audio_regs[inst], &audio_shift, &audio_mask); 365 } 366 367 static struct timing_generator *dce100_timing_generator_create( 368 struct dc_context *ctx, 369 uint32_t instance, 370 const struct dce110_timing_generator_offsets *offsets) 371 { 372 struct dce110_timing_generator *tg110 = 373 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 374 375 if (!tg110) 376 return NULL; 377 378 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 379 return &tg110->base; 380 } 381 382 static struct stream_encoder *dce100_stream_encoder_create( 383 enum engine_id eng_id, 384 struct dc_context *ctx) 385 { 386 struct dce110_stream_encoder *enc110 = 387 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 388 389 if (!enc110) 390 return NULL; 391 392 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 393 &stream_enc_regs[eng_id], &se_shift, &se_mask); 394 return &enc110->base; 395 } 396 397 #define SRII(reg_name, block, id)\ 398 .reg_name[id] = mm ## block ## id ## _ ## reg_name 399 400 static const struct dce_hwseq_registers hwseq_reg = { 401 HWSEQ_DCE10_REG_LIST() 402 }; 403 404 static const struct dce_hwseq_shift hwseq_shift = { 405 HWSEQ_DCE10_MASK_SH_LIST(__SHIFT) 406 }; 407 408 static const struct dce_hwseq_mask hwseq_mask = { 409 HWSEQ_DCE10_MASK_SH_LIST(_MASK) 410 }; 411 412 static struct dce_hwseq *dce100_hwseq_create( 413 struct dc_context *ctx) 414 { 415 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 416 417 if (hws) { 418 hws->ctx = ctx; 419 hws->regs = &hwseq_reg; 420 hws->shifts = &hwseq_shift; 421 hws->masks = &hwseq_mask; 422 } 423 return hws; 424 } 425 426 static const struct resource_create_funcs res_create_funcs = { 427 .read_dce_straps = read_dce_straps, 428 .create_audio = create_audio, 429 .create_stream_encoder = dce100_stream_encoder_create, 430 .create_hwseq = dce100_hwseq_create, 431 }; 432 433 #define mi_inst_regs(id) { \ 434 MI_DCE8_REG_LIST(id), \ 435 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 436 } 437 static const struct dce_mem_input_registers mi_regs[] = { 438 mi_inst_regs(0), 439 mi_inst_regs(1), 440 mi_inst_regs(2), 441 mi_inst_regs(3), 442 mi_inst_regs(4), 443 mi_inst_regs(5), 444 }; 445 446 static const struct dce_mem_input_shift mi_shifts = { 447 MI_DCE8_MASK_SH_LIST(__SHIFT), 448 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 449 }; 450 451 static const struct dce_mem_input_mask mi_masks = { 452 MI_DCE8_MASK_SH_LIST(_MASK), 453 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 454 }; 455 456 static struct mem_input *dce100_mem_input_create( 457 struct dc_context *ctx, 458 uint32_t inst) 459 { 460 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 461 GFP_KERNEL); 462 463 if (!dce_mi) { 464 BREAK_TO_DEBUGGER(); 465 return NULL; 466 } 467 468 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 469 dce_mi->wa.single_head_rdreq_dmif_limit = 2; 470 return &dce_mi->base; 471 } 472 473 static void dce100_transform_destroy(struct transform **xfm) 474 { 475 kfree(TO_DCE_TRANSFORM(*xfm)); 476 *xfm = NULL; 477 } 478 479 static struct transform *dce100_transform_create( 480 struct dc_context *ctx, 481 uint32_t inst) 482 { 483 struct dce_transform *transform = 484 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 485 486 if (!transform) 487 return NULL; 488 489 dce_transform_construct(transform, ctx, inst, 490 &xfm_regs[inst], &xfm_shift, &xfm_mask); 491 return &transform->base; 492 } 493 494 static struct input_pixel_processor *dce100_ipp_create( 495 struct dc_context *ctx, uint32_t inst) 496 { 497 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 498 499 if (!ipp) { 500 BREAK_TO_DEBUGGER(); 501 return NULL; 502 } 503 504 dce_ipp_construct(ipp, ctx, inst, 505 &ipp_regs[inst], &ipp_shift, &ipp_mask); 506 return &ipp->base; 507 } 508 509 static const struct encoder_feature_support link_enc_feature = { 510 .max_hdmi_deep_color = COLOR_DEPTH_121212, 511 .max_hdmi_pixel_clock = 300000, 512 .flags.bits.IS_HBR2_CAPABLE = true, 513 .flags.bits.IS_TPS3_CAPABLE = true, 514 .flags.bits.IS_YCBCR_CAPABLE = true 515 }; 516 517 struct link_encoder *dce100_link_encoder_create( 518 const struct encoder_init_data *enc_init_data) 519 { 520 struct dce110_link_encoder *enc110 = 521 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 522 523 if (!enc110) 524 return NULL; 525 526 dce110_link_encoder_construct(enc110, 527 enc_init_data, 528 &link_enc_feature, 529 &link_enc_regs[enc_init_data->transmitter], 530 &link_enc_aux_regs[enc_init_data->channel - 1], 531 &link_enc_hpd_regs[enc_init_data->hpd_source]); 532 return &enc110->base; 533 } 534 535 struct output_pixel_processor *dce100_opp_create( 536 struct dc_context *ctx, 537 uint32_t inst) 538 { 539 struct dce110_opp *opp = 540 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 541 542 if (!opp) 543 return NULL; 544 545 dce110_opp_construct(opp, 546 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 547 return &opp->base; 548 } 549 550 struct clock_source *dce100_clock_source_create( 551 struct dc_context *ctx, 552 struct dc_bios *bios, 553 enum clock_source_id id, 554 const struct dce110_clk_src_regs *regs, 555 bool dp_clk_src) 556 { 557 struct dce110_clk_src *clk_src = 558 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 559 560 if (!clk_src) 561 return NULL; 562 563 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 564 regs, &cs_shift, &cs_mask)) { 565 clk_src->base.dp_clk_src = dp_clk_src; 566 return &clk_src->base; 567 } 568 569 BREAK_TO_DEBUGGER(); 570 return NULL; 571 } 572 573 void dce100_clock_source_destroy(struct clock_source **clk_src) 574 { 575 kfree(TO_DCE110_CLK_SRC(*clk_src)); 576 *clk_src = NULL; 577 } 578 579 static void destruct(struct dce110_resource_pool *pool) 580 { 581 unsigned int i; 582 583 for (i = 0; i < pool->base.pipe_count; i++) { 584 if (pool->base.opps[i] != NULL) 585 dce110_opp_destroy(&pool->base.opps[i]); 586 587 if (pool->base.transforms[i] != NULL) 588 dce100_transform_destroy(&pool->base.transforms[i]); 589 590 if (pool->base.ipps[i] != NULL) 591 dce_ipp_destroy(&pool->base.ipps[i]); 592 593 if (pool->base.mis[i] != NULL) { 594 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 595 pool->base.mis[i] = NULL; 596 } 597 598 if (pool->base.timing_generators[i] != NULL) { 599 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 600 pool->base.timing_generators[i] = NULL; 601 } 602 } 603 604 for (i = 0; i < pool->base.stream_enc_count; i++) { 605 if (pool->base.stream_enc[i] != NULL) 606 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 607 } 608 609 for (i = 0; i < pool->base.clk_src_count; i++) { 610 if (pool->base.clock_sources[i] != NULL) 611 dce100_clock_source_destroy(&pool->base.clock_sources[i]); 612 } 613 614 if (pool->base.dp_clock_source != NULL) 615 dce100_clock_source_destroy(&pool->base.dp_clock_source); 616 617 for (i = 0; i < pool->base.audio_count; i++) { 618 if (pool->base.audios[i] != NULL) 619 dce_aud_destroy(&pool->base.audios[i]); 620 } 621 622 if (pool->base.display_clock != NULL) 623 dce_disp_clk_destroy(&pool->base.display_clock); 624 625 if (pool->base.irqs != NULL) 626 dal_irq_service_destroy(&pool->base.irqs); 627 } 628 629 static enum dc_status build_mapped_resource( 630 const struct dc *dc, 631 struct dc_state *context, 632 struct dc_stream_state *stream) 633 { 634 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 635 636 if (!pipe_ctx) 637 return DC_ERROR_UNEXPECTED; 638 639 dce110_resource_build_pipe_hw_param(pipe_ctx); 640 641 resource_build_info_frame(pipe_ctx); 642 643 return DC_OK; 644 } 645 646 bool dce100_validate_bandwidth( 647 struct dc *dc, 648 struct dc_state *context) 649 { 650 /* TODO implement when needed but for now hardcode max value*/ 651 context->bw.dce.dispclk_khz = 681000; 652 context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER; 653 654 return true; 655 } 656 657 static bool dce100_validate_surface_sets( 658 struct dc_state *context) 659 { 660 int i; 661 662 for (i = 0; i < context->stream_count; i++) { 663 if (context->stream_status[i].plane_count == 0) 664 continue; 665 666 if (context->stream_status[i].plane_count > 1) 667 return false; 668 669 if (context->stream_status[i].plane_states[0]->format 670 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 671 return false; 672 } 673 674 return true; 675 } 676 677 enum dc_status dce100_validate_global( 678 struct dc *dc, 679 struct dc_state *context) 680 { 681 if (!dce100_validate_surface_sets(context)) 682 return DC_FAIL_SURFACE_VALIDATE; 683 684 return DC_OK; 685 } 686 687 enum dc_status dce100_add_stream_to_ctx( 688 struct dc *dc, 689 struct dc_state *new_ctx, 690 struct dc_stream_state *dc_stream) 691 { 692 enum dc_status result = DC_ERROR_UNEXPECTED; 693 694 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 695 696 if (result == DC_OK) 697 result = resource_map_clock_resources(dc, new_ctx, dc_stream); 698 699 if (result == DC_OK) 700 result = build_mapped_resource(dc, new_ctx, dc_stream); 701 702 return result; 703 } 704 705 enum dc_status dce100_validate_guaranteed( 706 struct dc *dc, 707 struct dc_stream_state *dc_stream, 708 struct dc_state *context) 709 { 710 enum dc_status result = DC_ERROR_UNEXPECTED; 711 712 context->streams[0] = dc_stream; 713 dc_stream_retain(context->streams[0]); 714 context->stream_count++; 715 716 result = resource_map_pool_resources(dc, context, dc_stream); 717 718 if (result == DC_OK) 719 result = resource_map_clock_resources(dc, context, dc_stream); 720 721 if (result == DC_OK) 722 result = build_mapped_resource(dc, context, dc_stream); 723 724 if (result == DC_OK) { 725 validate_guaranteed_copy_streams( 726 context, dc->caps.max_streams); 727 result = resource_build_scaling_params_for_context(dc, context); 728 } 729 730 if (result == DC_OK) 731 if (!dce100_validate_bandwidth(dc, context)) 732 result = DC_FAIL_BANDWIDTH_VALIDATE; 733 734 return result; 735 } 736 737 static void dce100_destroy_resource_pool(struct resource_pool **pool) 738 { 739 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 740 741 destruct(dce110_pool); 742 kfree(dce110_pool); 743 *pool = NULL; 744 } 745 746 enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) 747 { 748 749 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 750 return DC_OK; 751 752 return DC_FAIL_SURFACE_VALIDATE; 753 } 754 755 static const struct resource_funcs dce100_res_pool_funcs = { 756 .destroy = dce100_destroy_resource_pool, 757 .link_enc_create = dce100_link_encoder_create, 758 .validate_guaranteed = dce100_validate_guaranteed, 759 .validate_bandwidth = dce100_validate_bandwidth, 760 .validate_plane = dce100_validate_plane, 761 .add_stream_to_ctx = dce100_add_stream_to_ctx, 762 .validate_global = dce100_validate_global 763 }; 764 765 static bool construct( 766 uint8_t num_virtual_links, 767 struct dc *dc, 768 struct dce110_resource_pool *pool) 769 { 770 unsigned int i; 771 struct dc_context *ctx = dc->ctx; 772 struct dc_firmware_info info; 773 struct dc_bios *bp; 774 struct dm_pp_static_clock_info static_clk_info = {0}; 775 776 ctx->dc_bios->regs = &bios_regs; 777 778 pool->base.res_cap = &res_cap; 779 pool->base.funcs = &dce100_res_pool_funcs; 780 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 781 782 bp = ctx->dc_bios; 783 784 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 785 info.external_clock_source_frequency_for_dp != 0) { 786 pool->base.dp_clock_source = 787 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 788 789 pool->base.clock_sources[0] = 790 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 791 pool->base.clock_sources[1] = 792 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 793 pool->base.clock_sources[2] = 794 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 795 pool->base.clk_src_count = 3; 796 797 } else { 798 pool->base.dp_clock_source = 799 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 800 801 pool->base.clock_sources[0] = 802 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 803 pool->base.clock_sources[1] = 804 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 805 pool->base.clk_src_count = 2; 806 } 807 808 if (pool->base.dp_clock_source == NULL) { 809 dm_error("DC: failed to create dp clock source!\n"); 810 BREAK_TO_DEBUGGER(); 811 goto res_create_fail; 812 } 813 814 for (i = 0; i < pool->base.clk_src_count; i++) { 815 if (pool->base.clock_sources[i] == NULL) { 816 dm_error("DC: failed to create clock sources!\n"); 817 BREAK_TO_DEBUGGER(); 818 goto res_create_fail; 819 } 820 } 821 822 pool->base.display_clock = dce_disp_clk_create(ctx, 823 &disp_clk_regs, 824 &disp_clk_shift, 825 &disp_clk_mask); 826 if (pool->base.display_clock == NULL) { 827 dm_error("DC: failed to create display clock!\n"); 828 BREAK_TO_DEBUGGER(); 829 goto res_create_fail; 830 } 831 832 833 /* get static clock information for PPLIB or firmware, save 834 * max_clock_state 835 */ 836 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 837 pool->base.display_clock->max_clks_state = 838 static_clk_info.max_clocks_state; 839 { 840 struct irq_service_init_data init_data; 841 init_data.ctx = dc->ctx; 842 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 843 if (!pool->base.irqs) 844 goto res_create_fail; 845 } 846 847 /************************************************* 848 * Resource + asic cap harcoding * 849 *************************************************/ 850 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 851 pool->base.pipe_count = res_cap.num_timing_generator; 852 dc->caps.max_downscale_ratio = 200; 853 dc->caps.i2c_speed_in_khz = 40; 854 dc->caps.max_cursor_size = 128; 855 856 for (i = 0; i < pool->base.pipe_count; i++) { 857 pool->base.timing_generators[i] = 858 dce100_timing_generator_create( 859 ctx, 860 i, 861 &dce100_tg_offsets[i]); 862 if (pool->base.timing_generators[i] == NULL) { 863 BREAK_TO_DEBUGGER(); 864 dm_error("DC: failed to create tg!\n"); 865 goto res_create_fail; 866 } 867 868 pool->base.mis[i] = dce100_mem_input_create(ctx, i); 869 if (pool->base.mis[i] == NULL) { 870 BREAK_TO_DEBUGGER(); 871 dm_error( 872 "DC: failed to create memory input!\n"); 873 goto res_create_fail; 874 } 875 876 pool->base.ipps[i] = dce100_ipp_create(ctx, i); 877 if (pool->base.ipps[i] == NULL) { 878 BREAK_TO_DEBUGGER(); 879 dm_error( 880 "DC: failed to create input pixel processor!\n"); 881 goto res_create_fail; 882 } 883 884 pool->base.transforms[i] = dce100_transform_create(ctx, i); 885 if (pool->base.transforms[i] == NULL) { 886 BREAK_TO_DEBUGGER(); 887 dm_error( 888 "DC: failed to create transform!\n"); 889 goto res_create_fail; 890 } 891 892 pool->base.opps[i] = dce100_opp_create(ctx, i); 893 if (pool->base.opps[i] == NULL) { 894 BREAK_TO_DEBUGGER(); 895 dm_error( 896 "DC: failed to create output pixel processor!\n"); 897 goto res_create_fail; 898 } 899 } 900 901 dc->caps.max_planes = pool->base.pipe_count; 902 903 if (!resource_construct(num_virtual_links, dc, &pool->base, 904 &res_create_funcs)) 905 goto res_create_fail; 906 907 /* Create hardware sequencer */ 908 dce100_hw_sequencer_construct(dc); 909 return true; 910 911 res_create_fail: 912 destruct(pool); 913 914 return false; 915 } 916 917 struct resource_pool *dce100_create_resource_pool( 918 uint8_t num_virtual_links, 919 struct dc *dc) 920 { 921 struct dce110_resource_pool *pool = 922 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 923 924 if (!pool) 925 return NULL; 926 927 if (construct(num_virtual_links, dc, pool)) 928 return &pool->base; 929 930 BREAK_TO_DEBUGGER(); 931 return NULL; 932 } 933 934