1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include "dm_services.h" 26 27 #include "link_encoder.h" 28 #include "stream_encoder.h" 29 30 #include "resource.h" 31 #include "include/irq_service_interface.h" 32 #include "../virtual/virtual_stream_encoder.h" 33 #include "dce110/dce110_resource.h" 34 #include "dce110/dce110_timing_generator.h" 35 #include "irq/dce110/irq_service_dce110.h" 36 #include "dce/dce_link_encoder.h" 37 #include "dce/dce_stream_encoder.h" 38 39 #include "dce/dce_clk_mgr.h" 40 #include "dce/dce_mem_input.h" 41 #include "dce/dce_ipp.h" 42 #include "dce/dce_transform.h" 43 #include "dce/dce_opp.h" 44 #include "dce/dce_clock_source.h" 45 #include "dce/dce_audio.h" 46 #include "dce/dce_hwseq.h" 47 #include "dce100/dce100_hw_sequencer.h" 48 49 #include "reg_helper.h" 50 51 #include "dce/dce_10_0_d.h" 52 #include "dce/dce_10_0_sh_mask.h" 53 54 #include "dce/dce_dmcu.h" 55 #include "dce/dce_aux.h" 56 #include "dce/dce_abm.h" 57 #include "dce/dce_i2c.h" 58 59 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 60 #include "gmc/gmc_8_2_d.h" 61 #include "gmc/gmc_8_2_sh_mask.h" 62 #endif 63 64 #ifndef mmDP_DPHY_INTERNAL_CTRL 65 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 66 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 67 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 68 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 69 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 70 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 71 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 72 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 73 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 74 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 75 #endif 76 77 #ifndef mmBIOS_SCRATCH_2 78 #define mmBIOS_SCRATCH_2 0x05CB 79 #define mmBIOS_SCRATCH_3 0x05CC 80 #define mmBIOS_SCRATCH_6 0x05CF 81 #endif 82 83 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 84 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 85 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 86 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 87 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 88 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 89 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 90 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 91 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 92 #endif 93 94 #ifndef mmDP_DPHY_FAST_TRAINING 95 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 96 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 97 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 98 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 99 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 100 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 101 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 102 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 103 #endif 104 105 static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = { 106 { 107 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 108 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 109 }, 110 { 111 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 112 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 113 }, 114 { 115 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 116 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 117 }, 118 { 119 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 120 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 121 }, 122 { 123 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 124 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 125 }, 126 { 127 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 128 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 129 } 130 }; 131 132 /* set register offset */ 133 #define SR(reg_name)\ 134 .reg_name = mm ## reg_name 135 136 /* set register offset with instance */ 137 #define SRI(reg_name, block, id)\ 138 .reg_name = mm ## block ## id ## _ ## reg_name 139 140 141 static const struct clk_mgr_registers disp_clk_regs = { 142 CLK_COMMON_REG_LIST_DCE_BASE() 143 }; 144 145 static const struct clk_mgr_shift disp_clk_shift = { 146 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 147 }; 148 149 static const struct clk_mgr_mask disp_clk_mask = { 150 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 151 }; 152 153 #define ipp_regs(id)\ 154 [id] = {\ 155 IPP_DCE100_REG_LIST_DCE_BASE(id)\ 156 } 157 158 static const struct dce_ipp_registers ipp_regs[] = { 159 ipp_regs(0), 160 ipp_regs(1), 161 ipp_regs(2), 162 ipp_regs(3), 163 ipp_regs(4), 164 ipp_regs(5) 165 }; 166 167 static const struct dce_ipp_shift ipp_shift = { 168 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 169 }; 170 171 static const struct dce_ipp_mask ipp_mask = { 172 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 173 }; 174 175 #define transform_regs(id)\ 176 [id] = {\ 177 XFM_COMMON_REG_LIST_DCE100(id)\ 178 } 179 180 static const struct dce_transform_registers xfm_regs[] = { 181 transform_regs(0), 182 transform_regs(1), 183 transform_regs(2), 184 transform_regs(3), 185 transform_regs(4), 186 transform_regs(5) 187 }; 188 189 static const struct dce_transform_shift xfm_shift = { 190 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 191 }; 192 193 static const struct dce_transform_mask xfm_mask = { 194 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 195 }; 196 197 #define aux_regs(id)\ 198 [id] = {\ 199 AUX_REG_LIST(id)\ 200 } 201 202 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 203 aux_regs(0), 204 aux_regs(1), 205 aux_regs(2), 206 aux_regs(3), 207 aux_regs(4), 208 aux_regs(5) 209 }; 210 211 #define hpd_regs(id)\ 212 [id] = {\ 213 HPD_REG_LIST(id)\ 214 } 215 216 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 217 hpd_regs(0), 218 hpd_regs(1), 219 hpd_regs(2), 220 hpd_regs(3), 221 hpd_regs(4), 222 hpd_regs(5) 223 }; 224 225 #define link_regs(id)\ 226 [id] = {\ 227 LE_DCE100_REG_LIST(id)\ 228 } 229 230 static const struct dce110_link_enc_registers link_enc_regs[] = { 231 link_regs(0), 232 link_regs(1), 233 link_regs(2), 234 link_regs(3), 235 link_regs(4), 236 link_regs(5), 237 link_regs(6), 238 }; 239 240 #define stream_enc_regs(id)\ 241 [id] = {\ 242 SE_COMMON_REG_LIST_DCE_BASE(id),\ 243 .AFMT_CNTL = 0,\ 244 } 245 246 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 247 stream_enc_regs(0), 248 stream_enc_regs(1), 249 stream_enc_regs(2), 250 stream_enc_regs(3), 251 stream_enc_regs(4), 252 stream_enc_regs(5), 253 stream_enc_regs(6) 254 }; 255 256 static const struct dce_stream_encoder_shift se_shift = { 257 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) 258 }; 259 260 static const struct dce_stream_encoder_mask se_mask = { 261 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) 262 }; 263 264 #define opp_regs(id)\ 265 [id] = {\ 266 OPP_DCE_100_REG_LIST(id),\ 267 } 268 269 static const struct dce_opp_registers opp_regs[] = { 270 opp_regs(0), 271 opp_regs(1), 272 opp_regs(2), 273 opp_regs(3), 274 opp_regs(4), 275 opp_regs(5) 276 }; 277 278 static const struct dce_opp_shift opp_shift = { 279 OPP_COMMON_MASK_SH_LIST_DCE_100(__SHIFT) 280 }; 281 282 static const struct dce_opp_mask opp_mask = { 283 OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK) 284 }; 285 #define aux_engine_regs(id)\ 286 [id] = {\ 287 AUX_COMMON_REG_LIST(id), \ 288 .AUX_RESET_MASK = 0 \ 289 } 290 291 static const struct dce110_aux_registers aux_engine_regs[] = { 292 aux_engine_regs(0), 293 aux_engine_regs(1), 294 aux_engine_regs(2), 295 aux_engine_regs(3), 296 aux_engine_regs(4), 297 aux_engine_regs(5) 298 }; 299 300 #define audio_regs(id)\ 301 [id] = {\ 302 AUD_COMMON_REG_LIST(id)\ 303 } 304 305 static const struct dce_audio_registers audio_regs[] = { 306 audio_regs(0), 307 audio_regs(1), 308 audio_regs(2), 309 audio_regs(3), 310 audio_regs(4), 311 audio_regs(5), 312 audio_regs(6), 313 }; 314 315 static const struct dce_audio_shift audio_shift = { 316 AUD_COMMON_MASK_SH_LIST(__SHIFT) 317 }; 318 319 static const struct dce_aduio_mask audio_mask = { 320 AUD_COMMON_MASK_SH_LIST(_MASK) 321 }; 322 323 #define clk_src_regs(id)\ 324 [id] = {\ 325 CS_COMMON_REG_LIST_DCE_100_110(id),\ 326 } 327 328 static const struct dce110_clk_src_regs clk_src_regs[] = { 329 clk_src_regs(0), 330 clk_src_regs(1), 331 clk_src_regs(2) 332 }; 333 334 static const struct dce110_clk_src_shift cs_shift = { 335 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 336 }; 337 338 static const struct dce110_clk_src_mask cs_mask = { 339 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 340 }; 341 342 static const struct dce_dmcu_registers dmcu_regs = { 343 DMCU_DCE110_COMMON_REG_LIST() 344 }; 345 346 static const struct dce_dmcu_shift dmcu_shift = { 347 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 348 }; 349 350 static const struct dce_dmcu_mask dmcu_mask = { 351 DMCU_MASK_SH_LIST_DCE110(_MASK) 352 }; 353 354 static const struct dce_abm_registers abm_regs = { 355 ABM_DCE110_COMMON_REG_LIST() 356 }; 357 358 static const struct dce_abm_shift abm_shift = { 359 ABM_MASK_SH_LIST_DCE110(__SHIFT) 360 }; 361 362 static const struct dce_abm_mask abm_mask = { 363 ABM_MASK_SH_LIST_DCE110(_MASK) 364 }; 365 366 #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03 367 368 static const struct bios_registers bios_regs = { 369 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 370 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 371 }; 372 373 static const struct resource_caps res_cap = { 374 .num_timing_generator = 6, 375 .num_audio = 6, 376 .num_stream_encoder = 6, 377 .num_pll = 3, 378 .num_ddc = 6, 379 }; 380 381 static const struct dc_plane_cap plane_cap = { 382 .type = DC_PLANE_TYPE_DCE_RGB, 383 .supports_argb8888 = true, 384 }; 385 386 #define CTX ctx 387 #define REG(reg) mm ## reg 388 389 #ifndef mmCC_DC_HDMI_STRAPS 390 #define mmCC_DC_HDMI_STRAPS 0x1918 391 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 392 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 393 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 394 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 395 #endif 396 397 static void read_dce_straps( 398 struct dc_context *ctx, 399 struct resource_straps *straps) 400 { 401 REG_GET_2(CC_DC_HDMI_STRAPS, 402 HDMI_DISABLE, &straps->hdmi_disable, 403 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 404 405 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 406 } 407 408 static struct audio *create_audio( 409 struct dc_context *ctx, unsigned int inst) 410 { 411 return dce_audio_create(ctx, inst, 412 &audio_regs[inst], &audio_shift, &audio_mask); 413 } 414 415 static struct timing_generator *dce100_timing_generator_create( 416 struct dc_context *ctx, 417 uint32_t instance, 418 const struct dce110_timing_generator_offsets *offsets) 419 { 420 struct dce110_timing_generator *tg110 = 421 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 422 423 if (!tg110) 424 return NULL; 425 426 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 427 return &tg110->base; 428 } 429 430 static struct stream_encoder *dce100_stream_encoder_create( 431 enum engine_id eng_id, 432 struct dc_context *ctx) 433 { 434 struct dce110_stream_encoder *enc110 = 435 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 436 437 if (!enc110) 438 return NULL; 439 440 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 441 &stream_enc_regs[eng_id], &se_shift, &se_mask); 442 return &enc110->base; 443 } 444 445 #define SRII(reg_name, block, id)\ 446 .reg_name[id] = mm ## block ## id ## _ ## reg_name 447 448 static const struct dce_hwseq_registers hwseq_reg = { 449 HWSEQ_DCE10_REG_LIST() 450 }; 451 452 static const struct dce_hwseq_shift hwseq_shift = { 453 HWSEQ_DCE10_MASK_SH_LIST(__SHIFT) 454 }; 455 456 static const struct dce_hwseq_mask hwseq_mask = { 457 HWSEQ_DCE10_MASK_SH_LIST(_MASK) 458 }; 459 460 static struct dce_hwseq *dce100_hwseq_create( 461 struct dc_context *ctx) 462 { 463 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 464 465 if (hws) { 466 hws->ctx = ctx; 467 hws->regs = &hwseq_reg; 468 hws->shifts = &hwseq_shift; 469 hws->masks = &hwseq_mask; 470 } 471 return hws; 472 } 473 474 static const struct resource_create_funcs res_create_funcs = { 475 .read_dce_straps = read_dce_straps, 476 .create_audio = create_audio, 477 .create_stream_encoder = dce100_stream_encoder_create, 478 .create_hwseq = dce100_hwseq_create, 479 }; 480 481 #define mi_inst_regs(id) { \ 482 MI_DCE8_REG_LIST(id), \ 483 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 484 } 485 static const struct dce_mem_input_registers mi_regs[] = { 486 mi_inst_regs(0), 487 mi_inst_regs(1), 488 mi_inst_regs(2), 489 mi_inst_regs(3), 490 mi_inst_regs(4), 491 mi_inst_regs(5), 492 }; 493 494 static const struct dce_mem_input_shift mi_shifts = { 495 MI_DCE8_MASK_SH_LIST(__SHIFT), 496 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 497 }; 498 499 static const struct dce_mem_input_mask mi_masks = { 500 MI_DCE8_MASK_SH_LIST(_MASK), 501 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 502 }; 503 504 static struct mem_input *dce100_mem_input_create( 505 struct dc_context *ctx, 506 uint32_t inst) 507 { 508 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 509 GFP_KERNEL); 510 511 if (!dce_mi) { 512 BREAK_TO_DEBUGGER(); 513 return NULL; 514 } 515 516 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 517 dce_mi->wa.single_head_rdreq_dmif_limit = 2; 518 return &dce_mi->base; 519 } 520 521 static void dce100_transform_destroy(struct transform **xfm) 522 { 523 kfree(TO_DCE_TRANSFORM(*xfm)); 524 *xfm = NULL; 525 } 526 527 static struct transform *dce100_transform_create( 528 struct dc_context *ctx, 529 uint32_t inst) 530 { 531 struct dce_transform *transform = 532 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 533 534 if (!transform) 535 return NULL; 536 537 dce_transform_construct(transform, ctx, inst, 538 &xfm_regs[inst], &xfm_shift, &xfm_mask); 539 return &transform->base; 540 } 541 542 static struct input_pixel_processor *dce100_ipp_create( 543 struct dc_context *ctx, uint32_t inst) 544 { 545 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 546 547 if (!ipp) { 548 BREAK_TO_DEBUGGER(); 549 return NULL; 550 } 551 552 dce_ipp_construct(ipp, ctx, inst, 553 &ipp_regs[inst], &ipp_shift, &ipp_mask); 554 return &ipp->base; 555 } 556 557 static const struct encoder_feature_support link_enc_feature = { 558 .max_hdmi_deep_color = COLOR_DEPTH_121212, 559 .max_hdmi_pixel_clock = 300000, 560 .flags.bits.IS_HBR2_CAPABLE = true, 561 .flags.bits.IS_TPS3_CAPABLE = true 562 }; 563 564 struct link_encoder *dce100_link_encoder_create( 565 const struct encoder_init_data *enc_init_data) 566 { 567 struct dce110_link_encoder *enc110 = 568 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 569 570 if (!enc110) 571 return NULL; 572 573 dce110_link_encoder_construct(enc110, 574 enc_init_data, 575 &link_enc_feature, 576 &link_enc_regs[enc_init_data->transmitter], 577 &link_enc_aux_regs[enc_init_data->channel - 1], 578 &link_enc_hpd_regs[enc_init_data->hpd_source]); 579 return &enc110->base; 580 } 581 582 struct output_pixel_processor *dce100_opp_create( 583 struct dc_context *ctx, 584 uint32_t inst) 585 { 586 struct dce110_opp *opp = 587 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 588 589 if (!opp) 590 return NULL; 591 592 dce110_opp_construct(opp, 593 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 594 return &opp->base; 595 } 596 597 struct dce_aux *dce100_aux_engine_create( 598 struct dc_context *ctx, 599 uint32_t inst) 600 { 601 struct aux_engine_dce110 *aux_engine = 602 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 603 604 if (!aux_engine) 605 return NULL; 606 607 dce110_aux_engine_construct(aux_engine, ctx, inst, 608 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 609 &aux_engine_regs[inst]); 610 611 return &aux_engine->base; 612 } 613 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 614 615 static const struct dce_i2c_registers i2c_hw_regs[] = { 616 i2c_inst_regs(1), 617 i2c_inst_regs(2), 618 i2c_inst_regs(3), 619 i2c_inst_regs(4), 620 i2c_inst_regs(5), 621 i2c_inst_regs(6), 622 }; 623 624 static const struct dce_i2c_shift i2c_shifts = { 625 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 626 }; 627 628 static const struct dce_i2c_mask i2c_masks = { 629 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 630 }; 631 632 struct dce_i2c_hw *dce100_i2c_hw_create( 633 struct dc_context *ctx, 634 uint32_t inst) 635 { 636 struct dce_i2c_hw *dce_i2c_hw = 637 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 638 639 if (!dce_i2c_hw) 640 return NULL; 641 642 dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst, 643 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 644 645 return dce_i2c_hw; 646 } 647 struct clock_source *dce100_clock_source_create( 648 struct dc_context *ctx, 649 struct dc_bios *bios, 650 enum clock_source_id id, 651 const struct dce110_clk_src_regs *regs, 652 bool dp_clk_src) 653 { 654 struct dce110_clk_src *clk_src = 655 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 656 657 if (!clk_src) 658 return NULL; 659 660 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 661 regs, &cs_shift, &cs_mask)) { 662 clk_src->base.dp_clk_src = dp_clk_src; 663 return &clk_src->base; 664 } 665 666 BREAK_TO_DEBUGGER(); 667 return NULL; 668 } 669 670 void dce100_clock_source_destroy(struct clock_source **clk_src) 671 { 672 kfree(TO_DCE110_CLK_SRC(*clk_src)); 673 *clk_src = NULL; 674 } 675 676 static void destruct(struct dce110_resource_pool *pool) 677 { 678 unsigned int i; 679 680 for (i = 0; i < pool->base.pipe_count; i++) { 681 if (pool->base.opps[i] != NULL) 682 dce110_opp_destroy(&pool->base.opps[i]); 683 684 if (pool->base.transforms[i] != NULL) 685 dce100_transform_destroy(&pool->base.transforms[i]); 686 687 if (pool->base.ipps[i] != NULL) 688 dce_ipp_destroy(&pool->base.ipps[i]); 689 690 if (pool->base.mis[i] != NULL) { 691 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 692 pool->base.mis[i] = NULL; 693 } 694 695 if (pool->base.timing_generators[i] != NULL) { 696 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 697 pool->base.timing_generators[i] = NULL; 698 } 699 } 700 701 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 702 if (pool->base.engines[i] != NULL) 703 dce110_engine_destroy(&pool->base.engines[i]); 704 if (pool->base.hw_i2cs[i] != NULL) { 705 kfree(pool->base.hw_i2cs[i]); 706 pool->base.hw_i2cs[i] = NULL; 707 } 708 if (pool->base.sw_i2cs[i] != NULL) { 709 kfree(pool->base.sw_i2cs[i]); 710 pool->base.sw_i2cs[i] = NULL; 711 } 712 } 713 714 for (i = 0; i < pool->base.stream_enc_count; i++) { 715 if (pool->base.stream_enc[i] != NULL) 716 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 717 } 718 719 for (i = 0; i < pool->base.clk_src_count; i++) { 720 if (pool->base.clock_sources[i] != NULL) 721 dce100_clock_source_destroy(&pool->base.clock_sources[i]); 722 } 723 724 if (pool->base.dp_clock_source != NULL) 725 dce100_clock_source_destroy(&pool->base.dp_clock_source); 726 727 for (i = 0; i < pool->base.audio_count; i++) { 728 if (pool->base.audios[i] != NULL) 729 dce_aud_destroy(&pool->base.audios[i]); 730 } 731 732 if (pool->base.clk_mgr != NULL) 733 dce_clk_mgr_destroy(&pool->base.clk_mgr); 734 735 if (pool->base.abm != NULL) 736 dce_abm_destroy(&pool->base.abm); 737 738 if (pool->base.dmcu != NULL) 739 dce_dmcu_destroy(&pool->base.dmcu); 740 741 if (pool->base.irqs != NULL) 742 dal_irq_service_destroy(&pool->base.irqs); 743 } 744 745 static enum dc_status build_mapped_resource( 746 const struct dc *dc, 747 struct dc_state *context, 748 struct dc_stream_state *stream) 749 { 750 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 751 752 if (!pipe_ctx) 753 return DC_ERROR_UNEXPECTED; 754 755 dce110_resource_build_pipe_hw_param(pipe_ctx); 756 757 resource_build_info_frame(pipe_ctx); 758 759 return DC_OK; 760 } 761 762 bool dce100_validate_bandwidth( 763 struct dc *dc, 764 struct dc_state *context) 765 { 766 int i; 767 bool at_least_one_pipe = false; 768 769 for (i = 0; i < dc->res_pool->pipe_count; i++) { 770 if (context->res_ctx.pipe_ctx[i].stream) 771 at_least_one_pipe = true; 772 } 773 774 if (at_least_one_pipe) { 775 /* TODO implement when needed but for now hardcode max value*/ 776 context->bw.dce.dispclk_khz = 681000; 777 context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; 778 } else { 779 context->bw.dce.dispclk_khz = 0; 780 context->bw.dce.yclk_khz = 0; 781 } 782 783 return true; 784 } 785 786 static bool dce100_validate_surface_sets( 787 struct dc_state *context) 788 { 789 int i; 790 791 for (i = 0; i < context->stream_count; i++) { 792 if (context->stream_status[i].plane_count == 0) 793 continue; 794 795 if (context->stream_status[i].plane_count > 1) 796 return false; 797 798 if (context->stream_status[i].plane_states[0]->format 799 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 800 return false; 801 } 802 803 return true; 804 } 805 806 enum dc_status dce100_validate_global( 807 struct dc *dc, 808 struct dc_state *context) 809 { 810 if (!dce100_validate_surface_sets(context)) 811 return DC_FAIL_SURFACE_VALIDATE; 812 813 return DC_OK; 814 } 815 816 enum dc_status dce100_add_stream_to_ctx( 817 struct dc *dc, 818 struct dc_state *new_ctx, 819 struct dc_stream_state *dc_stream) 820 { 821 enum dc_status result = DC_ERROR_UNEXPECTED; 822 823 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 824 825 if (result == DC_OK) 826 result = resource_map_clock_resources(dc, new_ctx, dc_stream); 827 828 if (result == DC_OK) 829 result = build_mapped_resource(dc, new_ctx, dc_stream); 830 831 return result; 832 } 833 834 static void dce100_destroy_resource_pool(struct resource_pool **pool) 835 { 836 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 837 838 destruct(dce110_pool); 839 kfree(dce110_pool); 840 *pool = NULL; 841 } 842 843 enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) 844 { 845 846 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 847 return DC_OK; 848 849 return DC_FAIL_SURFACE_VALIDATE; 850 } 851 852 static const struct resource_funcs dce100_res_pool_funcs = { 853 .destroy = dce100_destroy_resource_pool, 854 .link_enc_create = dce100_link_encoder_create, 855 .validate_bandwidth = dce100_validate_bandwidth, 856 .validate_plane = dce100_validate_plane, 857 .add_stream_to_ctx = dce100_add_stream_to_ctx, 858 .validate_global = dce100_validate_global 859 }; 860 861 static bool construct( 862 uint8_t num_virtual_links, 863 struct dc *dc, 864 struct dce110_resource_pool *pool) 865 { 866 unsigned int i; 867 struct dc_context *ctx = dc->ctx; 868 struct dc_firmware_info info; 869 struct dc_bios *bp; 870 871 ctx->dc_bios->regs = &bios_regs; 872 873 pool->base.res_cap = &res_cap; 874 pool->base.funcs = &dce100_res_pool_funcs; 875 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 876 877 bp = ctx->dc_bios; 878 879 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 880 info.external_clock_source_frequency_for_dp != 0) { 881 pool->base.dp_clock_source = 882 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 883 884 pool->base.clock_sources[0] = 885 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 886 pool->base.clock_sources[1] = 887 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 888 pool->base.clock_sources[2] = 889 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 890 pool->base.clk_src_count = 3; 891 892 } else { 893 pool->base.dp_clock_source = 894 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 895 896 pool->base.clock_sources[0] = 897 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 898 pool->base.clock_sources[1] = 899 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 900 pool->base.clk_src_count = 2; 901 } 902 903 if (pool->base.dp_clock_source == NULL) { 904 dm_error("DC: failed to create dp clock source!\n"); 905 BREAK_TO_DEBUGGER(); 906 goto res_create_fail; 907 } 908 909 for (i = 0; i < pool->base.clk_src_count; i++) { 910 if (pool->base.clock_sources[i] == NULL) { 911 dm_error("DC: failed to create clock sources!\n"); 912 BREAK_TO_DEBUGGER(); 913 goto res_create_fail; 914 } 915 } 916 917 pool->base.clk_mgr = dce_clk_mgr_create(ctx, 918 &disp_clk_regs, 919 &disp_clk_shift, 920 &disp_clk_mask); 921 if (pool->base.clk_mgr == NULL) { 922 dm_error("DC: failed to create display clock!\n"); 923 BREAK_TO_DEBUGGER(); 924 goto res_create_fail; 925 } 926 927 pool->base.dmcu = dce_dmcu_create(ctx, 928 &dmcu_regs, 929 &dmcu_shift, 930 &dmcu_mask); 931 if (pool->base.dmcu == NULL) { 932 dm_error("DC: failed to create dmcu!\n"); 933 BREAK_TO_DEBUGGER(); 934 goto res_create_fail; 935 } 936 937 pool->base.abm = dce_abm_create(ctx, 938 &abm_regs, 939 &abm_shift, 940 &abm_mask); 941 if (pool->base.abm == NULL) { 942 dm_error("DC: failed to create abm!\n"); 943 BREAK_TO_DEBUGGER(); 944 goto res_create_fail; 945 } 946 947 { 948 struct irq_service_init_data init_data; 949 init_data.ctx = dc->ctx; 950 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 951 if (!pool->base.irqs) 952 goto res_create_fail; 953 } 954 955 /************************************************* 956 * Resource + asic cap harcoding * 957 *************************************************/ 958 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 959 pool->base.pipe_count = res_cap.num_timing_generator; 960 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 961 dc->caps.max_downscale_ratio = 200; 962 dc->caps.i2c_speed_in_khz = 40; 963 dc->caps.max_cursor_size = 128; 964 dc->caps.dual_link_dvi = true; 965 dc->caps.disable_dp_clk_share = true; 966 for (i = 0; i < pool->base.pipe_count; i++) { 967 pool->base.timing_generators[i] = 968 dce100_timing_generator_create( 969 ctx, 970 i, 971 &dce100_tg_offsets[i]); 972 if (pool->base.timing_generators[i] == NULL) { 973 BREAK_TO_DEBUGGER(); 974 dm_error("DC: failed to create tg!\n"); 975 goto res_create_fail; 976 } 977 978 pool->base.mis[i] = dce100_mem_input_create(ctx, i); 979 if (pool->base.mis[i] == NULL) { 980 BREAK_TO_DEBUGGER(); 981 dm_error( 982 "DC: failed to create memory input!\n"); 983 goto res_create_fail; 984 } 985 986 pool->base.ipps[i] = dce100_ipp_create(ctx, i); 987 if (pool->base.ipps[i] == NULL) { 988 BREAK_TO_DEBUGGER(); 989 dm_error( 990 "DC: failed to create input pixel processor!\n"); 991 goto res_create_fail; 992 } 993 994 pool->base.transforms[i] = dce100_transform_create(ctx, i); 995 if (pool->base.transforms[i] == NULL) { 996 BREAK_TO_DEBUGGER(); 997 dm_error( 998 "DC: failed to create transform!\n"); 999 goto res_create_fail; 1000 } 1001 1002 pool->base.opps[i] = dce100_opp_create(ctx, i); 1003 if (pool->base.opps[i] == NULL) { 1004 BREAK_TO_DEBUGGER(); 1005 dm_error( 1006 "DC: failed to create output pixel processor!\n"); 1007 goto res_create_fail; 1008 } 1009 } 1010 1011 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1012 pool->base.engines[i] = dce100_aux_engine_create(ctx, i); 1013 if (pool->base.engines[i] == NULL) { 1014 BREAK_TO_DEBUGGER(); 1015 dm_error( 1016 "DC:failed to create aux engine!!\n"); 1017 goto res_create_fail; 1018 } 1019 pool->base.hw_i2cs[i] = dce100_i2c_hw_create(ctx, i); 1020 if (pool->base.hw_i2cs[i] == NULL) { 1021 BREAK_TO_DEBUGGER(); 1022 dm_error( 1023 "DC:failed to create i2c engine!!\n"); 1024 goto res_create_fail; 1025 } 1026 pool->base.sw_i2cs[i] = NULL; 1027 } 1028 1029 dc->caps.max_planes = pool->base.pipe_count; 1030 1031 for (i = 0; i < dc->caps.max_planes; ++i) 1032 dc->caps.planes[i] = plane_cap; 1033 1034 if (!resource_construct(num_virtual_links, dc, &pool->base, 1035 &res_create_funcs)) 1036 goto res_create_fail; 1037 1038 /* Create hardware sequencer */ 1039 dce100_hw_sequencer_construct(dc); 1040 return true; 1041 1042 res_create_fail: 1043 destruct(pool); 1044 1045 return false; 1046 } 1047 1048 struct resource_pool *dce100_create_resource_pool( 1049 uint8_t num_virtual_links, 1050 struct dc *dc) 1051 { 1052 struct dce110_resource_pool *pool = 1053 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1054 1055 if (!pool) 1056 return NULL; 1057 1058 if (construct(num_virtual_links, dc, pool)) 1059 return &pool->base; 1060 1061 BREAK_TO_DEBUGGER(); 1062 return NULL; 1063 } 1064 1065