1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include "dm_services.h" 26 27 #include "link_encoder.h" 28 #include "stream_encoder.h" 29 30 #include "resource.h" 31 #include "include/irq_service_interface.h" 32 #include "../virtual/virtual_stream_encoder.h" 33 #include "dce110/dce110_resource.h" 34 #include "dce110/dce110_timing_generator.h" 35 #include "irq/dce110/irq_service_dce110.h" 36 #include "dce/dce_link_encoder.h" 37 #include "dce/dce_stream_encoder.h" 38 #include "dce/dce_mem_input.h" 39 #include "dce/dce_ipp.h" 40 #include "dce/dce_transform.h" 41 #include "dce/dce_opp.h" 42 #include "dce/dce_clock_source.h" 43 #include "dce/dce_audio.h" 44 #include "dce/dce_hwseq.h" 45 #include "dce100/dce100_hw_sequencer.h" 46 47 #include "reg_helper.h" 48 49 #include "dce/dce_10_0_d.h" 50 #include "dce/dce_10_0_sh_mask.h" 51 52 #include "dce/dce_dmcu.h" 53 #include "dce/dce_aux.h" 54 #include "dce/dce_abm.h" 55 #include "dce/dce_i2c.h" 56 57 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 58 #include "gmc/gmc_8_2_d.h" 59 #include "gmc/gmc_8_2_sh_mask.h" 60 #endif 61 62 #ifndef mmDP_DPHY_INTERNAL_CTRL 63 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 64 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 65 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 66 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 67 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 68 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 69 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 70 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 71 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 72 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 73 #endif 74 75 #ifndef mmBIOS_SCRATCH_2 76 #define mmBIOS_SCRATCH_2 0x05CB 77 #define mmBIOS_SCRATCH_3 0x05CC 78 #define mmBIOS_SCRATCH_6 0x05CF 79 #endif 80 81 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 82 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 83 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 84 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 85 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 86 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 87 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 88 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 89 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 90 #endif 91 92 #ifndef mmDP_DPHY_FAST_TRAINING 93 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 94 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 95 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 96 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 97 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 98 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 99 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 100 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 101 #endif 102 103 static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = { 104 { 105 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 106 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 107 }, 108 { 109 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 110 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 111 }, 112 { 113 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 114 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 115 }, 116 { 117 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 118 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 119 }, 120 { 121 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 122 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 123 }, 124 { 125 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 126 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 127 } 128 }; 129 130 /* set register offset */ 131 #define SR(reg_name)\ 132 .reg_name = mm ## reg_name 133 134 /* set register offset with instance */ 135 #define SRI(reg_name, block, id)\ 136 .reg_name = mm ## block ## id ## _ ## reg_name 137 138 #define ipp_regs(id)\ 139 [id] = {\ 140 IPP_DCE100_REG_LIST_DCE_BASE(id)\ 141 } 142 143 static const struct dce_ipp_registers ipp_regs[] = { 144 ipp_regs(0), 145 ipp_regs(1), 146 ipp_regs(2), 147 ipp_regs(3), 148 ipp_regs(4), 149 ipp_regs(5) 150 }; 151 152 static const struct dce_ipp_shift ipp_shift = { 153 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 154 }; 155 156 static const struct dce_ipp_mask ipp_mask = { 157 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 158 }; 159 160 #define transform_regs(id)\ 161 [id] = {\ 162 XFM_COMMON_REG_LIST_DCE100(id)\ 163 } 164 165 static const struct dce_transform_registers xfm_regs[] = { 166 transform_regs(0), 167 transform_regs(1), 168 transform_regs(2), 169 transform_regs(3), 170 transform_regs(4), 171 transform_regs(5) 172 }; 173 174 static const struct dce_transform_shift xfm_shift = { 175 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 176 }; 177 178 static const struct dce_transform_mask xfm_mask = { 179 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 180 }; 181 182 #define aux_regs(id)\ 183 [id] = {\ 184 AUX_REG_LIST(id)\ 185 } 186 187 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 188 aux_regs(0), 189 aux_regs(1), 190 aux_regs(2), 191 aux_regs(3), 192 aux_regs(4), 193 aux_regs(5) 194 }; 195 196 #define hpd_regs(id)\ 197 [id] = {\ 198 HPD_REG_LIST(id)\ 199 } 200 201 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 202 hpd_regs(0), 203 hpd_regs(1), 204 hpd_regs(2), 205 hpd_regs(3), 206 hpd_regs(4), 207 hpd_regs(5) 208 }; 209 210 #define link_regs(id)\ 211 [id] = {\ 212 LE_DCE100_REG_LIST(id)\ 213 } 214 215 static const struct dce110_link_enc_registers link_enc_regs[] = { 216 link_regs(0), 217 link_regs(1), 218 link_regs(2), 219 link_regs(3), 220 link_regs(4), 221 link_regs(5), 222 link_regs(6), 223 }; 224 225 #define stream_enc_regs(id)\ 226 [id] = {\ 227 SE_COMMON_REG_LIST_DCE_BASE(id),\ 228 .AFMT_CNTL = 0,\ 229 } 230 231 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 232 stream_enc_regs(0), 233 stream_enc_regs(1), 234 stream_enc_regs(2), 235 stream_enc_regs(3), 236 stream_enc_regs(4), 237 stream_enc_regs(5), 238 stream_enc_regs(6) 239 }; 240 241 static const struct dce_stream_encoder_shift se_shift = { 242 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) 243 }; 244 245 static const struct dce_stream_encoder_mask se_mask = { 246 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) 247 }; 248 249 #define opp_regs(id)\ 250 [id] = {\ 251 OPP_DCE_100_REG_LIST(id),\ 252 } 253 254 static const struct dce_opp_registers opp_regs[] = { 255 opp_regs(0), 256 opp_regs(1), 257 opp_regs(2), 258 opp_regs(3), 259 opp_regs(4), 260 opp_regs(5) 261 }; 262 263 static const struct dce_opp_shift opp_shift = { 264 OPP_COMMON_MASK_SH_LIST_DCE_100(__SHIFT) 265 }; 266 267 static const struct dce_opp_mask opp_mask = { 268 OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK) 269 }; 270 #define aux_engine_regs(id)\ 271 [id] = {\ 272 AUX_COMMON_REG_LIST(id), \ 273 .AUX_RESET_MASK = 0 \ 274 } 275 276 static const struct dce110_aux_registers aux_engine_regs[] = { 277 aux_engine_regs(0), 278 aux_engine_regs(1), 279 aux_engine_regs(2), 280 aux_engine_regs(3), 281 aux_engine_regs(4), 282 aux_engine_regs(5) 283 }; 284 285 #define audio_regs(id)\ 286 [id] = {\ 287 AUD_COMMON_REG_LIST(id)\ 288 } 289 290 static const struct dce_audio_registers audio_regs[] = { 291 audio_regs(0), 292 audio_regs(1), 293 audio_regs(2), 294 audio_regs(3), 295 audio_regs(4), 296 audio_regs(5), 297 audio_regs(6), 298 }; 299 300 static const struct dce_audio_shift audio_shift = { 301 AUD_COMMON_MASK_SH_LIST(__SHIFT) 302 }; 303 304 static const struct dce_aduio_mask audio_mask = { 305 AUD_COMMON_MASK_SH_LIST(_MASK) 306 }; 307 308 #define clk_src_regs(id)\ 309 [id] = {\ 310 CS_COMMON_REG_LIST_DCE_100_110(id),\ 311 } 312 313 static const struct dce110_clk_src_regs clk_src_regs[] = { 314 clk_src_regs(0), 315 clk_src_regs(1), 316 clk_src_regs(2) 317 }; 318 319 static const struct dce110_clk_src_shift cs_shift = { 320 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 321 }; 322 323 static const struct dce110_clk_src_mask cs_mask = { 324 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 325 }; 326 327 static const struct dce_dmcu_registers dmcu_regs = { 328 DMCU_DCE110_COMMON_REG_LIST() 329 }; 330 331 static const struct dce_dmcu_shift dmcu_shift = { 332 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 333 }; 334 335 static const struct dce_dmcu_mask dmcu_mask = { 336 DMCU_MASK_SH_LIST_DCE110(_MASK) 337 }; 338 339 static const struct dce_abm_registers abm_regs = { 340 ABM_DCE110_COMMON_REG_LIST() 341 }; 342 343 static const struct dce_abm_shift abm_shift = { 344 ABM_MASK_SH_LIST_DCE110(__SHIFT) 345 }; 346 347 static const struct dce_abm_mask abm_mask = { 348 ABM_MASK_SH_LIST_DCE110(_MASK) 349 }; 350 351 #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03 352 353 static const struct bios_registers bios_regs = { 354 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 355 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 356 }; 357 358 static const struct resource_caps res_cap = { 359 .num_timing_generator = 6, 360 .num_audio = 6, 361 .num_stream_encoder = 6, 362 .num_pll = 3, 363 .num_ddc = 6, 364 }; 365 366 static const struct dc_plane_cap plane_cap = { 367 .type = DC_PLANE_TYPE_DCE_RGB, 368 369 .pixel_format_support = { 370 .argb8888 = true, 371 .nv12 = false, 372 .fp16 = false 373 }, 374 375 .max_upscale_factor = { 376 .argb8888 = 16000, 377 .nv12 = 1, 378 .fp16 = 1 379 }, 380 381 .max_downscale_factor = { 382 .argb8888 = 250, 383 .nv12 = 1, 384 .fp16 = 1 385 } 386 }; 387 388 #define CTX ctx 389 #define REG(reg) mm ## reg 390 391 #ifndef mmCC_DC_HDMI_STRAPS 392 #define mmCC_DC_HDMI_STRAPS 0x1918 393 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 394 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 395 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 396 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 397 #endif 398 399 static void read_dce_straps( 400 struct dc_context *ctx, 401 struct resource_straps *straps) 402 { 403 REG_GET_2(CC_DC_HDMI_STRAPS, 404 HDMI_DISABLE, &straps->hdmi_disable, 405 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 406 407 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 408 } 409 410 static struct audio *create_audio( 411 struct dc_context *ctx, unsigned int inst) 412 { 413 return dce_audio_create(ctx, inst, 414 &audio_regs[inst], &audio_shift, &audio_mask); 415 } 416 417 static struct timing_generator *dce100_timing_generator_create( 418 struct dc_context *ctx, 419 uint32_t instance, 420 const struct dce110_timing_generator_offsets *offsets) 421 { 422 struct dce110_timing_generator *tg110 = 423 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 424 425 if (!tg110) 426 return NULL; 427 428 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 429 return &tg110->base; 430 } 431 432 static struct stream_encoder *dce100_stream_encoder_create( 433 enum engine_id eng_id, 434 struct dc_context *ctx) 435 { 436 struct dce110_stream_encoder *enc110 = 437 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 438 439 if (!enc110) 440 return NULL; 441 442 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 443 &stream_enc_regs[eng_id], &se_shift, &se_mask); 444 return &enc110->base; 445 } 446 447 #define SRII(reg_name, block, id)\ 448 .reg_name[id] = mm ## block ## id ## _ ## reg_name 449 450 static const struct dce_hwseq_registers hwseq_reg = { 451 HWSEQ_DCE10_REG_LIST() 452 }; 453 454 static const struct dce_hwseq_shift hwseq_shift = { 455 HWSEQ_DCE10_MASK_SH_LIST(__SHIFT) 456 }; 457 458 static const struct dce_hwseq_mask hwseq_mask = { 459 HWSEQ_DCE10_MASK_SH_LIST(_MASK) 460 }; 461 462 static struct dce_hwseq *dce100_hwseq_create( 463 struct dc_context *ctx) 464 { 465 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 466 467 if (hws) { 468 hws->ctx = ctx; 469 hws->regs = &hwseq_reg; 470 hws->shifts = &hwseq_shift; 471 hws->masks = &hwseq_mask; 472 } 473 return hws; 474 } 475 476 static const struct resource_create_funcs res_create_funcs = { 477 .read_dce_straps = read_dce_straps, 478 .create_audio = create_audio, 479 .create_stream_encoder = dce100_stream_encoder_create, 480 .create_hwseq = dce100_hwseq_create, 481 }; 482 483 #define mi_inst_regs(id) { \ 484 MI_DCE8_REG_LIST(id), \ 485 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 486 } 487 static const struct dce_mem_input_registers mi_regs[] = { 488 mi_inst_regs(0), 489 mi_inst_regs(1), 490 mi_inst_regs(2), 491 mi_inst_regs(3), 492 mi_inst_regs(4), 493 mi_inst_regs(5), 494 }; 495 496 static const struct dce_mem_input_shift mi_shifts = { 497 MI_DCE8_MASK_SH_LIST(__SHIFT), 498 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 499 }; 500 501 static const struct dce_mem_input_mask mi_masks = { 502 MI_DCE8_MASK_SH_LIST(_MASK), 503 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 504 }; 505 506 static struct mem_input *dce100_mem_input_create( 507 struct dc_context *ctx, 508 uint32_t inst) 509 { 510 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 511 GFP_KERNEL); 512 513 if (!dce_mi) { 514 BREAK_TO_DEBUGGER(); 515 return NULL; 516 } 517 518 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 519 dce_mi->wa.single_head_rdreq_dmif_limit = 2; 520 return &dce_mi->base; 521 } 522 523 static void dce100_transform_destroy(struct transform **xfm) 524 { 525 kfree(TO_DCE_TRANSFORM(*xfm)); 526 *xfm = NULL; 527 } 528 529 static struct transform *dce100_transform_create( 530 struct dc_context *ctx, 531 uint32_t inst) 532 { 533 struct dce_transform *transform = 534 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 535 536 if (!transform) 537 return NULL; 538 539 dce_transform_construct(transform, ctx, inst, 540 &xfm_regs[inst], &xfm_shift, &xfm_mask); 541 return &transform->base; 542 } 543 544 static struct input_pixel_processor *dce100_ipp_create( 545 struct dc_context *ctx, uint32_t inst) 546 { 547 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 548 549 if (!ipp) { 550 BREAK_TO_DEBUGGER(); 551 return NULL; 552 } 553 554 dce_ipp_construct(ipp, ctx, inst, 555 &ipp_regs[inst], &ipp_shift, &ipp_mask); 556 return &ipp->base; 557 } 558 559 static const struct encoder_feature_support link_enc_feature = { 560 .max_hdmi_deep_color = COLOR_DEPTH_121212, 561 .max_hdmi_pixel_clock = 300000, 562 .flags.bits.IS_HBR2_CAPABLE = true, 563 .flags.bits.IS_TPS3_CAPABLE = true 564 }; 565 566 struct link_encoder *dce100_link_encoder_create( 567 const struct encoder_init_data *enc_init_data) 568 { 569 struct dce110_link_encoder *enc110 = 570 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 571 572 if (!enc110) 573 return NULL; 574 575 dce110_link_encoder_construct(enc110, 576 enc_init_data, 577 &link_enc_feature, 578 &link_enc_regs[enc_init_data->transmitter], 579 &link_enc_aux_regs[enc_init_data->channel - 1], 580 &link_enc_hpd_regs[enc_init_data->hpd_source]); 581 return &enc110->base; 582 } 583 584 struct output_pixel_processor *dce100_opp_create( 585 struct dc_context *ctx, 586 uint32_t inst) 587 { 588 struct dce110_opp *opp = 589 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 590 591 if (!opp) 592 return NULL; 593 594 dce110_opp_construct(opp, 595 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 596 return &opp->base; 597 } 598 599 struct dce_aux *dce100_aux_engine_create( 600 struct dc_context *ctx, 601 uint32_t inst) 602 { 603 struct aux_engine_dce110 *aux_engine = 604 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 605 606 if (!aux_engine) 607 return NULL; 608 609 dce110_aux_engine_construct(aux_engine, ctx, inst, 610 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 611 &aux_engine_regs[inst]); 612 613 return &aux_engine->base; 614 } 615 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 616 617 static const struct dce_i2c_registers i2c_hw_regs[] = { 618 i2c_inst_regs(1), 619 i2c_inst_regs(2), 620 i2c_inst_regs(3), 621 i2c_inst_regs(4), 622 i2c_inst_regs(5), 623 i2c_inst_regs(6), 624 }; 625 626 static const struct dce_i2c_shift i2c_shifts = { 627 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 628 }; 629 630 static const struct dce_i2c_mask i2c_masks = { 631 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 632 }; 633 634 struct dce_i2c_hw *dce100_i2c_hw_create( 635 struct dc_context *ctx, 636 uint32_t inst) 637 { 638 struct dce_i2c_hw *dce_i2c_hw = 639 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 640 641 if (!dce_i2c_hw) 642 return NULL; 643 644 dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst, 645 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 646 647 return dce_i2c_hw; 648 } 649 struct clock_source *dce100_clock_source_create( 650 struct dc_context *ctx, 651 struct dc_bios *bios, 652 enum clock_source_id id, 653 const struct dce110_clk_src_regs *regs, 654 bool dp_clk_src) 655 { 656 struct dce110_clk_src *clk_src = 657 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 658 659 if (!clk_src) 660 return NULL; 661 662 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 663 regs, &cs_shift, &cs_mask)) { 664 clk_src->base.dp_clk_src = dp_clk_src; 665 return &clk_src->base; 666 } 667 668 BREAK_TO_DEBUGGER(); 669 return NULL; 670 } 671 672 void dce100_clock_source_destroy(struct clock_source **clk_src) 673 { 674 kfree(TO_DCE110_CLK_SRC(*clk_src)); 675 *clk_src = NULL; 676 } 677 678 static void destruct(struct dce110_resource_pool *pool) 679 { 680 unsigned int i; 681 682 for (i = 0; i < pool->base.pipe_count; i++) { 683 if (pool->base.opps[i] != NULL) 684 dce110_opp_destroy(&pool->base.opps[i]); 685 686 if (pool->base.transforms[i] != NULL) 687 dce100_transform_destroy(&pool->base.transforms[i]); 688 689 if (pool->base.ipps[i] != NULL) 690 dce_ipp_destroy(&pool->base.ipps[i]); 691 692 if (pool->base.mis[i] != NULL) { 693 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 694 pool->base.mis[i] = NULL; 695 } 696 697 if (pool->base.timing_generators[i] != NULL) { 698 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 699 pool->base.timing_generators[i] = NULL; 700 } 701 } 702 703 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 704 if (pool->base.engines[i] != NULL) 705 dce110_engine_destroy(&pool->base.engines[i]); 706 if (pool->base.hw_i2cs[i] != NULL) { 707 kfree(pool->base.hw_i2cs[i]); 708 pool->base.hw_i2cs[i] = NULL; 709 } 710 if (pool->base.sw_i2cs[i] != NULL) { 711 kfree(pool->base.sw_i2cs[i]); 712 pool->base.sw_i2cs[i] = NULL; 713 } 714 } 715 716 for (i = 0; i < pool->base.stream_enc_count; i++) { 717 if (pool->base.stream_enc[i] != NULL) 718 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 719 } 720 721 for (i = 0; i < pool->base.clk_src_count; i++) { 722 if (pool->base.clock_sources[i] != NULL) 723 dce100_clock_source_destroy(&pool->base.clock_sources[i]); 724 } 725 726 if (pool->base.dp_clock_source != NULL) 727 dce100_clock_source_destroy(&pool->base.dp_clock_source); 728 729 for (i = 0; i < pool->base.audio_count; i++) { 730 if (pool->base.audios[i] != NULL) 731 dce_aud_destroy(&pool->base.audios[i]); 732 } 733 734 if (pool->base.abm != NULL) 735 dce_abm_destroy(&pool->base.abm); 736 737 if (pool->base.dmcu != NULL) 738 dce_dmcu_destroy(&pool->base.dmcu); 739 740 if (pool->base.irqs != NULL) 741 dal_irq_service_destroy(&pool->base.irqs); 742 } 743 744 static enum dc_status build_mapped_resource( 745 const struct dc *dc, 746 struct dc_state *context, 747 struct dc_stream_state *stream) 748 { 749 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 750 751 if (!pipe_ctx) 752 return DC_ERROR_UNEXPECTED; 753 754 dce110_resource_build_pipe_hw_param(pipe_ctx); 755 756 resource_build_info_frame(pipe_ctx); 757 758 return DC_OK; 759 } 760 761 bool dce100_validate_bandwidth( 762 struct dc *dc, 763 struct dc_state *context, 764 bool fast_validate) 765 { 766 int i; 767 bool at_least_one_pipe = false; 768 769 for (i = 0; i < dc->res_pool->pipe_count; i++) { 770 if (context->res_ctx.pipe_ctx[i].stream) 771 at_least_one_pipe = true; 772 } 773 774 if (at_least_one_pipe) { 775 /* TODO implement when needed but for now hardcode max value*/ 776 context->bw_ctx.bw.dce.dispclk_khz = 681000; 777 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; 778 } else { 779 context->bw_ctx.bw.dce.dispclk_khz = 0; 780 context->bw_ctx.bw.dce.yclk_khz = 0; 781 } 782 783 return true; 784 } 785 786 static bool dce100_validate_surface_sets( 787 struct dc_state *context) 788 { 789 int i; 790 791 for (i = 0; i < context->stream_count; i++) { 792 if (context->stream_status[i].plane_count == 0) 793 continue; 794 795 if (context->stream_status[i].plane_count > 1) 796 return false; 797 798 if (context->stream_status[i].plane_states[0]->format 799 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 800 return false; 801 } 802 803 return true; 804 } 805 806 enum dc_status dce100_validate_global( 807 struct dc *dc, 808 struct dc_state *context) 809 { 810 if (!dce100_validate_surface_sets(context)) 811 return DC_FAIL_SURFACE_VALIDATE; 812 813 return DC_OK; 814 } 815 816 enum dc_status dce100_add_stream_to_ctx( 817 struct dc *dc, 818 struct dc_state *new_ctx, 819 struct dc_stream_state *dc_stream) 820 { 821 enum dc_status result = DC_ERROR_UNEXPECTED; 822 823 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 824 825 if (result == DC_OK) 826 result = resource_map_clock_resources(dc, new_ctx, dc_stream); 827 828 if (result == DC_OK) 829 result = build_mapped_resource(dc, new_ctx, dc_stream); 830 831 return result; 832 } 833 834 static void dce100_destroy_resource_pool(struct resource_pool **pool) 835 { 836 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 837 838 destruct(dce110_pool); 839 kfree(dce110_pool); 840 *pool = NULL; 841 } 842 843 enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) 844 { 845 846 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 847 return DC_OK; 848 849 return DC_FAIL_SURFACE_VALIDATE; 850 } 851 852 struct stream_encoder *dce100_find_first_free_match_stream_enc_for_link( 853 struct resource_context *res_ctx, 854 const struct resource_pool *pool, 855 struct dc_stream_state *stream) 856 { 857 int i; 858 int j = -1; 859 struct dc_link *link = stream->link; 860 861 for (i = 0; i < pool->stream_enc_count; i++) { 862 if (!res_ctx->is_stream_enc_acquired[i] && 863 pool->stream_enc[i]) { 864 /* Store first available for MST second display 865 * in daisy chain use case 866 */ 867 j = i; 868 if (pool->stream_enc[i]->id == 869 link->link_enc->preferred_engine) 870 return pool->stream_enc[i]; 871 } 872 } 873 874 /* 875 * below can happen in cases when stream encoder is acquired: 876 * 1) for second MST display in chain, so preferred engine already 877 * acquired; 878 * 2) for another link, which preferred engine already acquired by any 879 * MST configuration. 880 * 881 * If signal is of DP type and preferred engine not found, return last available 882 * 883 * TODO - This is just a patch up and a generic solution is 884 * required for non DP connectors. 885 */ 886 887 if (j >= 0 && link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) 888 return pool->stream_enc[j]; 889 890 return NULL; 891 } 892 893 static const struct resource_funcs dce100_res_pool_funcs = { 894 .destroy = dce100_destroy_resource_pool, 895 .link_enc_create = dce100_link_encoder_create, 896 .validate_bandwidth = dce100_validate_bandwidth, 897 .validate_plane = dce100_validate_plane, 898 .add_stream_to_ctx = dce100_add_stream_to_ctx, 899 .validate_global = dce100_validate_global, 900 .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link 901 }; 902 903 static bool construct( 904 uint8_t num_virtual_links, 905 struct dc *dc, 906 struct dce110_resource_pool *pool) 907 { 908 unsigned int i; 909 struct dc_context *ctx = dc->ctx; 910 struct dc_firmware_info info; 911 struct dc_bios *bp; 912 913 ctx->dc_bios->regs = &bios_regs; 914 915 pool->base.res_cap = &res_cap; 916 pool->base.funcs = &dce100_res_pool_funcs; 917 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 918 919 bp = ctx->dc_bios; 920 921 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 922 info.external_clock_source_frequency_for_dp != 0) { 923 pool->base.dp_clock_source = 924 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 925 926 pool->base.clock_sources[0] = 927 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 928 pool->base.clock_sources[1] = 929 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 930 pool->base.clock_sources[2] = 931 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 932 pool->base.clk_src_count = 3; 933 934 } else { 935 pool->base.dp_clock_source = 936 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 937 938 pool->base.clock_sources[0] = 939 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 940 pool->base.clock_sources[1] = 941 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 942 pool->base.clk_src_count = 2; 943 } 944 945 if (pool->base.dp_clock_source == NULL) { 946 dm_error("DC: failed to create dp clock source!\n"); 947 BREAK_TO_DEBUGGER(); 948 goto res_create_fail; 949 } 950 951 for (i = 0; i < pool->base.clk_src_count; i++) { 952 if (pool->base.clock_sources[i] == NULL) { 953 dm_error("DC: failed to create clock sources!\n"); 954 BREAK_TO_DEBUGGER(); 955 goto res_create_fail; 956 } 957 } 958 959 pool->base.dmcu = dce_dmcu_create(ctx, 960 &dmcu_regs, 961 &dmcu_shift, 962 &dmcu_mask); 963 if (pool->base.dmcu == NULL) { 964 dm_error("DC: failed to create dmcu!\n"); 965 BREAK_TO_DEBUGGER(); 966 goto res_create_fail; 967 } 968 969 pool->base.abm = dce_abm_create(ctx, 970 &abm_regs, 971 &abm_shift, 972 &abm_mask); 973 if (pool->base.abm == NULL) { 974 dm_error("DC: failed to create abm!\n"); 975 BREAK_TO_DEBUGGER(); 976 goto res_create_fail; 977 } 978 979 { 980 struct irq_service_init_data init_data; 981 init_data.ctx = dc->ctx; 982 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 983 if (!pool->base.irqs) 984 goto res_create_fail; 985 } 986 987 /************************************************* 988 * Resource + asic cap harcoding * 989 *************************************************/ 990 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 991 pool->base.pipe_count = res_cap.num_timing_generator; 992 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 993 dc->caps.max_downscale_ratio = 200; 994 dc->caps.i2c_speed_in_khz = 40; 995 dc->caps.max_cursor_size = 128; 996 dc->caps.dual_link_dvi = true; 997 dc->caps.disable_dp_clk_share = true; 998 for (i = 0; i < pool->base.pipe_count; i++) { 999 pool->base.timing_generators[i] = 1000 dce100_timing_generator_create( 1001 ctx, 1002 i, 1003 &dce100_tg_offsets[i]); 1004 if (pool->base.timing_generators[i] == NULL) { 1005 BREAK_TO_DEBUGGER(); 1006 dm_error("DC: failed to create tg!\n"); 1007 goto res_create_fail; 1008 } 1009 1010 pool->base.mis[i] = dce100_mem_input_create(ctx, i); 1011 if (pool->base.mis[i] == NULL) { 1012 BREAK_TO_DEBUGGER(); 1013 dm_error( 1014 "DC: failed to create memory input!\n"); 1015 goto res_create_fail; 1016 } 1017 1018 pool->base.ipps[i] = dce100_ipp_create(ctx, i); 1019 if (pool->base.ipps[i] == NULL) { 1020 BREAK_TO_DEBUGGER(); 1021 dm_error( 1022 "DC: failed to create input pixel processor!\n"); 1023 goto res_create_fail; 1024 } 1025 1026 pool->base.transforms[i] = dce100_transform_create(ctx, i); 1027 if (pool->base.transforms[i] == NULL) { 1028 BREAK_TO_DEBUGGER(); 1029 dm_error( 1030 "DC: failed to create transform!\n"); 1031 goto res_create_fail; 1032 } 1033 1034 pool->base.opps[i] = dce100_opp_create(ctx, i); 1035 if (pool->base.opps[i] == NULL) { 1036 BREAK_TO_DEBUGGER(); 1037 dm_error( 1038 "DC: failed to create output pixel processor!\n"); 1039 goto res_create_fail; 1040 } 1041 } 1042 1043 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1044 pool->base.engines[i] = dce100_aux_engine_create(ctx, i); 1045 if (pool->base.engines[i] == NULL) { 1046 BREAK_TO_DEBUGGER(); 1047 dm_error( 1048 "DC:failed to create aux engine!!\n"); 1049 goto res_create_fail; 1050 } 1051 pool->base.hw_i2cs[i] = dce100_i2c_hw_create(ctx, i); 1052 if (pool->base.hw_i2cs[i] == NULL) { 1053 BREAK_TO_DEBUGGER(); 1054 dm_error( 1055 "DC:failed to create i2c engine!!\n"); 1056 goto res_create_fail; 1057 } 1058 pool->base.sw_i2cs[i] = NULL; 1059 } 1060 1061 dc->caps.max_planes = pool->base.pipe_count; 1062 1063 for (i = 0; i < dc->caps.max_planes; ++i) 1064 dc->caps.planes[i] = plane_cap; 1065 1066 if (!resource_construct(num_virtual_links, dc, &pool->base, 1067 &res_create_funcs)) 1068 goto res_create_fail; 1069 1070 /* Create hardware sequencer */ 1071 dce100_hw_sequencer_construct(dc); 1072 return true; 1073 1074 res_create_fail: 1075 destruct(pool); 1076 1077 return false; 1078 } 1079 1080 struct resource_pool *dce100_create_resource_pool( 1081 uint8_t num_virtual_links, 1082 struct dc *dc) 1083 { 1084 struct dce110_resource_pool *pool = 1085 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1086 1087 if (!pool) 1088 return NULL; 1089 1090 if (construct(num_virtual_links, dc, pool)) 1091 return &pool->base; 1092 1093 BREAK_TO_DEBUGGER(); 1094 return NULL; 1095 } 1096 1097