1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include "dm_services.h" 26 27 #include "link_encoder.h" 28 #include "stream_encoder.h" 29 30 #include "resource.h" 31 #include "include/irq_service_interface.h" 32 #include "../virtual/virtual_stream_encoder.h" 33 #include "dce110/dce110_resource.h" 34 #include "dce110/dce110_timing_generator.h" 35 #include "irq/dce110/irq_service_dce110.h" 36 #include "dce/dce_link_encoder.h" 37 #include "dce/dce_stream_encoder.h" 38 39 #include "dce/dce_mem_input.h" 40 #include "dce/dce_ipp.h" 41 #include "dce/dce_transform.h" 42 #include "dce/dce_opp.h" 43 #include "dce/dce_clocks.h" 44 #include "dce/dce_clock_source.h" 45 #include "dce/dce_audio.h" 46 #include "dce/dce_hwseq.h" 47 #include "dce100/dce100_hw_sequencer.h" 48 49 #include "reg_helper.h" 50 51 #include "dce/dce_10_0_d.h" 52 #include "dce/dce_10_0_sh_mask.h" 53 54 #include "dce/dce_dmcu.h" 55 #include "dce/dce_aux.h" 56 #include "dce/dce_abm.h" 57 #include "dce/dce_i2c.h" 58 59 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 60 #include "gmc/gmc_8_2_d.h" 61 #include "gmc/gmc_8_2_sh_mask.h" 62 #endif 63 64 #ifndef mmDP_DPHY_INTERNAL_CTRL 65 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 66 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 67 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 68 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 69 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 70 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 71 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 72 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 73 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 74 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 75 #endif 76 77 #ifndef mmBIOS_SCRATCH_2 78 #define mmBIOS_SCRATCH_2 0x05CB 79 #define mmBIOS_SCRATCH_6 0x05CF 80 #endif 81 82 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 83 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 84 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 85 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 86 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 87 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 88 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 89 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 90 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 91 #endif 92 93 #ifndef mmDP_DPHY_FAST_TRAINING 94 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 95 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 96 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 97 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 98 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 99 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 100 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 101 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 102 #endif 103 104 static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = { 105 { 106 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 107 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 108 }, 109 { 110 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 111 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 112 }, 113 { 114 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 115 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 116 }, 117 { 118 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 119 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 120 }, 121 { 122 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 123 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 124 }, 125 { 126 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 127 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 128 } 129 }; 130 131 /* set register offset */ 132 #define SR(reg_name)\ 133 .reg_name = mm ## reg_name 134 135 /* set register offset with instance */ 136 #define SRI(reg_name, block, id)\ 137 .reg_name = mm ## block ## id ## _ ## reg_name 138 139 140 static const struct dccg_registers disp_clk_regs = { 141 CLK_COMMON_REG_LIST_DCE_BASE() 142 }; 143 144 static const struct dccg_shift disp_clk_shift = { 145 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 146 }; 147 148 static const struct dccg_mask disp_clk_mask = { 149 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 150 }; 151 152 #define ipp_regs(id)\ 153 [id] = {\ 154 IPP_DCE100_REG_LIST_DCE_BASE(id)\ 155 } 156 157 static const struct dce_ipp_registers ipp_regs[] = { 158 ipp_regs(0), 159 ipp_regs(1), 160 ipp_regs(2), 161 ipp_regs(3), 162 ipp_regs(4), 163 ipp_regs(5) 164 }; 165 166 static const struct dce_ipp_shift ipp_shift = { 167 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 168 }; 169 170 static const struct dce_ipp_mask ipp_mask = { 171 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 172 }; 173 174 #define transform_regs(id)\ 175 [id] = {\ 176 XFM_COMMON_REG_LIST_DCE100(id)\ 177 } 178 179 static const struct dce_transform_registers xfm_regs[] = { 180 transform_regs(0), 181 transform_regs(1), 182 transform_regs(2), 183 transform_regs(3), 184 transform_regs(4), 185 transform_regs(5) 186 }; 187 188 static const struct dce_transform_shift xfm_shift = { 189 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 190 }; 191 192 static const struct dce_transform_mask xfm_mask = { 193 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 194 }; 195 196 #define aux_regs(id)\ 197 [id] = {\ 198 AUX_REG_LIST(id)\ 199 } 200 201 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 202 aux_regs(0), 203 aux_regs(1), 204 aux_regs(2), 205 aux_regs(3), 206 aux_regs(4), 207 aux_regs(5) 208 }; 209 210 #define hpd_regs(id)\ 211 [id] = {\ 212 HPD_REG_LIST(id)\ 213 } 214 215 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 216 hpd_regs(0), 217 hpd_regs(1), 218 hpd_regs(2), 219 hpd_regs(3), 220 hpd_regs(4), 221 hpd_regs(5) 222 }; 223 224 #define link_regs(id)\ 225 [id] = {\ 226 LE_DCE100_REG_LIST(id)\ 227 } 228 229 static const struct dce110_link_enc_registers link_enc_regs[] = { 230 link_regs(0), 231 link_regs(1), 232 link_regs(2), 233 link_regs(3), 234 link_regs(4), 235 link_regs(5), 236 link_regs(6), 237 }; 238 239 #define stream_enc_regs(id)\ 240 [id] = {\ 241 SE_COMMON_REG_LIST_DCE_BASE(id),\ 242 .AFMT_CNTL = 0,\ 243 } 244 245 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 246 stream_enc_regs(0), 247 stream_enc_regs(1), 248 stream_enc_regs(2), 249 stream_enc_regs(3), 250 stream_enc_regs(4), 251 stream_enc_regs(5), 252 stream_enc_regs(6) 253 }; 254 255 static const struct dce_stream_encoder_shift se_shift = { 256 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) 257 }; 258 259 static const struct dce_stream_encoder_mask se_mask = { 260 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) 261 }; 262 263 #define opp_regs(id)\ 264 [id] = {\ 265 OPP_DCE_100_REG_LIST(id),\ 266 } 267 268 static const struct dce_opp_registers opp_regs[] = { 269 opp_regs(0), 270 opp_regs(1), 271 opp_regs(2), 272 opp_regs(3), 273 opp_regs(4), 274 opp_regs(5) 275 }; 276 277 static const struct dce_opp_shift opp_shift = { 278 OPP_COMMON_MASK_SH_LIST_DCE_100(__SHIFT) 279 }; 280 281 static const struct dce_opp_mask opp_mask = { 282 OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK) 283 }; 284 #define aux_engine_regs(id)\ 285 [id] = {\ 286 AUX_COMMON_REG_LIST(id), \ 287 .AUX_RESET_MASK = 0 \ 288 } 289 290 static const struct dce110_aux_registers aux_engine_regs[] = { 291 aux_engine_regs(0), 292 aux_engine_regs(1), 293 aux_engine_regs(2), 294 aux_engine_regs(3), 295 aux_engine_regs(4), 296 aux_engine_regs(5) 297 }; 298 299 #define audio_regs(id)\ 300 [id] = {\ 301 AUD_COMMON_REG_LIST(id)\ 302 } 303 304 static const struct dce_audio_registers audio_regs[] = { 305 audio_regs(0), 306 audio_regs(1), 307 audio_regs(2), 308 audio_regs(3), 309 audio_regs(4), 310 audio_regs(5), 311 audio_regs(6), 312 }; 313 314 static const struct dce_audio_shift audio_shift = { 315 AUD_COMMON_MASK_SH_LIST(__SHIFT) 316 }; 317 318 static const struct dce_aduio_mask audio_mask = { 319 AUD_COMMON_MASK_SH_LIST(_MASK) 320 }; 321 322 #define clk_src_regs(id)\ 323 [id] = {\ 324 CS_COMMON_REG_LIST_DCE_100_110(id),\ 325 } 326 327 static const struct dce110_clk_src_regs clk_src_regs[] = { 328 clk_src_regs(0), 329 clk_src_regs(1), 330 clk_src_regs(2) 331 }; 332 333 static const struct dce110_clk_src_shift cs_shift = { 334 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 335 }; 336 337 static const struct dce110_clk_src_mask cs_mask = { 338 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 339 }; 340 341 static const struct dce_dmcu_registers dmcu_regs = { 342 DMCU_DCE110_COMMON_REG_LIST() 343 }; 344 345 static const struct dce_dmcu_shift dmcu_shift = { 346 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 347 }; 348 349 static const struct dce_dmcu_mask dmcu_mask = { 350 DMCU_MASK_SH_LIST_DCE110(_MASK) 351 }; 352 353 static const struct dce_abm_registers abm_regs = { 354 ABM_DCE110_COMMON_REG_LIST() 355 }; 356 357 static const struct dce_abm_shift abm_shift = { 358 ABM_MASK_SH_LIST_DCE110(__SHIFT) 359 }; 360 361 static const struct dce_abm_mask abm_mask = { 362 ABM_MASK_SH_LIST_DCE110(_MASK) 363 }; 364 365 #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03 366 367 static const struct bios_registers bios_regs = { 368 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 369 }; 370 371 static const struct resource_caps res_cap = { 372 .num_timing_generator = 6, 373 .num_audio = 6, 374 .num_stream_encoder = 6, 375 .num_pll = 3, 376 .num_ddc = 6, 377 }; 378 379 #define CTX ctx 380 #define REG(reg) mm ## reg 381 382 #ifndef mmCC_DC_HDMI_STRAPS 383 #define mmCC_DC_HDMI_STRAPS 0x1918 384 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 385 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 386 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 387 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 388 #endif 389 390 static void read_dce_straps( 391 struct dc_context *ctx, 392 struct resource_straps *straps) 393 { 394 REG_GET_2(CC_DC_HDMI_STRAPS, 395 HDMI_DISABLE, &straps->hdmi_disable, 396 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 397 398 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 399 } 400 401 static struct audio *create_audio( 402 struct dc_context *ctx, unsigned int inst) 403 { 404 return dce_audio_create(ctx, inst, 405 &audio_regs[inst], &audio_shift, &audio_mask); 406 } 407 408 static struct timing_generator *dce100_timing_generator_create( 409 struct dc_context *ctx, 410 uint32_t instance, 411 const struct dce110_timing_generator_offsets *offsets) 412 { 413 struct dce110_timing_generator *tg110 = 414 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 415 416 if (!tg110) 417 return NULL; 418 419 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 420 return &tg110->base; 421 } 422 423 static struct stream_encoder *dce100_stream_encoder_create( 424 enum engine_id eng_id, 425 struct dc_context *ctx) 426 { 427 struct dce110_stream_encoder *enc110 = 428 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 429 430 if (!enc110) 431 return NULL; 432 433 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 434 &stream_enc_regs[eng_id], &se_shift, &se_mask); 435 return &enc110->base; 436 } 437 438 #define SRII(reg_name, block, id)\ 439 .reg_name[id] = mm ## block ## id ## _ ## reg_name 440 441 static const struct dce_hwseq_registers hwseq_reg = { 442 HWSEQ_DCE10_REG_LIST() 443 }; 444 445 static const struct dce_hwseq_shift hwseq_shift = { 446 HWSEQ_DCE10_MASK_SH_LIST(__SHIFT) 447 }; 448 449 static const struct dce_hwseq_mask hwseq_mask = { 450 HWSEQ_DCE10_MASK_SH_LIST(_MASK) 451 }; 452 453 static struct dce_hwseq *dce100_hwseq_create( 454 struct dc_context *ctx) 455 { 456 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 457 458 if (hws) { 459 hws->ctx = ctx; 460 hws->regs = &hwseq_reg; 461 hws->shifts = &hwseq_shift; 462 hws->masks = &hwseq_mask; 463 } 464 return hws; 465 } 466 467 static const struct resource_create_funcs res_create_funcs = { 468 .read_dce_straps = read_dce_straps, 469 .create_audio = create_audio, 470 .create_stream_encoder = dce100_stream_encoder_create, 471 .create_hwseq = dce100_hwseq_create, 472 }; 473 474 #define mi_inst_regs(id) { \ 475 MI_DCE8_REG_LIST(id), \ 476 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 477 } 478 static const struct dce_mem_input_registers mi_regs[] = { 479 mi_inst_regs(0), 480 mi_inst_regs(1), 481 mi_inst_regs(2), 482 mi_inst_regs(3), 483 mi_inst_regs(4), 484 mi_inst_regs(5), 485 }; 486 487 static const struct dce_mem_input_shift mi_shifts = { 488 MI_DCE8_MASK_SH_LIST(__SHIFT), 489 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 490 }; 491 492 static const struct dce_mem_input_mask mi_masks = { 493 MI_DCE8_MASK_SH_LIST(_MASK), 494 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 495 }; 496 497 static struct mem_input *dce100_mem_input_create( 498 struct dc_context *ctx, 499 uint32_t inst) 500 { 501 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 502 GFP_KERNEL); 503 504 if (!dce_mi) { 505 BREAK_TO_DEBUGGER(); 506 return NULL; 507 } 508 509 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 510 dce_mi->wa.single_head_rdreq_dmif_limit = 2; 511 return &dce_mi->base; 512 } 513 514 static void dce100_transform_destroy(struct transform **xfm) 515 { 516 kfree(TO_DCE_TRANSFORM(*xfm)); 517 *xfm = NULL; 518 } 519 520 static struct transform *dce100_transform_create( 521 struct dc_context *ctx, 522 uint32_t inst) 523 { 524 struct dce_transform *transform = 525 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 526 527 if (!transform) 528 return NULL; 529 530 dce_transform_construct(transform, ctx, inst, 531 &xfm_regs[inst], &xfm_shift, &xfm_mask); 532 return &transform->base; 533 } 534 535 static struct input_pixel_processor *dce100_ipp_create( 536 struct dc_context *ctx, uint32_t inst) 537 { 538 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 539 540 if (!ipp) { 541 BREAK_TO_DEBUGGER(); 542 return NULL; 543 } 544 545 dce_ipp_construct(ipp, ctx, inst, 546 &ipp_regs[inst], &ipp_shift, &ipp_mask); 547 return &ipp->base; 548 } 549 550 static const struct encoder_feature_support link_enc_feature = { 551 .max_hdmi_deep_color = COLOR_DEPTH_121212, 552 .max_hdmi_pixel_clock = 300000, 553 .flags.bits.IS_HBR2_CAPABLE = true, 554 .flags.bits.IS_TPS3_CAPABLE = true 555 }; 556 557 struct link_encoder *dce100_link_encoder_create( 558 const struct encoder_init_data *enc_init_data) 559 { 560 struct dce110_link_encoder *enc110 = 561 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 562 563 if (!enc110) 564 return NULL; 565 566 dce110_link_encoder_construct(enc110, 567 enc_init_data, 568 &link_enc_feature, 569 &link_enc_regs[enc_init_data->transmitter], 570 &link_enc_aux_regs[enc_init_data->channel - 1], 571 &link_enc_hpd_regs[enc_init_data->hpd_source]); 572 return &enc110->base; 573 } 574 575 struct output_pixel_processor *dce100_opp_create( 576 struct dc_context *ctx, 577 uint32_t inst) 578 { 579 struct dce110_opp *opp = 580 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 581 582 if (!opp) 583 return NULL; 584 585 dce110_opp_construct(opp, 586 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 587 return &opp->base; 588 } 589 590 struct aux_engine *dce100_aux_engine_create( 591 struct dc_context *ctx, 592 uint32_t inst) 593 { 594 struct aux_engine_dce110 *aux_engine = 595 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 596 597 if (!aux_engine) 598 return NULL; 599 600 dce110_aux_engine_construct(aux_engine, ctx, inst, 601 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 602 &aux_engine_regs[inst]); 603 604 return &aux_engine->base; 605 } 606 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 607 608 static const struct dce_i2c_registers i2c_hw_regs[] = { 609 i2c_inst_regs(1), 610 i2c_inst_regs(2), 611 i2c_inst_regs(3), 612 i2c_inst_regs(4), 613 i2c_inst_regs(5), 614 i2c_inst_regs(6), 615 }; 616 617 static const struct dce_i2c_shift i2c_shifts = { 618 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 619 }; 620 621 static const struct dce_i2c_mask i2c_masks = { 622 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 623 }; 624 625 struct dce_i2c_hw *dce100_i2c_hw_create( 626 struct dc_context *ctx, 627 uint32_t inst) 628 { 629 struct dce_i2c_hw *dce_i2c_hw = 630 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 631 632 if (!dce_i2c_hw) 633 return NULL; 634 635 dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst, 636 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 637 638 return dce_i2c_hw; 639 } 640 struct clock_source *dce100_clock_source_create( 641 struct dc_context *ctx, 642 struct dc_bios *bios, 643 enum clock_source_id id, 644 const struct dce110_clk_src_regs *regs, 645 bool dp_clk_src) 646 { 647 struct dce110_clk_src *clk_src = 648 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 649 650 if (!clk_src) 651 return NULL; 652 653 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 654 regs, &cs_shift, &cs_mask)) { 655 clk_src->base.dp_clk_src = dp_clk_src; 656 return &clk_src->base; 657 } 658 659 BREAK_TO_DEBUGGER(); 660 return NULL; 661 } 662 663 void dce100_clock_source_destroy(struct clock_source **clk_src) 664 { 665 kfree(TO_DCE110_CLK_SRC(*clk_src)); 666 *clk_src = NULL; 667 } 668 669 static void destruct(struct dce110_resource_pool *pool) 670 { 671 unsigned int i; 672 673 for (i = 0; i < pool->base.pipe_count; i++) { 674 if (pool->base.opps[i] != NULL) 675 dce110_opp_destroy(&pool->base.opps[i]); 676 677 if (pool->base.transforms[i] != NULL) 678 dce100_transform_destroy(&pool->base.transforms[i]); 679 680 if (pool->base.ipps[i] != NULL) 681 dce_ipp_destroy(&pool->base.ipps[i]); 682 683 if (pool->base.mis[i] != NULL) { 684 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 685 pool->base.mis[i] = NULL; 686 } 687 688 if (pool->base.timing_generators[i] != NULL) { 689 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 690 pool->base.timing_generators[i] = NULL; 691 } 692 } 693 694 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 695 if (pool->base.engines[i] != NULL) 696 dce110_engine_destroy(&pool->base.engines[i]); 697 if (pool->base.hw_i2cs[i] != NULL) { 698 kfree(pool->base.hw_i2cs[i]); 699 pool->base.hw_i2cs[i] = NULL; 700 } 701 if (pool->base.sw_i2cs[i] != NULL) { 702 kfree(pool->base.sw_i2cs[i]); 703 pool->base.sw_i2cs[i] = NULL; 704 } 705 } 706 707 for (i = 0; i < pool->base.stream_enc_count; i++) { 708 if (pool->base.stream_enc[i] != NULL) 709 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 710 } 711 712 for (i = 0; i < pool->base.clk_src_count; i++) { 713 if (pool->base.clock_sources[i] != NULL) 714 dce100_clock_source_destroy(&pool->base.clock_sources[i]); 715 } 716 717 if (pool->base.dp_clock_source != NULL) 718 dce100_clock_source_destroy(&pool->base.dp_clock_source); 719 720 for (i = 0; i < pool->base.audio_count; i++) { 721 if (pool->base.audios[i] != NULL) 722 dce_aud_destroy(&pool->base.audios[i]); 723 } 724 725 if (pool->base.dccg != NULL) 726 dce_dccg_destroy(&pool->base.dccg); 727 728 if (pool->base.abm != NULL) 729 dce_abm_destroy(&pool->base.abm); 730 731 if (pool->base.dmcu != NULL) 732 dce_dmcu_destroy(&pool->base.dmcu); 733 734 if (pool->base.irqs != NULL) 735 dal_irq_service_destroy(&pool->base.irqs); 736 } 737 738 static enum dc_status build_mapped_resource( 739 const struct dc *dc, 740 struct dc_state *context, 741 struct dc_stream_state *stream) 742 { 743 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 744 745 if (!pipe_ctx) 746 return DC_ERROR_UNEXPECTED; 747 748 dce110_resource_build_pipe_hw_param(pipe_ctx); 749 750 resource_build_info_frame(pipe_ctx); 751 752 return DC_OK; 753 } 754 755 bool dce100_validate_bandwidth( 756 struct dc *dc, 757 struct dc_state *context) 758 { 759 int i; 760 bool at_least_one_pipe = false; 761 762 for (i = 0; i < dc->res_pool->pipe_count; i++) { 763 if (context->res_ctx.pipe_ctx[i].stream) 764 at_least_one_pipe = true; 765 } 766 767 if (at_least_one_pipe) { 768 /* TODO implement when needed but for now hardcode max value*/ 769 context->bw.dce.dispclk_khz = 681000; 770 context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER; 771 } else { 772 context->bw.dce.dispclk_khz = 0; 773 context->bw.dce.yclk_khz = 0; 774 } 775 776 return true; 777 } 778 779 static bool dce100_validate_surface_sets( 780 struct dc_state *context) 781 { 782 int i; 783 784 for (i = 0; i < context->stream_count; i++) { 785 if (context->stream_status[i].plane_count == 0) 786 continue; 787 788 if (context->stream_status[i].plane_count > 1) 789 return false; 790 791 if (context->stream_status[i].plane_states[0]->format 792 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 793 return false; 794 } 795 796 return true; 797 } 798 799 enum dc_status dce100_validate_global( 800 struct dc *dc, 801 struct dc_state *context) 802 { 803 if (!dce100_validate_surface_sets(context)) 804 return DC_FAIL_SURFACE_VALIDATE; 805 806 return DC_OK; 807 } 808 809 enum dc_status dce100_add_stream_to_ctx( 810 struct dc *dc, 811 struct dc_state *new_ctx, 812 struct dc_stream_state *dc_stream) 813 { 814 enum dc_status result = DC_ERROR_UNEXPECTED; 815 816 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 817 818 if (result == DC_OK) 819 result = resource_map_clock_resources(dc, new_ctx, dc_stream); 820 821 if (result == DC_OK) 822 result = build_mapped_resource(dc, new_ctx, dc_stream); 823 824 return result; 825 } 826 827 static void dce100_destroy_resource_pool(struct resource_pool **pool) 828 { 829 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 830 831 destruct(dce110_pool); 832 kfree(dce110_pool); 833 *pool = NULL; 834 } 835 836 enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) 837 { 838 839 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 840 return DC_OK; 841 842 return DC_FAIL_SURFACE_VALIDATE; 843 } 844 845 static const struct resource_funcs dce100_res_pool_funcs = { 846 .destroy = dce100_destroy_resource_pool, 847 .link_enc_create = dce100_link_encoder_create, 848 .validate_bandwidth = dce100_validate_bandwidth, 849 .validate_plane = dce100_validate_plane, 850 .add_stream_to_ctx = dce100_add_stream_to_ctx, 851 .validate_global = dce100_validate_global 852 }; 853 854 static bool construct( 855 uint8_t num_virtual_links, 856 struct dc *dc, 857 struct dce110_resource_pool *pool) 858 { 859 unsigned int i; 860 struct dc_context *ctx = dc->ctx; 861 struct dc_firmware_info info; 862 struct dc_bios *bp; 863 struct dm_pp_static_clock_info static_clk_info = {0}; 864 865 ctx->dc_bios->regs = &bios_regs; 866 867 pool->base.res_cap = &res_cap; 868 pool->base.funcs = &dce100_res_pool_funcs; 869 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 870 871 bp = ctx->dc_bios; 872 873 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 874 info.external_clock_source_frequency_for_dp != 0) { 875 pool->base.dp_clock_source = 876 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 877 878 pool->base.clock_sources[0] = 879 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 880 pool->base.clock_sources[1] = 881 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 882 pool->base.clock_sources[2] = 883 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 884 pool->base.clk_src_count = 3; 885 886 } else { 887 pool->base.dp_clock_source = 888 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 889 890 pool->base.clock_sources[0] = 891 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 892 pool->base.clock_sources[1] = 893 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 894 pool->base.clk_src_count = 2; 895 } 896 897 if (pool->base.dp_clock_source == NULL) { 898 dm_error("DC: failed to create dp clock source!\n"); 899 BREAK_TO_DEBUGGER(); 900 goto res_create_fail; 901 } 902 903 for (i = 0; i < pool->base.clk_src_count; i++) { 904 if (pool->base.clock_sources[i] == NULL) { 905 dm_error("DC: failed to create clock sources!\n"); 906 BREAK_TO_DEBUGGER(); 907 goto res_create_fail; 908 } 909 } 910 911 pool->base.dccg = dce_dccg_create(ctx, 912 &disp_clk_regs, 913 &disp_clk_shift, 914 &disp_clk_mask); 915 if (pool->base.dccg == NULL) { 916 dm_error("DC: failed to create display clock!\n"); 917 BREAK_TO_DEBUGGER(); 918 goto res_create_fail; 919 } 920 921 pool->base.dmcu = dce_dmcu_create(ctx, 922 &dmcu_regs, 923 &dmcu_shift, 924 &dmcu_mask); 925 if (pool->base.dmcu == NULL) { 926 dm_error("DC: failed to create dmcu!\n"); 927 BREAK_TO_DEBUGGER(); 928 goto res_create_fail; 929 } 930 931 pool->base.abm = dce_abm_create(ctx, 932 &abm_regs, 933 &abm_shift, 934 &abm_mask); 935 if (pool->base.abm == NULL) { 936 dm_error("DC: failed to create abm!\n"); 937 BREAK_TO_DEBUGGER(); 938 goto res_create_fail; 939 } 940 941 /* get static clock information for PPLIB or firmware, save 942 * max_clock_state 943 */ 944 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 945 pool->base.dccg->max_clks_state = 946 static_clk_info.max_clocks_state; 947 { 948 struct irq_service_init_data init_data; 949 init_data.ctx = dc->ctx; 950 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 951 if (!pool->base.irqs) 952 goto res_create_fail; 953 } 954 955 /************************************************* 956 * Resource + asic cap harcoding * 957 *************************************************/ 958 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 959 pool->base.pipe_count = res_cap.num_timing_generator; 960 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 961 dc->caps.max_downscale_ratio = 200; 962 dc->caps.i2c_speed_in_khz = 40; 963 dc->caps.max_cursor_size = 128; 964 dc->caps.dual_link_dvi = true; 965 dc->caps.disable_dp_clk_share = true; 966 for (i = 0; i < pool->base.pipe_count; i++) { 967 pool->base.timing_generators[i] = 968 dce100_timing_generator_create( 969 ctx, 970 i, 971 &dce100_tg_offsets[i]); 972 if (pool->base.timing_generators[i] == NULL) { 973 BREAK_TO_DEBUGGER(); 974 dm_error("DC: failed to create tg!\n"); 975 goto res_create_fail; 976 } 977 978 pool->base.mis[i] = dce100_mem_input_create(ctx, i); 979 if (pool->base.mis[i] == NULL) { 980 BREAK_TO_DEBUGGER(); 981 dm_error( 982 "DC: failed to create memory input!\n"); 983 goto res_create_fail; 984 } 985 986 pool->base.ipps[i] = dce100_ipp_create(ctx, i); 987 if (pool->base.ipps[i] == NULL) { 988 BREAK_TO_DEBUGGER(); 989 dm_error( 990 "DC: failed to create input pixel processor!\n"); 991 goto res_create_fail; 992 } 993 994 pool->base.transforms[i] = dce100_transform_create(ctx, i); 995 if (pool->base.transforms[i] == NULL) { 996 BREAK_TO_DEBUGGER(); 997 dm_error( 998 "DC: failed to create transform!\n"); 999 goto res_create_fail; 1000 } 1001 1002 pool->base.opps[i] = dce100_opp_create(ctx, i); 1003 if (pool->base.opps[i] == NULL) { 1004 BREAK_TO_DEBUGGER(); 1005 dm_error( 1006 "DC: failed to create output pixel processor!\n"); 1007 goto res_create_fail; 1008 } 1009 } 1010 1011 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1012 pool->base.engines[i] = dce100_aux_engine_create(ctx, i); 1013 if (pool->base.engines[i] == NULL) { 1014 BREAK_TO_DEBUGGER(); 1015 dm_error( 1016 "DC:failed to create aux engine!!\n"); 1017 goto res_create_fail; 1018 } 1019 pool->base.hw_i2cs[i] = dce100_i2c_hw_create(ctx, i); 1020 if (pool->base.hw_i2cs[i] == NULL) { 1021 BREAK_TO_DEBUGGER(); 1022 dm_error( 1023 "DC:failed to create i2c engine!!\n"); 1024 goto res_create_fail; 1025 } 1026 pool->base.sw_i2cs[i] = NULL; 1027 } 1028 1029 dc->caps.max_planes = pool->base.pipe_count; 1030 1031 if (!resource_construct(num_virtual_links, dc, &pool->base, 1032 &res_create_funcs)) 1033 goto res_create_fail; 1034 1035 /* Create hardware sequencer */ 1036 dce100_hw_sequencer_construct(dc); 1037 return true; 1038 1039 res_create_fail: 1040 destruct(pool); 1041 1042 return false; 1043 } 1044 1045 struct resource_pool *dce100_create_resource_pool( 1046 uint8_t num_virtual_links, 1047 struct dc *dc) 1048 { 1049 struct dce110_resource_pool *pool = 1050 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1051 1052 if (!pool) 1053 return NULL; 1054 1055 if (construct(num_virtual_links, dc, pool)) 1056 return &pool->base; 1057 1058 BREAK_TO_DEBUGGER(); 1059 return NULL; 1060 } 1061 1062