1 /*
2  * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dm_services.h"
27 
28 #include "link_encoder.h"
29 #include "stream_encoder.h"
30 
31 #include "resource.h"
32 #include "include/irq_service_interface.h"
33 #include "../virtual/virtual_stream_encoder.h"
34 #include "dce110/dce110_resource.h"
35 #include "dce110/dce110_timing_generator.h"
36 #include "irq/dce110/irq_service_dce110.h"
37 #include "dce/dce_link_encoder.h"
38 #include "dce/dce_stream_encoder.h"
39 #include "dce/dce_mem_input.h"
40 #include "dce/dce_ipp.h"
41 #include "dce/dce_transform.h"
42 #include "dce/dce_opp.h"
43 #include "dce/dce_clock_source.h"
44 #include "dce/dce_audio.h"
45 #include "dce/dce_hwseq.h"
46 #include "dce100/dce100_hw_sequencer.h"
47 #include "dce/dce_panel_cntl.h"
48 
49 #include "reg_helper.h"
50 
51 #include "dce/dce_10_0_d.h"
52 #include "dce/dce_10_0_sh_mask.h"
53 
54 #include "dce/dce_dmcu.h"
55 #include "dce/dce_aux.h"
56 #include "dce/dce_abm.h"
57 #include "dce/dce_i2c.h"
58 
59 #include "dce100_resource.h"
60 
61 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
62 #include "gmc/gmc_8_2_d.h"
63 #include "gmc/gmc_8_2_sh_mask.h"
64 #endif
65 
66 #ifndef mmDP_DPHY_INTERNAL_CTRL
67 	#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
68 	#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
69 	#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
70 	#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
71 	#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
72 	#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
73 	#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
74 	#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
75 	#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
76 	#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
77 #endif
78 
79 #ifndef mmBIOS_SCRATCH_2
80 	#define mmBIOS_SCRATCH_2 0x05CB
81 	#define mmBIOS_SCRATCH_3 0x05CC
82 	#define mmBIOS_SCRATCH_6 0x05CF
83 #endif
84 
85 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
86 	#define mmDP_DPHY_BS_SR_SWAP_CNTL                       0x4ADC
87 	#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                   0x4ADC
88 	#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                   0x4BDC
89 	#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                   0x4CDC
90 	#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                   0x4DDC
91 	#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                   0x4EDC
92 	#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL                   0x4FDC
93 	#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL                   0x54DC
94 #endif
95 
96 #ifndef mmDP_DPHY_FAST_TRAINING
97 	#define mmDP_DPHY_FAST_TRAINING                         0x4ABC
98 	#define mmDP0_DP_DPHY_FAST_TRAINING                     0x4ABC
99 	#define mmDP1_DP_DPHY_FAST_TRAINING                     0x4BBC
100 	#define mmDP2_DP_DPHY_FAST_TRAINING                     0x4CBC
101 	#define mmDP3_DP_DPHY_FAST_TRAINING                     0x4DBC
102 	#define mmDP4_DP_DPHY_FAST_TRAINING                     0x4EBC
103 	#define mmDP5_DP_DPHY_FAST_TRAINING                     0x4FBC
104 	#define mmDP6_DP_DPHY_FAST_TRAINING                     0x54BC
105 #endif
106 
107 static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = {
108 	{
109 		.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
110 		.dcp =  (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
111 	},
112 	{
113 		.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
114 		.dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
115 	},
116 	{
117 		.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
118 		.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
119 	},
120 	{
121 		.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
122 		.dcp =  (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
123 	},
124 	{
125 		.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
126 		.dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
127 	},
128 	{
129 		.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
130 		.dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
131 	}
132 };
133 
134 /* set register offset */
135 #define SR(reg_name)\
136 	.reg_name = mm ## reg_name
137 
138 /* set register offset with instance */
139 #define SRI(reg_name, block, id)\
140 	.reg_name = mm ## block ## id ## _ ## reg_name
141 
142 #define ipp_regs(id)\
143 [id] = {\
144 		IPP_DCE100_REG_LIST_DCE_BASE(id)\
145 }
146 
147 static const struct dce_ipp_registers ipp_regs[] = {
148 		ipp_regs(0),
149 		ipp_regs(1),
150 		ipp_regs(2),
151 		ipp_regs(3),
152 		ipp_regs(4),
153 		ipp_regs(5)
154 };
155 
156 static const struct dce_ipp_shift ipp_shift = {
157 		IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
158 };
159 
160 static const struct dce_ipp_mask ipp_mask = {
161 		IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
162 };
163 
164 #define transform_regs(id)\
165 [id] = {\
166 		XFM_COMMON_REG_LIST_DCE100(id)\
167 }
168 
169 static const struct dce_transform_registers xfm_regs[] = {
170 		transform_regs(0),
171 		transform_regs(1),
172 		transform_regs(2),
173 		transform_regs(3),
174 		transform_regs(4),
175 		transform_regs(5)
176 };
177 
178 static const struct dce_transform_shift xfm_shift = {
179 		XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
180 };
181 
182 static const struct dce_transform_mask xfm_mask = {
183 		XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
184 };
185 
186 #define aux_regs(id)\
187 [id] = {\
188 	AUX_REG_LIST(id)\
189 }
190 
191 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
192 		aux_regs(0),
193 		aux_regs(1),
194 		aux_regs(2),
195 		aux_regs(3),
196 		aux_regs(4),
197 		aux_regs(5)
198 };
199 
200 #define hpd_regs(id)\
201 [id] = {\
202 	HPD_REG_LIST(id)\
203 }
204 
205 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
206 		hpd_regs(0),
207 		hpd_regs(1),
208 		hpd_regs(2),
209 		hpd_regs(3),
210 		hpd_regs(4),
211 		hpd_regs(5)
212 };
213 
214 #define link_regs(id)\
215 [id] = {\
216 	LE_DCE100_REG_LIST(id)\
217 }
218 
219 static const struct dce110_link_enc_registers link_enc_regs[] = {
220 	link_regs(0),
221 	link_regs(1),
222 	link_regs(2),
223 	link_regs(3),
224 	link_regs(4),
225 	link_regs(5),
226 	link_regs(6),
227 };
228 
229 #define stream_enc_regs(id)\
230 [id] = {\
231 	SE_COMMON_REG_LIST_DCE_BASE(id),\
232 	.AFMT_CNTL = 0,\
233 }
234 
235 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
236 	stream_enc_regs(0),
237 	stream_enc_regs(1),
238 	stream_enc_regs(2),
239 	stream_enc_regs(3),
240 	stream_enc_regs(4),
241 	stream_enc_regs(5),
242 	stream_enc_regs(6)
243 };
244 
245 static const struct dce_stream_encoder_shift se_shift = {
246 		SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
247 };
248 
249 static const struct dce_stream_encoder_mask se_mask = {
250 		SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
251 };
252 
253 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
254 	{ DCE_PANEL_CNTL_REG_LIST() }
255 };
256 
257 static const struct dce_panel_cntl_shift panel_cntl_shift = {
258 	DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
259 };
260 
261 static const struct dce_panel_cntl_mask panel_cntl_mask = {
262 	DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
263 };
264 
265 #define opp_regs(id)\
266 [id] = {\
267 	OPP_DCE_100_REG_LIST(id),\
268 }
269 
270 static const struct dce_opp_registers opp_regs[] = {
271 	opp_regs(0),
272 	opp_regs(1),
273 	opp_regs(2),
274 	opp_regs(3),
275 	opp_regs(4),
276 	opp_regs(5)
277 };
278 
279 static const struct dce_opp_shift opp_shift = {
280 	OPP_COMMON_MASK_SH_LIST_DCE_100(__SHIFT)
281 };
282 
283 static const struct dce_opp_mask opp_mask = {
284 	OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK)
285 };
286 #define aux_engine_regs(id)\
287 [id] = {\
288 	AUX_COMMON_REG_LIST(id), \
289 	.AUX_RESET_MASK = 0 \
290 }
291 
292 static const struct dce110_aux_registers aux_engine_regs[] = {
293 		aux_engine_regs(0),
294 		aux_engine_regs(1),
295 		aux_engine_regs(2),
296 		aux_engine_regs(3),
297 		aux_engine_regs(4),
298 		aux_engine_regs(5)
299 };
300 
301 #define audio_regs(id)\
302 [id] = {\
303 	AUD_COMMON_REG_LIST(id)\
304 }
305 
306 static const struct dce_audio_registers audio_regs[] = {
307 	audio_regs(0),
308 	audio_regs(1),
309 	audio_regs(2),
310 	audio_regs(3),
311 	audio_regs(4),
312 	audio_regs(5),
313 	audio_regs(6),
314 };
315 
316 static const struct dce_audio_shift audio_shift = {
317 		AUD_COMMON_MASK_SH_LIST(__SHIFT)
318 };
319 
320 static const struct dce_audio_mask audio_mask = {
321 		AUD_COMMON_MASK_SH_LIST(_MASK)
322 };
323 
324 #define clk_src_regs(id)\
325 [id] = {\
326 	CS_COMMON_REG_LIST_DCE_100_110(id),\
327 }
328 
329 static const struct dce110_clk_src_regs clk_src_regs[] = {
330 	clk_src_regs(0),
331 	clk_src_regs(1),
332 	clk_src_regs(2)
333 };
334 
335 static const struct dce110_clk_src_shift cs_shift = {
336 		CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
337 };
338 
339 static const struct dce110_clk_src_mask cs_mask = {
340 		CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
341 };
342 
343 static const struct dce_dmcu_registers dmcu_regs = {
344 		DMCU_DCE110_COMMON_REG_LIST()
345 };
346 
347 static const struct dce_dmcu_shift dmcu_shift = {
348 		DMCU_MASK_SH_LIST_DCE110(__SHIFT)
349 };
350 
351 static const struct dce_dmcu_mask dmcu_mask = {
352 		DMCU_MASK_SH_LIST_DCE110(_MASK)
353 };
354 
355 static const struct dce_abm_registers abm_regs = {
356 		ABM_DCE110_COMMON_REG_LIST()
357 };
358 
359 static const struct dce_abm_shift abm_shift = {
360 		ABM_MASK_SH_LIST_DCE110(__SHIFT)
361 };
362 
363 static const struct dce_abm_mask abm_mask = {
364 		ABM_MASK_SH_LIST_DCE110(_MASK)
365 };
366 
367 #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03
368 
369 static const struct bios_registers bios_regs = {
370 	.BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
371 	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
372 };
373 
374 static const struct resource_caps res_cap = {
375 	.num_timing_generator = 6,
376 	.num_audio = 6,
377 	.num_stream_encoder = 6,
378 	.num_pll = 3,
379 	.num_ddc = 6,
380 };
381 
382 static const struct dc_plane_cap plane_cap = {
383 	.type = DC_PLANE_TYPE_DCE_RGB,
384 
385 	.pixel_format_support = {
386 			.argb8888 = true,
387 			.nv12 = false,
388 			.fp16 = true
389 	},
390 
391 	.max_upscale_factor = {
392 			.argb8888 = 16000,
393 			.nv12 = 1,
394 			.fp16 = 1
395 	},
396 
397 	.max_downscale_factor = {
398 			.argb8888 = 250,
399 			.nv12 = 1,
400 			.fp16 = 1
401 	}
402 };
403 
404 static const struct dc_debug_options debug_defaults = {
405 		.enable_legacy_fast_update = true,
406 };
407 
408 #define CTX  ctx
409 #define REG(reg) mm ## reg
410 
411 #ifndef mmCC_DC_HDMI_STRAPS
412 #define mmCC_DC_HDMI_STRAPS 0x1918
413 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
414 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
415 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
416 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
417 #endif
418 
419 static int map_transmitter_id_to_phy_instance(
420 	enum transmitter transmitter)
421 {
422 	switch (transmitter) {
423 	case TRANSMITTER_UNIPHY_A:
424 		return 0;
425 	case TRANSMITTER_UNIPHY_B:
426 		return 1;
427 	case TRANSMITTER_UNIPHY_C:
428 		return 2;
429 	case TRANSMITTER_UNIPHY_D:
430 		return 3;
431 	case TRANSMITTER_UNIPHY_E:
432 		return 4;
433 	case TRANSMITTER_UNIPHY_F:
434 		return 5;
435 	case TRANSMITTER_UNIPHY_G:
436 		return 6;
437 	default:
438 		ASSERT(0);
439 		return 0;
440 	}
441 }
442 
443 static void read_dce_straps(
444 	struct dc_context *ctx,
445 	struct resource_straps *straps)
446 {
447 	REG_GET_2(CC_DC_HDMI_STRAPS,
448 			HDMI_DISABLE, &straps->hdmi_disable,
449 			AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
450 
451 	REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
452 }
453 
454 static struct audio *create_audio(
455 		struct dc_context *ctx, unsigned int inst)
456 {
457 	return dce_audio_create(ctx, inst,
458 			&audio_regs[inst], &audio_shift, &audio_mask);
459 }
460 
461 static struct timing_generator *dce100_timing_generator_create(
462 		struct dc_context *ctx,
463 		uint32_t instance,
464 		const struct dce110_timing_generator_offsets *offsets)
465 {
466 	struct dce110_timing_generator *tg110 =
467 		kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
468 
469 	if (!tg110)
470 		return NULL;
471 
472 	dce110_timing_generator_construct(tg110, ctx, instance, offsets);
473 	return &tg110->base;
474 }
475 
476 static struct stream_encoder *dce100_stream_encoder_create(
477 	enum engine_id eng_id,
478 	struct dc_context *ctx)
479 {
480 	struct dce110_stream_encoder *enc110 =
481 		kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
482 
483 	if (!enc110)
484 		return NULL;
485 
486 	dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
487 					&stream_enc_regs[eng_id], &se_shift, &se_mask);
488 	return &enc110->base;
489 }
490 
491 #define SRII(reg_name, block, id)\
492 	.reg_name[id] = mm ## block ## id ## _ ## reg_name
493 
494 static const struct dce_hwseq_registers hwseq_reg = {
495 		HWSEQ_DCE10_REG_LIST()
496 };
497 
498 static const struct dce_hwseq_shift hwseq_shift = {
499 		HWSEQ_DCE10_MASK_SH_LIST(__SHIFT)
500 };
501 
502 static const struct dce_hwseq_mask hwseq_mask = {
503 		HWSEQ_DCE10_MASK_SH_LIST(_MASK)
504 };
505 
506 static struct dce_hwseq *dce100_hwseq_create(
507 	struct dc_context *ctx)
508 {
509 	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
510 
511 	if (hws) {
512 		hws->ctx = ctx;
513 		hws->regs = &hwseq_reg;
514 		hws->shifts = &hwseq_shift;
515 		hws->masks = &hwseq_mask;
516 	}
517 	return hws;
518 }
519 
520 static const struct resource_create_funcs res_create_funcs = {
521 	.read_dce_straps = read_dce_straps,
522 	.create_audio = create_audio,
523 	.create_stream_encoder = dce100_stream_encoder_create,
524 	.create_hwseq = dce100_hwseq_create,
525 };
526 
527 #define mi_inst_regs(id) { \
528 	MI_DCE8_REG_LIST(id), \
529 	.MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
530 }
531 static const struct dce_mem_input_registers mi_regs[] = {
532 		mi_inst_regs(0),
533 		mi_inst_regs(1),
534 		mi_inst_regs(2),
535 		mi_inst_regs(3),
536 		mi_inst_regs(4),
537 		mi_inst_regs(5),
538 };
539 
540 static const struct dce_mem_input_shift mi_shifts = {
541 		MI_DCE8_MASK_SH_LIST(__SHIFT),
542 		.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
543 };
544 
545 static const struct dce_mem_input_mask mi_masks = {
546 		MI_DCE8_MASK_SH_LIST(_MASK),
547 		.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
548 };
549 
550 static const struct dce110_aux_registers_shift aux_shift = {
551 	DCE10_AUX_MASK_SH_LIST(__SHIFT)
552 };
553 
554 static const struct dce110_aux_registers_mask aux_mask = {
555 	DCE10_AUX_MASK_SH_LIST(_MASK)
556 };
557 
558 static struct mem_input *dce100_mem_input_create(
559 	struct dc_context *ctx,
560 	uint32_t inst)
561 {
562 	struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
563 					       GFP_KERNEL);
564 
565 	if (!dce_mi) {
566 		BREAK_TO_DEBUGGER();
567 		return NULL;
568 	}
569 
570 	dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
571 	dce_mi->wa.single_head_rdreq_dmif_limit = 2;
572 	return &dce_mi->base;
573 }
574 
575 static void dce100_transform_destroy(struct transform **xfm)
576 {
577 	kfree(TO_DCE_TRANSFORM(*xfm));
578 	*xfm = NULL;
579 }
580 
581 static struct transform *dce100_transform_create(
582 	struct dc_context *ctx,
583 	uint32_t inst)
584 {
585 	struct dce_transform *transform =
586 		kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
587 
588 	if (!transform)
589 		return NULL;
590 
591 	dce_transform_construct(transform, ctx, inst,
592 				&xfm_regs[inst], &xfm_shift, &xfm_mask);
593 	return &transform->base;
594 }
595 
596 static struct input_pixel_processor *dce100_ipp_create(
597 	struct dc_context *ctx, uint32_t inst)
598 {
599 	struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
600 
601 	if (!ipp) {
602 		BREAK_TO_DEBUGGER();
603 		return NULL;
604 	}
605 
606 	dce_ipp_construct(ipp, ctx, inst,
607 			&ipp_regs[inst], &ipp_shift, &ipp_mask);
608 	return &ipp->base;
609 }
610 
611 static const struct encoder_feature_support link_enc_feature = {
612 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
613 		.max_hdmi_pixel_clock = 300000,
614 		.flags.bits.IS_HBR2_CAPABLE = true,
615 		.flags.bits.IS_TPS3_CAPABLE = true
616 };
617 
618 static struct link_encoder *dce100_link_encoder_create(
619 	struct dc_context *ctx,
620 	const struct encoder_init_data *enc_init_data)
621 {
622 	struct dce110_link_encoder *enc110 =
623 		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
624 	int link_regs_id;
625 
626 	if (!enc110)
627 		return NULL;
628 
629 	link_regs_id =
630 		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
631 
632 	dce110_link_encoder_construct(enc110,
633 				      enc_init_data,
634 				      &link_enc_feature,
635 				      &link_enc_regs[link_regs_id],
636 				      &link_enc_aux_regs[enc_init_data->channel - 1],
637 				      &link_enc_hpd_regs[enc_init_data->hpd_source]);
638 	return &enc110->base;
639 }
640 
641 static struct panel_cntl *dce100_panel_cntl_create(const struct panel_cntl_init_data *init_data)
642 {
643 	struct dce_panel_cntl *panel_cntl =
644 		kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
645 
646 	if (!panel_cntl)
647 		return NULL;
648 
649 	dce_panel_cntl_construct(panel_cntl,
650 			init_data,
651 			&panel_cntl_regs[init_data->inst],
652 			&panel_cntl_shift,
653 			&panel_cntl_mask);
654 
655 	return &panel_cntl->base;
656 }
657 
658 static struct output_pixel_processor *dce100_opp_create(
659 	struct dc_context *ctx,
660 	uint32_t inst)
661 {
662 	struct dce110_opp *opp =
663 		kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
664 
665 	if (!opp)
666 		return NULL;
667 
668 	dce110_opp_construct(opp,
669 			     ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
670 	return &opp->base;
671 }
672 
673 static struct dce_aux *dce100_aux_engine_create(
674 	struct dc_context *ctx,
675 	uint32_t inst)
676 {
677 	struct aux_engine_dce110 *aux_engine =
678 		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
679 
680 	if (!aux_engine)
681 		return NULL;
682 
683 	dce110_aux_engine_construct(aux_engine, ctx, inst,
684 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
685 				    &aux_engine_regs[inst],
686 					&aux_mask,
687 					&aux_shift,
688 					ctx->dc->caps.extended_aux_timeout_support);
689 
690 	return &aux_engine->base;
691 }
692 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
693 
694 static const struct dce_i2c_registers i2c_hw_regs[] = {
695 		i2c_inst_regs(1),
696 		i2c_inst_regs(2),
697 		i2c_inst_regs(3),
698 		i2c_inst_regs(4),
699 		i2c_inst_regs(5),
700 		i2c_inst_regs(6),
701 };
702 
703 static const struct dce_i2c_shift i2c_shifts = {
704 		I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
705 };
706 
707 static const struct dce_i2c_mask i2c_masks = {
708 		I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
709 };
710 
711 static struct dce_i2c_hw *dce100_i2c_hw_create(
712 	struct dc_context *ctx,
713 	uint32_t inst)
714 {
715 	struct dce_i2c_hw *dce_i2c_hw =
716 		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
717 
718 	if (!dce_i2c_hw)
719 		return NULL;
720 
721 	dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst,
722 				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
723 
724 	return dce_i2c_hw;
725 }
726 static struct clock_source *dce100_clock_source_create(
727 	struct dc_context *ctx,
728 	struct dc_bios *bios,
729 	enum clock_source_id id,
730 	const struct dce110_clk_src_regs *regs,
731 	bool dp_clk_src)
732 {
733 	struct dce110_clk_src *clk_src =
734 		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
735 
736 	if (!clk_src)
737 		return NULL;
738 
739 	if (dce110_clk_src_construct(clk_src, ctx, bios, id,
740 			regs, &cs_shift, &cs_mask)) {
741 		clk_src->base.dp_clk_src = dp_clk_src;
742 		return &clk_src->base;
743 	}
744 
745 	kfree(clk_src);
746 	BREAK_TO_DEBUGGER();
747 	return NULL;
748 }
749 
750 static void dce100_clock_source_destroy(struct clock_source **clk_src)
751 {
752 	kfree(TO_DCE110_CLK_SRC(*clk_src));
753 	*clk_src = NULL;
754 }
755 
756 static void dce100_resource_destruct(struct dce110_resource_pool *pool)
757 {
758 	unsigned int i;
759 
760 	for (i = 0; i < pool->base.pipe_count; i++) {
761 		if (pool->base.opps[i] != NULL)
762 			dce110_opp_destroy(&pool->base.opps[i]);
763 
764 		if (pool->base.transforms[i] != NULL)
765 			dce100_transform_destroy(&pool->base.transforms[i]);
766 
767 		if (pool->base.ipps[i] != NULL)
768 			dce_ipp_destroy(&pool->base.ipps[i]);
769 
770 		if (pool->base.mis[i] != NULL) {
771 			kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
772 			pool->base.mis[i] = NULL;
773 		}
774 
775 		if (pool->base.timing_generators[i] != NULL)	{
776 			kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
777 			pool->base.timing_generators[i] = NULL;
778 		}
779 	}
780 
781 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
782 		if (pool->base.engines[i] != NULL)
783 			dce110_engine_destroy(&pool->base.engines[i]);
784 		if (pool->base.hw_i2cs[i] != NULL) {
785 			kfree(pool->base.hw_i2cs[i]);
786 			pool->base.hw_i2cs[i] = NULL;
787 		}
788 		if (pool->base.sw_i2cs[i] != NULL) {
789 			kfree(pool->base.sw_i2cs[i]);
790 			pool->base.sw_i2cs[i] = NULL;
791 		}
792 	}
793 
794 	for (i = 0; i < pool->base.stream_enc_count; i++) {
795 		if (pool->base.stream_enc[i] != NULL)
796 			kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
797 	}
798 
799 	for (i = 0; i < pool->base.clk_src_count; i++) {
800 		if (pool->base.clock_sources[i] != NULL)
801 			dce100_clock_source_destroy(&pool->base.clock_sources[i]);
802 	}
803 
804 	if (pool->base.dp_clock_source != NULL)
805 		dce100_clock_source_destroy(&pool->base.dp_clock_source);
806 
807 	for (i = 0; i < pool->base.audio_count; i++)	{
808 		if (pool->base.audios[i] != NULL)
809 			dce_aud_destroy(&pool->base.audios[i]);
810 	}
811 
812 	if (pool->base.abm != NULL)
813 				dce_abm_destroy(&pool->base.abm);
814 
815 	if (pool->base.dmcu != NULL)
816 			dce_dmcu_destroy(&pool->base.dmcu);
817 
818 	if (pool->base.irqs != NULL)
819 		dal_irq_service_destroy(&pool->base.irqs);
820 }
821 
822 static enum dc_status build_mapped_resource(
823 		const struct dc  *dc,
824 		struct dc_state *context,
825 		struct dc_stream_state *stream)
826 {
827 	struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
828 
829 	if (!pipe_ctx)
830 		return DC_ERROR_UNEXPECTED;
831 
832 	dce110_resource_build_pipe_hw_param(pipe_ctx);
833 
834 	resource_build_info_frame(pipe_ctx);
835 
836 	return DC_OK;
837 }
838 
839 static bool dce100_validate_bandwidth(
840 	struct dc  *dc,
841 	struct dc_state *context,
842 	bool fast_validate)
843 {
844 	int i;
845 	bool at_least_one_pipe = false;
846 
847 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
848 		if (context->res_ctx.pipe_ctx[i].stream)
849 			at_least_one_pipe = true;
850 	}
851 
852 	if (at_least_one_pipe) {
853 		/* TODO implement when needed but for now hardcode max value*/
854 		context->bw_ctx.bw.dce.dispclk_khz = 681000;
855 		context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
856 	} else {
857 		context->bw_ctx.bw.dce.dispclk_khz = 0;
858 		context->bw_ctx.bw.dce.yclk_khz = 0;
859 	}
860 
861 	return true;
862 }
863 
864 static bool dce100_validate_surface_sets(
865 		struct dc_state *context)
866 {
867 	int i;
868 
869 	for (i = 0; i < context->stream_count; i++) {
870 		if (context->stream_status[i].plane_count == 0)
871 			continue;
872 
873 		if (context->stream_status[i].plane_count > 1)
874 			return false;
875 
876 		if (context->stream_status[i].plane_states[0]->format
877 				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
878 			return false;
879 	}
880 
881 	return true;
882 }
883 
884 static enum dc_status dce100_validate_global(
885 		struct dc  *dc,
886 		struct dc_state *context)
887 {
888 	if (!dce100_validate_surface_sets(context))
889 		return DC_FAIL_SURFACE_VALIDATE;
890 
891 	return DC_OK;
892 }
893 
894 enum dc_status dce100_add_stream_to_ctx(
895 		struct dc *dc,
896 		struct dc_state *new_ctx,
897 		struct dc_stream_state *dc_stream)
898 {
899 	enum dc_status result = DC_ERROR_UNEXPECTED;
900 
901 	result = resource_map_pool_resources(dc, new_ctx, dc_stream);
902 
903 	if (result == DC_OK)
904 		result = resource_map_clock_resources(dc, new_ctx, dc_stream);
905 
906 	if (result == DC_OK)
907 		result = build_mapped_resource(dc, new_ctx, dc_stream);
908 
909 	return result;
910 }
911 
912 static void dce100_destroy_resource_pool(struct resource_pool **pool)
913 {
914 	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
915 
916 	dce100_resource_destruct(dce110_pool);
917 	kfree(dce110_pool);
918 	*pool = NULL;
919 }
920 
921 enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
922 {
923 
924 	if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
925 		return DC_OK;
926 
927 	return DC_FAIL_SURFACE_VALIDATE;
928 }
929 
930 struct stream_encoder *dce100_find_first_free_match_stream_enc_for_link(
931 		struct resource_context *res_ctx,
932 		const struct resource_pool *pool,
933 		struct dc_stream_state *stream)
934 {
935 	int i;
936 	int j = -1;
937 	struct dc_link *link = stream->link;
938 
939 	for (i = 0; i < pool->stream_enc_count; i++) {
940 		if (!res_ctx->is_stream_enc_acquired[i] &&
941 				pool->stream_enc[i]) {
942 			/* Store first available for MST second display
943 			 * in daisy chain use case
944 			 */
945 			j = i;
946 			if (pool->stream_enc[i]->id ==
947 					link->link_enc->preferred_engine)
948 				return pool->stream_enc[i];
949 		}
950 	}
951 
952 	/*
953 	 * below can happen in cases when stream encoder is acquired:
954 	 * 1) for second MST display in chain, so preferred engine already
955 	 * acquired;
956 	 * 2) for another link, which preferred engine already acquired by any
957 	 * MST configuration.
958 	 *
959 	 * If signal is of DP type and preferred engine not found, return last available
960 	 *
961 	 * TODO - This is just a patch up and a generic solution is
962 	 * required for non DP connectors.
963 	 */
964 
965 	if (j >= 0 && link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT)
966 		return pool->stream_enc[j];
967 
968 	return NULL;
969 }
970 
971 static const struct resource_funcs dce100_res_pool_funcs = {
972 	.destroy = dce100_destroy_resource_pool,
973 	.link_enc_create = dce100_link_encoder_create,
974 	.panel_cntl_create = dce100_panel_cntl_create,
975 	.validate_bandwidth = dce100_validate_bandwidth,
976 	.validate_plane = dce100_validate_plane,
977 	.add_stream_to_ctx = dce100_add_stream_to_ctx,
978 	.validate_global = dce100_validate_global,
979 	.find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link
980 };
981 
982 static bool dce100_resource_construct(
983 	uint8_t num_virtual_links,
984 	struct dc  *dc,
985 	struct dce110_resource_pool *pool)
986 {
987 	unsigned int i;
988 	struct dc_context *ctx = dc->ctx;
989 	struct dc_bios *bp;
990 
991 	ctx->dc_bios->regs = &bios_regs;
992 
993 	pool->base.res_cap = &res_cap;
994 	pool->base.funcs = &dce100_res_pool_funcs;
995 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
996 
997 	bp = ctx->dc_bios;
998 
999 	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1000 		pool->base.dp_clock_source =
1001 				dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1002 
1003 		pool->base.clock_sources[0] =
1004 				dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
1005 		pool->base.clock_sources[1] =
1006 				dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1007 		pool->base.clock_sources[2] =
1008 				dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1009 		pool->base.clk_src_count = 3;
1010 
1011 	} else {
1012 		pool->base.dp_clock_source =
1013 				dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
1014 
1015 		pool->base.clock_sources[0] =
1016 				dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1017 		pool->base.clock_sources[1] =
1018 				dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1019 		pool->base.clk_src_count = 2;
1020 	}
1021 
1022 	if (pool->base.dp_clock_source == NULL) {
1023 		dm_error("DC: failed to create dp clock source!\n");
1024 		BREAK_TO_DEBUGGER();
1025 		goto res_create_fail;
1026 	}
1027 
1028 	for (i = 0; i < pool->base.clk_src_count; i++) {
1029 		if (pool->base.clock_sources[i] == NULL) {
1030 			dm_error("DC: failed to create clock sources!\n");
1031 			BREAK_TO_DEBUGGER();
1032 			goto res_create_fail;
1033 		}
1034 	}
1035 
1036 	pool->base.dmcu = dce_dmcu_create(ctx,
1037 			&dmcu_regs,
1038 			&dmcu_shift,
1039 			&dmcu_mask);
1040 	if (pool->base.dmcu == NULL) {
1041 		dm_error("DC: failed to create dmcu!\n");
1042 		BREAK_TO_DEBUGGER();
1043 		goto res_create_fail;
1044 	}
1045 
1046 	pool->base.abm = dce_abm_create(ctx,
1047 				&abm_regs,
1048 				&abm_shift,
1049 				&abm_mask);
1050 	if (pool->base.abm == NULL) {
1051 		dm_error("DC: failed to create abm!\n");
1052 		BREAK_TO_DEBUGGER();
1053 		goto res_create_fail;
1054 	}
1055 
1056 	{
1057 		struct irq_service_init_data init_data;
1058 		init_data.ctx = dc->ctx;
1059 		pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1060 		if (!pool->base.irqs)
1061 			goto res_create_fail;
1062 	}
1063 
1064 	/*************************************************
1065 	*  Resource + asic cap harcoding                *
1066 	*************************************************/
1067 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1068 	pool->base.pipe_count = res_cap.num_timing_generator;
1069 	pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1070 	dc->caps.max_downscale_ratio = 200;
1071 	dc->caps.i2c_speed_in_khz = 40;
1072 	dc->caps.i2c_speed_in_khz = 40;
1073 	dc->caps.max_cursor_size = 128;
1074 	dc->caps.min_horizontal_blanking_period = 80;
1075 	dc->caps.dual_link_dvi = true;
1076 	dc->caps.disable_dp_clk_share = true;
1077 	dc->caps.extended_aux_timeout_support = false;
1078 	dc->debug = debug_defaults;
1079 
1080 	for (i = 0; i < pool->base.pipe_count; i++) {
1081 		pool->base.timing_generators[i] =
1082 			dce100_timing_generator_create(
1083 				ctx,
1084 				i,
1085 				&dce100_tg_offsets[i]);
1086 		if (pool->base.timing_generators[i] == NULL) {
1087 			BREAK_TO_DEBUGGER();
1088 			dm_error("DC: failed to create tg!\n");
1089 			goto res_create_fail;
1090 		}
1091 
1092 		pool->base.mis[i] = dce100_mem_input_create(ctx, i);
1093 		if (pool->base.mis[i] == NULL) {
1094 			BREAK_TO_DEBUGGER();
1095 			dm_error(
1096 				"DC: failed to create memory input!\n");
1097 			goto res_create_fail;
1098 		}
1099 
1100 		pool->base.ipps[i] = dce100_ipp_create(ctx, i);
1101 		if (pool->base.ipps[i] == NULL) {
1102 			BREAK_TO_DEBUGGER();
1103 			dm_error(
1104 				"DC: failed to create input pixel processor!\n");
1105 			goto res_create_fail;
1106 		}
1107 
1108 		pool->base.transforms[i] = dce100_transform_create(ctx, i);
1109 		if (pool->base.transforms[i] == NULL) {
1110 			BREAK_TO_DEBUGGER();
1111 			dm_error(
1112 				"DC: failed to create transform!\n");
1113 			goto res_create_fail;
1114 		}
1115 
1116 		pool->base.opps[i] = dce100_opp_create(ctx, i);
1117 		if (pool->base.opps[i] == NULL) {
1118 			BREAK_TO_DEBUGGER();
1119 			dm_error(
1120 				"DC: failed to create output pixel processor!\n");
1121 			goto res_create_fail;
1122 		}
1123 	}
1124 
1125 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1126 		pool->base.engines[i] = dce100_aux_engine_create(ctx, i);
1127 		if (pool->base.engines[i] == NULL) {
1128 			BREAK_TO_DEBUGGER();
1129 			dm_error(
1130 				"DC:failed to create aux engine!!\n");
1131 			goto res_create_fail;
1132 		}
1133 		pool->base.hw_i2cs[i] = dce100_i2c_hw_create(ctx, i);
1134 		if (pool->base.hw_i2cs[i] == NULL) {
1135 			BREAK_TO_DEBUGGER();
1136 			dm_error(
1137 				"DC:failed to create i2c engine!!\n");
1138 			goto res_create_fail;
1139 		}
1140 		pool->base.sw_i2cs[i] = NULL;
1141 	}
1142 
1143 	dc->caps.max_planes =  pool->base.pipe_count;
1144 
1145 	for (i = 0; i < dc->caps.max_planes; ++i)
1146 		dc->caps.planes[i] = plane_cap;
1147 
1148 	if (!resource_construct(num_virtual_links, dc, &pool->base,
1149 			&res_create_funcs))
1150 		goto res_create_fail;
1151 
1152 	/* Create hardware sequencer */
1153 	dce100_hw_sequencer_construct(dc);
1154 	return true;
1155 
1156 res_create_fail:
1157 	dce100_resource_destruct(pool);
1158 
1159 	return false;
1160 }
1161 
1162 struct resource_pool *dce100_create_resource_pool(
1163 	uint8_t num_virtual_links,
1164 	struct dc  *dc)
1165 {
1166 	struct dce110_resource_pool *pool =
1167 		kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1168 
1169 	if (!pool)
1170 		return NULL;
1171 
1172 	if (dce100_resource_construct(num_virtual_links, dc, pool))
1173 		return &pool->base;
1174 
1175 	kfree(pool);
1176 	BREAK_TO_DEBUGGER();
1177 	return NULL;
1178 }
1179 
1180