1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include "dm_services.h" 26 27 #include "link_encoder.h" 28 #include "stream_encoder.h" 29 30 #include "resource.h" 31 #include "include/irq_service_interface.h" 32 #include "../virtual/virtual_stream_encoder.h" 33 #include "dce110/dce110_resource.h" 34 #include "dce110/dce110_timing_generator.h" 35 #include "irq/dce110/irq_service_dce110.h" 36 #include "dce/dce_link_encoder.h" 37 #include "dce/dce_stream_encoder.h" 38 39 #include "dce/dce_clk_mgr.h" 40 #include "dce/dce_mem_input.h" 41 #include "dce/dce_ipp.h" 42 #include "dce/dce_transform.h" 43 #include "dce/dce_opp.h" 44 #include "dce/dce_clock_source.h" 45 #include "dce/dce_audio.h" 46 #include "dce/dce_hwseq.h" 47 #include "dce100/dce100_hw_sequencer.h" 48 49 #include "reg_helper.h" 50 51 #include "dce/dce_10_0_d.h" 52 #include "dce/dce_10_0_sh_mask.h" 53 54 #include "dce/dce_dmcu.h" 55 #include "dce/dce_aux.h" 56 #include "dce/dce_abm.h" 57 #include "dce/dce_i2c.h" 58 59 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 60 #include "gmc/gmc_8_2_d.h" 61 #include "gmc/gmc_8_2_sh_mask.h" 62 #endif 63 64 #ifndef mmDP_DPHY_INTERNAL_CTRL 65 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 66 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 67 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 68 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 69 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 70 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 71 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 72 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 73 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 74 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 75 #endif 76 77 #ifndef mmBIOS_SCRATCH_2 78 #define mmBIOS_SCRATCH_2 0x05CB 79 #define mmBIOS_SCRATCH_3 0x05CC 80 #define mmBIOS_SCRATCH_6 0x05CF 81 #endif 82 83 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 84 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 85 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 86 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 87 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 88 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 89 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 90 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 91 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 92 #endif 93 94 #ifndef mmDP_DPHY_FAST_TRAINING 95 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 96 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 97 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 98 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 99 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 100 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 101 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 102 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 103 #endif 104 105 static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = { 106 { 107 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 108 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 109 }, 110 { 111 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 112 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 113 }, 114 { 115 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 116 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 117 }, 118 { 119 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 120 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 121 }, 122 { 123 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 124 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 125 }, 126 { 127 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 128 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 129 } 130 }; 131 132 /* set register offset */ 133 #define SR(reg_name)\ 134 .reg_name = mm ## reg_name 135 136 /* set register offset with instance */ 137 #define SRI(reg_name, block, id)\ 138 .reg_name = mm ## block ## id ## _ ## reg_name 139 140 141 static const struct clk_mgr_registers disp_clk_regs = { 142 CLK_COMMON_REG_LIST_DCE_BASE() 143 }; 144 145 static const struct clk_mgr_shift disp_clk_shift = { 146 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 147 }; 148 149 static const struct clk_mgr_mask disp_clk_mask = { 150 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 151 }; 152 153 #define ipp_regs(id)\ 154 [id] = {\ 155 IPP_DCE100_REG_LIST_DCE_BASE(id)\ 156 } 157 158 static const struct dce_ipp_registers ipp_regs[] = { 159 ipp_regs(0), 160 ipp_regs(1), 161 ipp_regs(2), 162 ipp_regs(3), 163 ipp_regs(4), 164 ipp_regs(5) 165 }; 166 167 static const struct dce_ipp_shift ipp_shift = { 168 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 169 }; 170 171 static const struct dce_ipp_mask ipp_mask = { 172 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 173 }; 174 175 #define transform_regs(id)\ 176 [id] = {\ 177 XFM_COMMON_REG_LIST_DCE100(id)\ 178 } 179 180 static const struct dce_transform_registers xfm_regs[] = { 181 transform_regs(0), 182 transform_regs(1), 183 transform_regs(2), 184 transform_regs(3), 185 transform_regs(4), 186 transform_regs(5) 187 }; 188 189 static const struct dce_transform_shift xfm_shift = { 190 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 191 }; 192 193 static const struct dce_transform_mask xfm_mask = { 194 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 195 }; 196 197 #define aux_regs(id)\ 198 [id] = {\ 199 AUX_REG_LIST(id)\ 200 } 201 202 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 203 aux_regs(0), 204 aux_regs(1), 205 aux_regs(2), 206 aux_regs(3), 207 aux_regs(4), 208 aux_regs(5) 209 }; 210 211 #define hpd_regs(id)\ 212 [id] = {\ 213 HPD_REG_LIST(id)\ 214 } 215 216 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 217 hpd_regs(0), 218 hpd_regs(1), 219 hpd_regs(2), 220 hpd_regs(3), 221 hpd_regs(4), 222 hpd_regs(5) 223 }; 224 225 #define link_regs(id)\ 226 [id] = {\ 227 LE_DCE100_REG_LIST(id)\ 228 } 229 230 static const struct dce110_link_enc_registers link_enc_regs[] = { 231 link_regs(0), 232 link_regs(1), 233 link_regs(2), 234 link_regs(3), 235 link_regs(4), 236 link_regs(5), 237 link_regs(6), 238 }; 239 240 #define stream_enc_regs(id)\ 241 [id] = {\ 242 SE_COMMON_REG_LIST_DCE_BASE(id),\ 243 .AFMT_CNTL = 0,\ 244 } 245 246 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 247 stream_enc_regs(0), 248 stream_enc_regs(1), 249 stream_enc_regs(2), 250 stream_enc_regs(3), 251 stream_enc_regs(4), 252 stream_enc_regs(5), 253 stream_enc_regs(6) 254 }; 255 256 static const struct dce_stream_encoder_shift se_shift = { 257 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) 258 }; 259 260 static const struct dce_stream_encoder_mask se_mask = { 261 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) 262 }; 263 264 #define opp_regs(id)\ 265 [id] = {\ 266 OPP_DCE_100_REG_LIST(id),\ 267 } 268 269 static const struct dce_opp_registers opp_regs[] = { 270 opp_regs(0), 271 opp_regs(1), 272 opp_regs(2), 273 opp_regs(3), 274 opp_regs(4), 275 opp_regs(5) 276 }; 277 278 static const struct dce_opp_shift opp_shift = { 279 OPP_COMMON_MASK_SH_LIST_DCE_100(__SHIFT) 280 }; 281 282 static const struct dce_opp_mask opp_mask = { 283 OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK) 284 }; 285 #define aux_engine_regs(id)\ 286 [id] = {\ 287 AUX_COMMON_REG_LIST(id), \ 288 .AUX_RESET_MASK = 0 \ 289 } 290 291 static const struct dce110_aux_registers aux_engine_regs[] = { 292 aux_engine_regs(0), 293 aux_engine_regs(1), 294 aux_engine_regs(2), 295 aux_engine_regs(3), 296 aux_engine_regs(4), 297 aux_engine_regs(5) 298 }; 299 300 #define audio_regs(id)\ 301 [id] = {\ 302 AUD_COMMON_REG_LIST(id)\ 303 } 304 305 static const struct dce_audio_registers audio_regs[] = { 306 audio_regs(0), 307 audio_regs(1), 308 audio_regs(2), 309 audio_regs(3), 310 audio_regs(4), 311 audio_regs(5), 312 audio_regs(6), 313 }; 314 315 static const struct dce_audio_shift audio_shift = { 316 AUD_COMMON_MASK_SH_LIST(__SHIFT) 317 }; 318 319 static const struct dce_aduio_mask audio_mask = { 320 AUD_COMMON_MASK_SH_LIST(_MASK) 321 }; 322 323 #define clk_src_regs(id)\ 324 [id] = {\ 325 CS_COMMON_REG_LIST_DCE_100_110(id),\ 326 } 327 328 static const struct dce110_clk_src_regs clk_src_regs[] = { 329 clk_src_regs(0), 330 clk_src_regs(1), 331 clk_src_regs(2) 332 }; 333 334 static const struct dce110_clk_src_shift cs_shift = { 335 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 336 }; 337 338 static const struct dce110_clk_src_mask cs_mask = { 339 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 340 }; 341 342 static const struct dce_dmcu_registers dmcu_regs = { 343 DMCU_DCE110_COMMON_REG_LIST() 344 }; 345 346 static const struct dce_dmcu_shift dmcu_shift = { 347 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 348 }; 349 350 static const struct dce_dmcu_mask dmcu_mask = { 351 DMCU_MASK_SH_LIST_DCE110(_MASK) 352 }; 353 354 static const struct dce_abm_registers abm_regs = { 355 ABM_DCE110_COMMON_REG_LIST() 356 }; 357 358 static const struct dce_abm_shift abm_shift = { 359 ABM_MASK_SH_LIST_DCE110(__SHIFT) 360 }; 361 362 static const struct dce_abm_mask abm_mask = { 363 ABM_MASK_SH_LIST_DCE110(_MASK) 364 }; 365 366 #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03 367 368 static const struct bios_registers bios_regs = { 369 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 370 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 371 }; 372 373 static const struct resource_caps res_cap = { 374 .num_timing_generator = 6, 375 .num_audio = 6, 376 .num_stream_encoder = 6, 377 .num_pll = 3, 378 .num_ddc = 6, 379 }; 380 381 static const struct dc_plane_cap plane_cap = { 382 .type = DC_PLANE_TYPE_DCE_RGB, 383 384 .pixel_format_support = { 385 .argb8888 = true, 386 .nv12 = false, 387 .fp16 = false 388 }, 389 390 .max_upscale_factor = { 391 .argb8888 = 16000, 392 .nv12 = 1, 393 .fp16 = 1 394 }, 395 396 .max_downscale_factor = { 397 .argb8888 = 250, 398 .nv12 = 1, 399 .fp16 = 1 400 } 401 }; 402 403 #define CTX ctx 404 #define REG(reg) mm ## reg 405 406 #ifndef mmCC_DC_HDMI_STRAPS 407 #define mmCC_DC_HDMI_STRAPS 0x1918 408 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 409 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 410 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 411 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 412 #endif 413 414 static void read_dce_straps( 415 struct dc_context *ctx, 416 struct resource_straps *straps) 417 { 418 REG_GET_2(CC_DC_HDMI_STRAPS, 419 HDMI_DISABLE, &straps->hdmi_disable, 420 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 421 422 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 423 } 424 425 static struct audio *create_audio( 426 struct dc_context *ctx, unsigned int inst) 427 { 428 return dce_audio_create(ctx, inst, 429 &audio_regs[inst], &audio_shift, &audio_mask); 430 } 431 432 static struct timing_generator *dce100_timing_generator_create( 433 struct dc_context *ctx, 434 uint32_t instance, 435 const struct dce110_timing_generator_offsets *offsets) 436 { 437 struct dce110_timing_generator *tg110 = 438 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 439 440 if (!tg110) 441 return NULL; 442 443 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 444 return &tg110->base; 445 } 446 447 static struct stream_encoder *dce100_stream_encoder_create( 448 enum engine_id eng_id, 449 struct dc_context *ctx) 450 { 451 struct dce110_stream_encoder *enc110 = 452 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 453 454 if (!enc110) 455 return NULL; 456 457 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 458 &stream_enc_regs[eng_id], &se_shift, &se_mask); 459 return &enc110->base; 460 } 461 462 #define SRII(reg_name, block, id)\ 463 .reg_name[id] = mm ## block ## id ## _ ## reg_name 464 465 static const struct dce_hwseq_registers hwseq_reg = { 466 HWSEQ_DCE10_REG_LIST() 467 }; 468 469 static const struct dce_hwseq_shift hwseq_shift = { 470 HWSEQ_DCE10_MASK_SH_LIST(__SHIFT) 471 }; 472 473 static const struct dce_hwseq_mask hwseq_mask = { 474 HWSEQ_DCE10_MASK_SH_LIST(_MASK) 475 }; 476 477 static struct dce_hwseq *dce100_hwseq_create( 478 struct dc_context *ctx) 479 { 480 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 481 482 if (hws) { 483 hws->ctx = ctx; 484 hws->regs = &hwseq_reg; 485 hws->shifts = &hwseq_shift; 486 hws->masks = &hwseq_mask; 487 } 488 return hws; 489 } 490 491 static const struct resource_create_funcs res_create_funcs = { 492 .read_dce_straps = read_dce_straps, 493 .create_audio = create_audio, 494 .create_stream_encoder = dce100_stream_encoder_create, 495 .create_hwseq = dce100_hwseq_create, 496 }; 497 498 #define mi_inst_regs(id) { \ 499 MI_DCE8_REG_LIST(id), \ 500 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 501 } 502 static const struct dce_mem_input_registers mi_regs[] = { 503 mi_inst_regs(0), 504 mi_inst_regs(1), 505 mi_inst_regs(2), 506 mi_inst_regs(3), 507 mi_inst_regs(4), 508 mi_inst_regs(5), 509 }; 510 511 static const struct dce_mem_input_shift mi_shifts = { 512 MI_DCE8_MASK_SH_LIST(__SHIFT), 513 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 514 }; 515 516 static const struct dce_mem_input_mask mi_masks = { 517 MI_DCE8_MASK_SH_LIST(_MASK), 518 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 519 }; 520 521 static struct mem_input *dce100_mem_input_create( 522 struct dc_context *ctx, 523 uint32_t inst) 524 { 525 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 526 GFP_KERNEL); 527 528 if (!dce_mi) { 529 BREAK_TO_DEBUGGER(); 530 return NULL; 531 } 532 533 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 534 dce_mi->wa.single_head_rdreq_dmif_limit = 2; 535 return &dce_mi->base; 536 } 537 538 static void dce100_transform_destroy(struct transform **xfm) 539 { 540 kfree(TO_DCE_TRANSFORM(*xfm)); 541 *xfm = NULL; 542 } 543 544 static struct transform *dce100_transform_create( 545 struct dc_context *ctx, 546 uint32_t inst) 547 { 548 struct dce_transform *transform = 549 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 550 551 if (!transform) 552 return NULL; 553 554 dce_transform_construct(transform, ctx, inst, 555 &xfm_regs[inst], &xfm_shift, &xfm_mask); 556 return &transform->base; 557 } 558 559 static struct input_pixel_processor *dce100_ipp_create( 560 struct dc_context *ctx, uint32_t inst) 561 { 562 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 563 564 if (!ipp) { 565 BREAK_TO_DEBUGGER(); 566 return NULL; 567 } 568 569 dce_ipp_construct(ipp, ctx, inst, 570 &ipp_regs[inst], &ipp_shift, &ipp_mask); 571 return &ipp->base; 572 } 573 574 static const struct encoder_feature_support link_enc_feature = { 575 .max_hdmi_deep_color = COLOR_DEPTH_121212, 576 .max_hdmi_pixel_clock = 300000, 577 .flags.bits.IS_HBR2_CAPABLE = true, 578 .flags.bits.IS_TPS3_CAPABLE = true 579 }; 580 581 struct link_encoder *dce100_link_encoder_create( 582 const struct encoder_init_data *enc_init_data) 583 { 584 struct dce110_link_encoder *enc110 = 585 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 586 587 if (!enc110) 588 return NULL; 589 590 dce110_link_encoder_construct(enc110, 591 enc_init_data, 592 &link_enc_feature, 593 &link_enc_regs[enc_init_data->transmitter], 594 &link_enc_aux_regs[enc_init_data->channel - 1], 595 &link_enc_hpd_regs[enc_init_data->hpd_source]); 596 return &enc110->base; 597 } 598 599 struct output_pixel_processor *dce100_opp_create( 600 struct dc_context *ctx, 601 uint32_t inst) 602 { 603 struct dce110_opp *opp = 604 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 605 606 if (!opp) 607 return NULL; 608 609 dce110_opp_construct(opp, 610 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 611 return &opp->base; 612 } 613 614 struct dce_aux *dce100_aux_engine_create( 615 struct dc_context *ctx, 616 uint32_t inst) 617 { 618 struct aux_engine_dce110 *aux_engine = 619 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 620 621 if (!aux_engine) 622 return NULL; 623 624 dce110_aux_engine_construct(aux_engine, ctx, inst, 625 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 626 &aux_engine_regs[inst]); 627 628 return &aux_engine->base; 629 } 630 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 631 632 static const struct dce_i2c_registers i2c_hw_regs[] = { 633 i2c_inst_regs(1), 634 i2c_inst_regs(2), 635 i2c_inst_regs(3), 636 i2c_inst_regs(4), 637 i2c_inst_regs(5), 638 i2c_inst_regs(6), 639 }; 640 641 static const struct dce_i2c_shift i2c_shifts = { 642 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 643 }; 644 645 static const struct dce_i2c_mask i2c_masks = { 646 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 647 }; 648 649 struct dce_i2c_hw *dce100_i2c_hw_create( 650 struct dc_context *ctx, 651 uint32_t inst) 652 { 653 struct dce_i2c_hw *dce_i2c_hw = 654 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 655 656 if (!dce_i2c_hw) 657 return NULL; 658 659 dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst, 660 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 661 662 return dce_i2c_hw; 663 } 664 struct clock_source *dce100_clock_source_create( 665 struct dc_context *ctx, 666 struct dc_bios *bios, 667 enum clock_source_id id, 668 const struct dce110_clk_src_regs *regs, 669 bool dp_clk_src) 670 { 671 struct dce110_clk_src *clk_src = 672 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 673 674 if (!clk_src) 675 return NULL; 676 677 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 678 regs, &cs_shift, &cs_mask)) { 679 clk_src->base.dp_clk_src = dp_clk_src; 680 return &clk_src->base; 681 } 682 683 BREAK_TO_DEBUGGER(); 684 return NULL; 685 } 686 687 void dce100_clock_source_destroy(struct clock_source **clk_src) 688 { 689 kfree(TO_DCE110_CLK_SRC(*clk_src)); 690 *clk_src = NULL; 691 } 692 693 static void destruct(struct dce110_resource_pool *pool) 694 { 695 unsigned int i; 696 697 for (i = 0; i < pool->base.pipe_count; i++) { 698 if (pool->base.opps[i] != NULL) 699 dce110_opp_destroy(&pool->base.opps[i]); 700 701 if (pool->base.transforms[i] != NULL) 702 dce100_transform_destroy(&pool->base.transforms[i]); 703 704 if (pool->base.ipps[i] != NULL) 705 dce_ipp_destroy(&pool->base.ipps[i]); 706 707 if (pool->base.mis[i] != NULL) { 708 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 709 pool->base.mis[i] = NULL; 710 } 711 712 if (pool->base.timing_generators[i] != NULL) { 713 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 714 pool->base.timing_generators[i] = NULL; 715 } 716 } 717 718 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 719 if (pool->base.engines[i] != NULL) 720 dce110_engine_destroy(&pool->base.engines[i]); 721 if (pool->base.hw_i2cs[i] != NULL) { 722 kfree(pool->base.hw_i2cs[i]); 723 pool->base.hw_i2cs[i] = NULL; 724 } 725 if (pool->base.sw_i2cs[i] != NULL) { 726 kfree(pool->base.sw_i2cs[i]); 727 pool->base.sw_i2cs[i] = NULL; 728 } 729 } 730 731 for (i = 0; i < pool->base.stream_enc_count; i++) { 732 if (pool->base.stream_enc[i] != NULL) 733 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 734 } 735 736 for (i = 0; i < pool->base.clk_src_count; i++) { 737 if (pool->base.clock_sources[i] != NULL) 738 dce100_clock_source_destroy(&pool->base.clock_sources[i]); 739 } 740 741 if (pool->base.dp_clock_source != NULL) 742 dce100_clock_source_destroy(&pool->base.dp_clock_source); 743 744 for (i = 0; i < pool->base.audio_count; i++) { 745 if (pool->base.audios[i] != NULL) 746 dce_aud_destroy(&pool->base.audios[i]); 747 } 748 749 if (pool->base.clk_mgr != NULL) 750 dce_clk_mgr_destroy(&pool->base.clk_mgr); 751 752 if (pool->base.abm != NULL) 753 dce_abm_destroy(&pool->base.abm); 754 755 if (pool->base.dmcu != NULL) 756 dce_dmcu_destroy(&pool->base.dmcu); 757 758 if (pool->base.irqs != NULL) 759 dal_irq_service_destroy(&pool->base.irqs); 760 } 761 762 static enum dc_status build_mapped_resource( 763 const struct dc *dc, 764 struct dc_state *context, 765 struct dc_stream_state *stream) 766 { 767 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 768 769 if (!pipe_ctx) 770 return DC_ERROR_UNEXPECTED; 771 772 dce110_resource_build_pipe_hw_param(pipe_ctx); 773 774 resource_build_info_frame(pipe_ctx); 775 776 return DC_OK; 777 } 778 779 bool dce100_validate_bandwidth( 780 struct dc *dc, 781 struct dc_state *context, 782 bool fast_validate) 783 { 784 int i; 785 bool at_least_one_pipe = false; 786 787 for (i = 0; i < dc->res_pool->pipe_count; i++) { 788 if (context->res_ctx.pipe_ctx[i].stream) 789 at_least_one_pipe = true; 790 } 791 792 if (at_least_one_pipe) { 793 /* TODO implement when needed but for now hardcode max value*/ 794 context->bw_ctx.bw.dce.dispclk_khz = 681000; 795 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; 796 } else { 797 context->bw_ctx.bw.dce.dispclk_khz = 0; 798 context->bw_ctx.bw.dce.yclk_khz = 0; 799 } 800 801 return true; 802 } 803 804 static bool dce100_validate_surface_sets( 805 struct dc_state *context) 806 { 807 int i; 808 809 for (i = 0; i < context->stream_count; i++) { 810 if (context->stream_status[i].plane_count == 0) 811 continue; 812 813 if (context->stream_status[i].plane_count > 1) 814 return false; 815 816 if (context->stream_status[i].plane_states[0]->format 817 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 818 return false; 819 } 820 821 return true; 822 } 823 824 enum dc_status dce100_validate_global( 825 struct dc *dc, 826 struct dc_state *context) 827 { 828 if (!dce100_validate_surface_sets(context)) 829 return DC_FAIL_SURFACE_VALIDATE; 830 831 return DC_OK; 832 } 833 834 enum dc_status dce100_add_stream_to_ctx( 835 struct dc *dc, 836 struct dc_state *new_ctx, 837 struct dc_stream_state *dc_stream) 838 { 839 enum dc_status result = DC_ERROR_UNEXPECTED; 840 841 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 842 843 if (result == DC_OK) 844 result = resource_map_clock_resources(dc, new_ctx, dc_stream); 845 846 if (result == DC_OK) 847 result = build_mapped_resource(dc, new_ctx, dc_stream); 848 849 return result; 850 } 851 852 static void dce100_destroy_resource_pool(struct resource_pool **pool) 853 { 854 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 855 856 destruct(dce110_pool); 857 kfree(dce110_pool); 858 *pool = NULL; 859 } 860 861 enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) 862 { 863 864 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 865 return DC_OK; 866 867 return DC_FAIL_SURFACE_VALIDATE; 868 } 869 870 static const struct resource_funcs dce100_res_pool_funcs = { 871 .destroy = dce100_destroy_resource_pool, 872 .link_enc_create = dce100_link_encoder_create, 873 .validate_bandwidth = dce100_validate_bandwidth, 874 .validate_plane = dce100_validate_plane, 875 .add_stream_to_ctx = dce100_add_stream_to_ctx, 876 .validate_global = dce100_validate_global 877 }; 878 879 static bool construct( 880 uint8_t num_virtual_links, 881 struct dc *dc, 882 struct dce110_resource_pool *pool) 883 { 884 unsigned int i; 885 struct dc_context *ctx = dc->ctx; 886 struct dc_firmware_info info; 887 struct dc_bios *bp; 888 889 ctx->dc_bios->regs = &bios_regs; 890 891 pool->base.res_cap = &res_cap; 892 pool->base.funcs = &dce100_res_pool_funcs; 893 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 894 895 bp = ctx->dc_bios; 896 897 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 898 info.external_clock_source_frequency_for_dp != 0) { 899 pool->base.dp_clock_source = 900 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 901 902 pool->base.clock_sources[0] = 903 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 904 pool->base.clock_sources[1] = 905 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 906 pool->base.clock_sources[2] = 907 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 908 pool->base.clk_src_count = 3; 909 910 } else { 911 pool->base.dp_clock_source = 912 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 913 914 pool->base.clock_sources[0] = 915 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 916 pool->base.clock_sources[1] = 917 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 918 pool->base.clk_src_count = 2; 919 } 920 921 if (pool->base.dp_clock_source == NULL) { 922 dm_error("DC: failed to create dp clock source!\n"); 923 BREAK_TO_DEBUGGER(); 924 goto res_create_fail; 925 } 926 927 for (i = 0; i < pool->base.clk_src_count; i++) { 928 if (pool->base.clock_sources[i] == NULL) { 929 dm_error("DC: failed to create clock sources!\n"); 930 BREAK_TO_DEBUGGER(); 931 goto res_create_fail; 932 } 933 } 934 935 pool->base.clk_mgr = dce_clk_mgr_create(ctx, 936 &disp_clk_regs, 937 &disp_clk_shift, 938 &disp_clk_mask); 939 if (pool->base.clk_mgr == NULL) { 940 dm_error("DC: failed to create display clock!\n"); 941 BREAK_TO_DEBUGGER(); 942 goto res_create_fail; 943 } 944 945 pool->base.dmcu = dce_dmcu_create(ctx, 946 &dmcu_regs, 947 &dmcu_shift, 948 &dmcu_mask); 949 if (pool->base.dmcu == NULL) { 950 dm_error("DC: failed to create dmcu!\n"); 951 BREAK_TO_DEBUGGER(); 952 goto res_create_fail; 953 } 954 955 pool->base.abm = dce_abm_create(ctx, 956 &abm_regs, 957 &abm_shift, 958 &abm_mask); 959 if (pool->base.abm == NULL) { 960 dm_error("DC: failed to create abm!\n"); 961 BREAK_TO_DEBUGGER(); 962 goto res_create_fail; 963 } 964 965 { 966 struct irq_service_init_data init_data; 967 init_data.ctx = dc->ctx; 968 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 969 if (!pool->base.irqs) 970 goto res_create_fail; 971 } 972 973 /************************************************* 974 * Resource + asic cap harcoding * 975 *************************************************/ 976 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 977 pool->base.pipe_count = res_cap.num_timing_generator; 978 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 979 dc->caps.max_downscale_ratio = 200; 980 dc->caps.i2c_speed_in_khz = 40; 981 dc->caps.max_cursor_size = 128; 982 dc->caps.dual_link_dvi = true; 983 dc->caps.disable_dp_clk_share = true; 984 for (i = 0; i < pool->base.pipe_count; i++) { 985 pool->base.timing_generators[i] = 986 dce100_timing_generator_create( 987 ctx, 988 i, 989 &dce100_tg_offsets[i]); 990 if (pool->base.timing_generators[i] == NULL) { 991 BREAK_TO_DEBUGGER(); 992 dm_error("DC: failed to create tg!\n"); 993 goto res_create_fail; 994 } 995 996 pool->base.mis[i] = dce100_mem_input_create(ctx, i); 997 if (pool->base.mis[i] == NULL) { 998 BREAK_TO_DEBUGGER(); 999 dm_error( 1000 "DC: failed to create memory input!\n"); 1001 goto res_create_fail; 1002 } 1003 1004 pool->base.ipps[i] = dce100_ipp_create(ctx, i); 1005 if (pool->base.ipps[i] == NULL) { 1006 BREAK_TO_DEBUGGER(); 1007 dm_error( 1008 "DC: failed to create input pixel processor!\n"); 1009 goto res_create_fail; 1010 } 1011 1012 pool->base.transforms[i] = dce100_transform_create(ctx, i); 1013 if (pool->base.transforms[i] == NULL) { 1014 BREAK_TO_DEBUGGER(); 1015 dm_error( 1016 "DC: failed to create transform!\n"); 1017 goto res_create_fail; 1018 } 1019 1020 pool->base.opps[i] = dce100_opp_create(ctx, i); 1021 if (pool->base.opps[i] == NULL) { 1022 BREAK_TO_DEBUGGER(); 1023 dm_error( 1024 "DC: failed to create output pixel processor!\n"); 1025 goto res_create_fail; 1026 } 1027 } 1028 1029 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1030 pool->base.engines[i] = dce100_aux_engine_create(ctx, i); 1031 if (pool->base.engines[i] == NULL) { 1032 BREAK_TO_DEBUGGER(); 1033 dm_error( 1034 "DC:failed to create aux engine!!\n"); 1035 goto res_create_fail; 1036 } 1037 pool->base.hw_i2cs[i] = dce100_i2c_hw_create(ctx, i); 1038 if (pool->base.hw_i2cs[i] == NULL) { 1039 BREAK_TO_DEBUGGER(); 1040 dm_error( 1041 "DC:failed to create i2c engine!!\n"); 1042 goto res_create_fail; 1043 } 1044 pool->base.sw_i2cs[i] = NULL; 1045 } 1046 1047 dc->caps.max_planes = pool->base.pipe_count; 1048 1049 for (i = 0; i < dc->caps.max_planes; ++i) 1050 dc->caps.planes[i] = plane_cap; 1051 1052 if (!resource_construct(num_virtual_links, dc, &pool->base, 1053 &res_create_funcs)) 1054 goto res_create_fail; 1055 1056 /* Create hardware sequencer */ 1057 dce100_hw_sequencer_construct(dc); 1058 return true; 1059 1060 res_create_fail: 1061 destruct(pool); 1062 1063 return false; 1064 } 1065 1066 struct resource_pool *dce100_create_resource_pool( 1067 uint8_t num_virtual_links, 1068 struct dc *dc) 1069 { 1070 struct dce110_resource_pool *pool = 1071 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1072 1073 if (!pool) 1074 return NULL; 1075 1076 if (construct(num_virtual_links, dc, pool)) 1077 return &pool->base; 1078 1079 BREAK_TO_DEBUGGER(); 1080 return NULL; 1081 } 1082 1083