1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 30 #include "link_encoder.h" 31 #include "stream_encoder.h" 32 33 #include "resource.h" 34 #include "include/irq_service_interface.h" 35 #include "../virtual/virtual_stream_encoder.h" 36 #include "dce110/dce110_resource.h" 37 #include "dce110/dce110_timing_generator.h" 38 #include "irq/dce110/irq_service_dce110.h" 39 #include "dce/dce_link_encoder.h" 40 #include "dce/dce_stream_encoder.h" 41 #include "dce/dce_mem_input.h" 42 #include "dce/dce_ipp.h" 43 #include "dce/dce_transform.h" 44 #include "dce/dce_opp.h" 45 #include "dce/dce_clock_source.h" 46 #include "dce/dce_audio.h" 47 #include "dce/dce_hwseq.h" 48 #include "dce100/dce100_hw_sequencer.h" 49 50 #include "reg_helper.h" 51 52 #include "dce/dce_10_0_d.h" 53 #include "dce/dce_10_0_sh_mask.h" 54 55 #include "dce/dce_dmcu.h" 56 #include "dce/dce_aux.h" 57 #include "dce/dce_abm.h" 58 #include "dce/dce_i2c.h" 59 60 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 61 #include "gmc/gmc_8_2_d.h" 62 #include "gmc/gmc_8_2_sh_mask.h" 63 #endif 64 65 #ifndef mmDP_DPHY_INTERNAL_CTRL 66 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 67 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 68 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 69 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 70 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 71 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 72 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 73 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 74 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 75 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 76 #endif 77 78 #ifndef mmBIOS_SCRATCH_2 79 #define mmBIOS_SCRATCH_2 0x05CB 80 #define mmBIOS_SCRATCH_3 0x05CC 81 #define mmBIOS_SCRATCH_6 0x05CF 82 #endif 83 84 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 85 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 86 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 87 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 88 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 89 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 90 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 91 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 92 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 93 #endif 94 95 #ifndef mmDP_DPHY_FAST_TRAINING 96 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 97 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 98 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 99 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 100 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 101 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 102 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 103 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 104 #endif 105 106 static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = { 107 { 108 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 109 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 110 }, 111 { 112 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 113 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 114 }, 115 { 116 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 117 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 118 }, 119 { 120 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 121 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 122 }, 123 { 124 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 125 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 126 }, 127 { 128 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 129 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 130 } 131 }; 132 133 /* set register offset */ 134 #define SR(reg_name)\ 135 .reg_name = mm ## reg_name 136 137 /* set register offset with instance */ 138 #define SRI(reg_name, block, id)\ 139 .reg_name = mm ## block ## id ## _ ## reg_name 140 141 #define ipp_regs(id)\ 142 [id] = {\ 143 IPP_DCE100_REG_LIST_DCE_BASE(id)\ 144 } 145 146 static const struct dce_ipp_registers ipp_regs[] = { 147 ipp_regs(0), 148 ipp_regs(1), 149 ipp_regs(2), 150 ipp_regs(3), 151 ipp_regs(4), 152 ipp_regs(5) 153 }; 154 155 static const struct dce_ipp_shift ipp_shift = { 156 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 157 }; 158 159 static const struct dce_ipp_mask ipp_mask = { 160 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 161 }; 162 163 #define transform_regs(id)\ 164 [id] = {\ 165 XFM_COMMON_REG_LIST_DCE100(id)\ 166 } 167 168 static const struct dce_transform_registers xfm_regs[] = { 169 transform_regs(0), 170 transform_regs(1), 171 transform_regs(2), 172 transform_regs(3), 173 transform_regs(4), 174 transform_regs(5) 175 }; 176 177 static const struct dce_transform_shift xfm_shift = { 178 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 179 }; 180 181 static const struct dce_transform_mask xfm_mask = { 182 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 183 }; 184 185 #define aux_regs(id)\ 186 [id] = {\ 187 AUX_REG_LIST(id)\ 188 } 189 190 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 191 aux_regs(0), 192 aux_regs(1), 193 aux_regs(2), 194 aux_regs(3), 195 aux_regs(4), 196 aux_regs(5) 197 }; 198 199 #define hpd_regs(id)\ 200 [id] = {\ 201 HPD_REG_LIST(id)\ 202 } 203 204 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 205 hpd_regs(0), 206 hpd_regs(1), 207 hpd_regs(2), 208 hpd_regs(3), 209 hpd_regs(4), 210 hpd_regs(5) 211 }; 212 213 #define link_regs(id)\ 214 [id] = {\ 215 LE_DCE100_REG_LIST(id)\ 216 } 217 218 static const struct dce110_link_enc_registers link_enc_regs[] = { 219 link_regs(0), 220 link_regs(1), 221 link_regs(2), 222 link_regs(3), 223 link_regs(4), 224 link_regs(5), 225 link_regs(6), 226 }; 227 228 #define stream_enc_regs(id)\ 229 [id] = {\ 230 SE_COMMON_REG_LIST_DCE_BASE(id),\ 231 .AFMT_CNTL = 0,\ 232 } 233 234 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 235 stream_enc_regs(0), 236 stream_enc_regs(1), 237 stream_enc_regs(2), 238 stream_enc_regs(3), 239 stream_enc_regs(4), 240 stream_enc_regs(5), 241 stream_enc_regs(6) 242 }; 243 244 static const struct dce_stream_encoder_shift se_shift = { 245 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) 246 }; 247 248 static const struct dce_stream_encoder_mask se_mask = { 249 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) 250 }; 251 252 #define opp_regs(id)\ 253 [id] = {\ 254 OPP_DCE_100_REG_LIST(id),\ 255 } 256 257 static const struct dce_opp_registers opp_regs[] = { 258 opp_regs(0), 259 opp_regs(1), 260 opp_regs(2), 261 opp_regs(3), 262 opp_regs(4), 263 opp_regs(5) 264 }; 265 266 static const struct dce_opp_shift opp_shift = { 267 OPP_COMMON_MASK_SH_LIST_DCE_100(__SHIFT) 268 }; 269 270 static const struct dce_opp_mask opp_mask = { 271 OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK) 272 }; 273 #define aux_engine_regs(id)\ 274 [id] = {\ 275 AUX_COMMON_REG_LIST(id), \ 276 .AUX_RESET_MASK = 0 \ 277 } 278 279 static const struct dce110_aux_registers aux_engine_regs[] = { 280 aux_engine_regs(0), 281 aux_engine_regs(1), 282 aux_engine_regs(2), 283 aux_engine_regs(3), 284 aux_engine_regs(4), 285 aux_engine_regs(5) 286 }; 287 288 #define audio_regs(id)\ 289 [id] = {\ 290 AUD_COMMON_REG_LIST(id)\ 291 } 292 293 static const struct dce_audio_registers audio_regs[] = { 294 audio_regs(0), 295 audio_regs(1), 296 audio_regs(2), 297 audio_regs(3), 298 audio_regs(4), 299 audio_regs(5), 300 audio_regs(6), 301 }; 302 303 static const struct dce_audio_shift audio_shift = { 304 AUD_COMMON_MASK_SH_LIST(__SHIFT) 305 }; 306 307 static const struct dce_audio_mask audio_mask = { 308 AUD_COMMON_MASK_SH_LIST(_MASK) 309 }; 310 311 #define clk_src_regs(id)\ 312 [id] = {\ 313 CS_COMMON_REG_LIST_DCE_100_110(id),\ 314 } 315 316 static const struct dce110_clk_src_regs clk_src_regs[] = { 317 clk_src_regs(0), 318 clk_src_regs(1), 319 clk_src_regs(2) 320 }; 321 322 static const struct dce110_clk_src_shift cs_shift = { 323 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 324 }; 325 326 static const struct dce110_clk_src_mask cs_mask = { 327 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 328 }; 329 330 static const struct dce_dmcu_registers dmcu_regs = { 331 DMCU_DCE110_COMMON_REG_LIST() 332 }; 333 334 static const struct dce_dmcu_shift dmcu_shift = { 335 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 336 }; 337 338 static const struct dce_dmcu_mask dmcu_mask = { 339 DMCU_MASK_SH_LIST_DCE110(_MASK) 340 }; 341 342 static const struct dce_abm_registers abm_regs = { 343 ABM_DCE110_COMMON_REG_LIST() 344 }; 345 346 static const struct dce_abm_shift abm_shift = { 347 ABM_MASK_SH_LIST_DCE110(__SHIFT) 348 }; 349 350 static const struct dce_abm_mask abm_mask = { 351 ABM_MASK_SH_LIST_DCE110(_MASK) 352 }; 353 354 #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03 355 356 static const struct bios_registers bios_regs = { 357 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 358 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 359 }; 360 361 static const struct resource_caps res_cap = { 362 .num_timing_generator = 6, 363 .num_audio = 6, 364 .num_stream_encoder = 6, 365 .num_pll = 3, 366 .num_ddc = 6, 367 }; 368 369 static const struct dc_plane_cap plane_cap = { 370 .type = DC_PLANE_TYPE_DCE_RGB, 371 372 .pixel_format_support = { 373 .argb8888 = true, 374 .nv12 = false, 375 .fp16 = false 376 }, 377 378 .max_upscale_factor = { 379 .argb8888 = 16000, 380 .nv12 = 1, 381 .fp16 = 1 382 }, 383 384 .max_downscale_factor = { 385 .argb8888 = 250, 386 .nv12 = 1, 387 .fp16 = 1 388 } 389 }; 390 391 #define CTX ctx 392 #define REG(reg) mm ## reg 393 394 #ifndef mmCC_DC_HDMI_STRAPS 395 #define mmCC_DC_HDMI_STRAPS 0x1918 396 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 397 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 398 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 399 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 400 #endif 401 402 static int map_transmitter_id_to_phy_instance( 403 enum transmitter transmitter) 404 { 405 switch (transmitter) { 406 case TRANSMITTER_UNIPHY_A: 407 return 0; 408 break; 409 case TRANSMITTER_UNIPHY_B: 410 return 1; 411 break; 412 case TRANSMITTER_UNIPHY_C: 413 return 2; 414 break; 415 case TRANSMITTER_UNIPHY_D: 416 return 3; 417 break; 418 case TRANSMITTER_UNIPHY_E: 419 return 4; 420 break; 421 case TRANSMITTER_UNIPHY_F: 422 return 5; 423 break; 424 case TRANSMITTER_UNIPHY_G: 425 return 6; 426 break; 427 default: 428 ASSERT(0); 429 return 0; 430 } 431 } 432 433 static void read_dce_straps( 434 struct dc_context *ctx, 435 struct resource_straps *straps) 436 { 437 REG_GET_2(CC_DC_HDMI_STRAPS, 438 HDMI_DISABLE, &straps->hdmi_disable, 439 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 440 441 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 442 } 443 444 static struct audio *create_audio( 445 struct dc_context *ctx, unsigned int inst) 446 { 447 return dce_audio_create(ctx, inst, 448 &audio_regs[inst], &audio_shift, &audio_mask); 449 } 450 451 static struct timing_generator *dce100_timing_generator_create( 452 struct dc_context *ctx, 453 uint32_t instance, 454 const struct dce110_timing_generator_offsets *offsets) 455 { 456 struct dce110_timing_generator *tg110 = 457 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 458 459 if (!tg110) 460 return NULL; 461 462 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 463 return &tg110->base; 464 } 465 466 static struct stream_encoder *dce100_stream_encoder_create( 467 enum engine_id eng_id, 468 struct dc_context *ctx) 469 { 470 struct dce110_stream_encoder *enc110 = 471 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 472 473 if (!enc110) 474 return NULL; 475 476 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 477 &stream_enc_regs[eng_id], &se_shift, &se_mask); 478 return &enc110->base; 479 } 480 481 #define SRII(reg_name, block, id)\ 482 .reg_name[id] = mm ## block ## id ## _ ## reg_name 483 484 static const struct dce_hwseq_registers hwseq_reg = { 485 HWSEQ_DCE10_REG_LIST() 486 }; 487 488 static const struct dce_hwseq_shift hwseq_shift = { 489 HWSEQ_DCE10_MASK_SH_LIST(__SHIFT) 490 }; 491 492 static const struct dce_hwseq_mask hwseq_mask = { 493 HWSEQ_DCE10_MASK_SH_LIST(_MASK) 494 }; 495 496 static struct dce_hwseq *dce100_hwseq_create( 497 struct dc_context *ctx) 498 { 499 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 500 501 if (hws) { 502 hws->ctx = ctx; 503 hws->regs = &hwseq_reg; 504 hws->shifts = &hwseq_shift; 505 hws->masks = &hwseq_mask; 506 } 507 return hws; 508 } 509 510 static const struct resource_create_funcs res_create_funcs = { 511 .read_dce_straps = read_dce_straps, 512 .create_audio = create_audio, 513 .create_stream_encoder = dce100_stream_encoder_create, 514 .create_hwseq = dce100_hwseq_create, 515 }; 516 517 #define mi_inst_regs(id) { \ 518 MI_DCE8_REG_LIST(id), \ 519 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 520 } 521 static const struct dce_mem_input_registers mi_regs[] = { 522 mi_inst_regs(0), 523 mi_inst_regs(1), 524 mi_inst_regs(2), 525 mi_inst_regs(3), 526 mi_inst_regs(4), 527 mi_inst_regs(5), 528 }; 529 530 static const struct dce_mem_input_shift mi_shifts = { 531 MI_DCE8_MASK_SH_LIST(__SHIFT), 532 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 533 }; 534 535 static const struct dce_mem_input_mask mi_masks = { 536 MI_DCE8_MASK_SH_LIST(_MASK), 537 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 538 }; 539 540 static const struct dce110_aux_registers_shift aux_shift = { 541 DCE10_AUX_MASK_SH_LIST(__SHIFT) 542 }; 543 544 static const struct dce110_aux_registers_mask aux_mask = { 545 DCE10_AUX_MASK_SH_LIST(_MASK) 546 }; 547 548 static struct mem_input *dce100_mem_input_create( 549 struct dc_context *ctx, 550 uint32_t inst) 551 { 552 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 553 GFP_KERNEL); 554 555 if (!dce_mi) { 556 BREAK_TO_DEBUGGER(); 557 return NULL; 558 } 559 560 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 561 dce_mi->wa.single_head_rdreq_dmif_limit = 2; 562 return &dce_mi->base; 563 } 564 565 static void dce100_transform_destroy(struct transform **xfm) 566 { 567 kfree(TO_DCE_TRANSFORM(*xfm)); 568 *xfm = NULL; 569 } 570 571 static struct transform *dce100_transform_create( 572 struct dc_context *ctx, 573 uint32_t inst) 574 { 575 struct dce_transform *transform = 576 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 577 578 if (!transform) 579 return NULL; 580 581 dce_transform_construct(transform, ctx, inst, 582 &xfm_regs[inst], &xfm_shift, &xfm_mask); 583 return &transform->base; 584 } 585 586 static struct input_pixel_processor *dce100_ipp_create( 587 struct dc_context *ctx, uint32_t inst) 588 { 589 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 590 591 if (!ipp) { 592 BREAK_TO_DEBUGGER(); 593 return NULL; 594 } 595 596 dce_ipp_construct(ipp, ctx, inst, 597 &ipp_regs[inst], &ipp_shift, &ipp_mask); 598 return &ipp->base; 599 } 600 601 static const struct encoder_feature_support link_enc_feature = { 602 .max_hdmi_deep_color = COLOR_DEPTH_121212, 603 .max_hdmi_pixel_clock = 300000, 604 .flags.bits.IS_HBR2_CAPABLE = true, 605 .flags.bits.IS_TPS3_CAPABLE = true 606 }; 607 608 struct link_encoder *dce100_link_encoder_create( 609 const struct encoder_init_data *enc_init_data) 610 { 611 struct dce110_link_encoder *enc110 = 612 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 613 int link_regs_id; 614 615 if (!enc110) 616 return NULL; 617 618 link_regs_id = 619 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 620 621 dce110_link_encoder_construct(enc110, 622 enc_init_data, 623 &link_enc_feature, 624 &link_enc_regs[link_regs_id], 625 &link_enc_aux_regs[enc_init_data->channel - 1], 626 &link_enc_hpd_regs[enc_init_data->hpd_source]); 627 return &enc110->base; 628 } 629 630 struct output_pixel_processor *dce100_opp_create( 631 struct dc_context *ctx, 632 uint32_t inst) 633 { 634 struct dce110_opp *opp = 635 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 636 637 if (!opp) 638 return NULL; 639 640 dce110_opp_construct(opp, 641 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 642 return &opp->base; 643 } 644 645 struct dce_aux *dce100_aux_engine_create( 646 struct dc_context *ctx, 647 uint32_t inst) 648 { 649 struct aux_engine_dce110 *aux_engine = 650 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 651 652 if (!aux_engine) 653 return NULL; 654 655 dce110_aux_engine_construct(aux_engine, ctx, inst, 656 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 657 &aux_engine_regs[inst], 658 &aux_mask, 659 &aux_shift, 660 ctx->dc->caps.extended_aux_timeout_support); 661 662 return &aux_engine->base; 663 } 664 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 665 666 static const struct dce_i2c_registers i2c_hw_regs[] = { 667 i2c_inst_regs(1), 668 i2c_inst_regs(2), 669 i2c_inst_regs(3), 670 i2c_inst_regs(4), 671 i2c_inst_regs(5), 672 i2c_inst_regs(6), 673 }; 674 675 static const struct dce_i2c_shift i2c_shifts = { 676 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 677 }; 678 679 static const struct dce_i2c_mask i2c_masks = { 680 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 681 }; 682 683 struct dce_i2c_hw *dce100_i2c_hw_create( 684 struct dc_context *ctx, 685 uint32_t inst) 686 { 687 struct dce_i2c_hw *dce_i2c_hw = 688 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 689 690 if (!dce_i2c_hw) 691 return NULL; 692 693 dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst, 694 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 695 696 return dce_i2c_hw; 697 } 698 struct clock_source *dce100_clock_source_create( 699 struct dc_context *ctx, 700 struct dc_bios *bios, 701 enum clock_source_id id, 702 const struct dce110_clk_src_regs *regs, 703 bool dp_clk_src) 704 { 705 struct dce110_clk_src *clk_src = 706 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 707 708 if (!clk_src) 709 return NULL; 710 711 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 712 regs, &cs_shift, &cs_mask)) { 713 clk_src->base.dp_clk_src = dp_clk_src; 714 return &clk_src->base; 715 } 716 717 kfree(clk_src); 718 BREAK_TO_DEBUGGER(); 719 return NULL; 720 } 721 722 void dce100_clock_source_destroy(struct clock_source **clk_src) 723 { 724 kfree(TO_DCE110_CLK_SRC(*clk_src)); 725 *clk_src = NULL; 726 } 727 728 static void dce100_resource_destruct(struct dce110_resource_pool *pool) 729 { 730 unsigned int i; 731 732 for (i = 0; i < pool->base.pipe_count; i++) { 733 if (pool->base.opps[i] != NULL) 734 dce110_opp_destroy(&pool->base.opps[i]); 735 736 if (pool->base.transforms[i] != NULL) 737 dce100_transform_destroy(&pool->base.transforms[i]); 738 739 if (pool->base.ipps[i] != NULL) 740 dce_ipp_destroy(&pool->base.ipps[i]); 741 742 if (pool->base.mis[i] != NULL) { 743 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 744 pool->base.mis[i] = NULL; 745 } 746 747 if (pool->base.timing_generators[i] != NULL) { 748 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 749 pool->base.timing_generators[i] = NULL; 750 } 751 } 752 753 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 754 if (pool->base.engines[i] != NULL) 755 dce110_engine_destroy(&pool->base.engines[i]); 756 if (pool->base.hw_i2cs[i] != NULL) { 757 kfree(pool->base.hw_i2cs[i]); 758 pool->base.hw_i2cs[i] = NULL; 759 } 760 if (pool->base.sw_i2cs[i] != NULL) { 761 kfree(pool->base.sw_i2cs[i]); 762 pool->base.sw_i2cs[i] = NULL; 763 } 764 } 765 766 for (i = 0; i < pool->base.stream_enc_count; i++) { 767 if (pool->base.stream_enc[i] != NULL) 768 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 769 } 770 771 for (i = 0; i < pool->base.clk_src_count; i++) { 772 if (pool->base.clock_sources[i] != NULL) 773 dce100_clock_source_destroy(&pool->base.clock_sources[i]); 774 } 775 776 if (pool->base.dp_clock_source != NULL) 777 dce100_clock_source_destroy(&pool->base.dp_clock_source); 778 779 for (i = 0; i < pool->base.audio_count; i++) { 780 if (pool->base.audios[i] != NULL) 781 dce_aud_destroy(&pool->base.audios[i]); 782 } 783 784 if (pool->base.abm != NULL) 785 dce_abm_destroy(&pool->base.abm); 786 787 if (pool->base.dmcu != NULL) 788 dce_dmcu_destroy(&pool->base.dmcu); 789 790 if (pool->base.irqs != NULL) 791 dal_irq_service_destroy(&pool->base.irqs); 792 } 793 794 static enum dc_status build_mapped_resource( 795 const struct dc *dc, 796 struct dc_state *context, 797 struct dc_stream_state *stream) 798 { 799 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 800 801 if (!pipe_ctx) 802 return DC_ERROR_UNEXPECTED; 803 804 dce110_resource_build_pipe_hw_param(pipe_ctx); 805 806 resource_build_info_frame(pipe_ctx); 807 808 return DC_OK; 809 } 810 811 bool dce100_validate_bandwidth( 812 struct dc *dc, 813 struct dc_state *context, 814 bool fast_validate) 815 { 816 int i; 817 bool at_least_one_pipe = false; 818 819 for (i = 0; i < dc->res_pool->pipe_count; i++) { 820 if (context->res_ctx.pipe_ctx[i].stream) 821 at_least_one_pipe = true; 822 } 823 824 if (at_least_one_pipe) { 825 /* TODO implement when needed but for now hardcode max value*/ 826 context->bw_ctx.bw.dce.dispclk_khz = 681000; 827 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; 828 } else { 829 context->bw_ctx.bw.dce.dispclk_khz = 0; 830 context->bw_ctx.bw.dce.yclk_khz = 0; 831 } 832 833 return true; 834 } 835 836 static bool dce100_validate_surface_sets( 837 struct dc_state *context) 838 { 839 int i; 840 841 for (i = 0; i < context->stream_count; i++) { 842 if (context->stream_status[i].plane_count == 0) 843 continue; 844 845 if (context->stream_status[i].plane_count > 1) 846 return false; 847 848 if (context->stream_status[i].plane_states[0]->format 849 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 850 return false; 851 } 852 853 return true; 854 } 855 856 enum dc_status dce100_validate_global( 857 struct dc *dc, 858 struct dc_state *context) 859 { 860 if (!dce100_validate_surface_sets(context)) 861 return DC_FAIL_SURFACE_VALIDATE; 862 863 return DC_OK; 864 } 865 866 enum dc_status dce100_add_stream_to_ctx( 867 struct dc *dc, 868 struct dc_state *new_ctx, 869 struct dc_stream_state *dc_stream) 870 { 871 enum dc_status result = DC_ERROR_UNEXPECTED; 872 873 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 874 875 if (result == DC_OK) 876 result = resource_map_clock_resources(dc, new_ctx, dc_stream); 877 878 if (result == DC_OK) 879 result = build_mapped_resource(dc, new_ctx, dc_stream); 880 881 return result; 882 } 883 884 static void dce100_destroy_resource_pool(struct resource_pool **pool) 885 { 886 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 887 888 dce100_resource_destruct(dce110_pool); 889 kfree(dce110_pool); 890 *pool = NULL; 891 } 892 893 enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) 894 { 895 896 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 897 return DC_OK; 898 899 return DC_FAIL_SURFACE_VALIDATE; 900 } 901 902 struct stream_encoder *dce100_find_first_free_match_stream_enc_for_link( 903 struct resource_context *res_ctx, 904 const struct resource_pool *pool, 905 struct dc_stream_state *stream) 906 { 907 int i; 908 int j = -1; 909 struct dc_link *link = stream->link; 910 911 for (i = 0; i < pool->stream_enc_count; i++) { 912 if (!res_ctx->is_stream_enc_acquired[i] && 913 pool->stream_enc[i]) { 914 /* Store first available for MST second display 915 * in daisy chain use case 916 */ 917 j = i; 918 if (pool->stream_enc[i]->id == 919 link->link_enc->preferred_engine) 920 return pool->stream_enc[i]; 921 } 922 } 923 924 /* 925 * below can happen in cases when stream encoder is acquired: 926 * 1) for second MST display in chain, so preferred engine already 927 * acquired; 928 * 2) for another link, which preferred engine already acquired by any 929 * MST configuration. 930 * 931 * If signal is of DP type and preferred engine not found, return last available 932 * 933 * TODO - This is just a patch up and a generic solution is 934 * required for non DP connectors. 935 */ 936 937 if (j >= 0 && link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) 938 return pool->stream_enc[j]; 939 940 return NULL; 941 } 942 943 static const struct resource_funcs dce100_res_pool_funcs = { 944 .destroy = dce100_destroy_resource_pool, 945 .link_enc_create = dce100_link_encoder_create, 946 .validate_bandwidth = dce100_validate_bandwidth, 947 .validate_plane = dce100_validate_plane, 948 .add_stream_to_ctx = dce100_add_stream_to_ctx, 949 .validate_global = dce100_validate_global, 950 .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link 951 }; 952 953 static bool dce100_resource_construct( 954 uint8_t num_virtual_links, 955 struct dc *dc, 956 struct dce110_resource_pool *pool) 957 { 958 unsigned int i; 959 struct dc_context *ctx = dc->ctx; 960 struct dc_bios *bp; 961 962 ctx->dc_bios->regs = &bios_regs; 963 964 pool->base.res_cap = &res_cap; 965 pool->base.funcs = &dce100_res_pool_funcs; 966 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 967 968 bp = ctx->dc_bios; 969 970 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 971 pool->base.dp_clock_source = 972 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 973 974 pool->base.clock_sources[0] = 975 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 976 pool->base.clock_sources[1] = 977 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 978 pool->base.clock_sources[2] = 979 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 980 pool->base.clk_src_count = 3; 981 982 } else { 983 pool->base.dp_clock_source = 984 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 985 986 pool->base.clock_sources[0] = 987 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 988 pool->base.clock_sources[1] = 989 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 990 pool->base.clk_src_count = 2; 991 } 992 993 if (pool->base.dp_clock_source == NULL) { 994 dm_error("DC: failed to create dp clock source!\n"); 995 BREAK_TO_DEBUGGER(); 996 goto res_create_fail; 997 } 998 999 for (i = 0; i < pool->base.clk_src_count; i++) { 1000 if (pool->base.clock_sources[i] == NULL) { 1001 dm_error("DC: failed to create clock sources!\n"); 1002 BREAK_TO_DEBUGGER(); 1003 goto res_create_fail; 1004 } 1005 } 1006 1007 pool->base.dmcu = dce_dmcu_create(ctx, 1008 &dmcu_regs, 1009 &dmcu_shift, 1010 &dmcu_mask); 1011 if (pool->base.dmcu == NULL) { 1012 dm_error("DC: failed to create dmcu!\n"); 1013 BREAK_TO_DEBUGGER(); 1014 goto res_create_fail; 1015 } 1016 1017 pool->base.abm = dce_abm_create(ctx, 1018 &abm_regs, 1019 &abm_shift, 1020 &abm_mask); 1021 if (pool->base.abm == NULL) { 1022 dm_error("DC: failed to create abm!\n"); 1023 BREAK_TO_DEBUGGER(); 1024 goto res_create_fail; 1025 } 1026 1027 { 1028 struct irq_service_init_data init_data; 1029 init_data.ctx = dc->ctx; 1030 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 1031 if (!pool->base.irqs) 1032 goto res_create_fail; 1033 } 1034 1035 /************************************************* 1036 * Resource + asic cap harcoding * 1037 *************************************************/ 1038 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1039 pool->base.pipe_count = res_cap.num_timing_generator; 1040 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1041 dc->caps.max_downscale_ratio = 200; 1042 dc->caps.i2c_speed_in_khz = 40; 1043 dc->caps.max_cursor_size = 128; 1044 dc->caps.dual_link_dvi = true; 1045 dc->caps.disable_dp_clk_share = true; 1046 dc->caps.extended_aux_timeout_support = false; 1047 1048 for (i = 0; i < pool->base.pipe_count; i++) { 1049 pool->base.timing_generators[i] = 1050 dce100_timing_generator_create( 1051 ctx, 1052 i, 1053 &dce100_tg_offsets[i]); 1054 if (pool->base.timing_generators[i] == NULL) { 1055 BREAK_TO_DEBUGGER(); 1056 dm_error("DC: failed to create tg!\n"); 1057 goto res_create_fail; 1058 } 1059 1060 pool->base.mis[i] = dce100_mem_input_create(ctx, i); 1061 if (pool->base.mis[i] == NULL) { 1062 BREAK_TO_DEBUGGER(); 1063 dm_error( 1064 "DC: failed to create memory input!\n"); 1065 goto res_create_fail; 1066 } 1067 1068 pool->base.ipps[i] = dce100_ipp_create(ctx, i); 1069 if (pool->base.ipps[i] == NULL) { 1070 BREAK_TO_DEBUGGER(); 1071 dm_error( 1072 "DC: failed to create input pixel processor!\n"); 1073 goto res_create_fail; 1074 } 1075 1076 pool->base.transforms[i] = dce100_transform_create(ctx, i); 1077 if (pool->base.transforms[i] == NULL) { 1078 BREAK_TO_DEBUGGER(); 1079 dm_error( 1080 "DC: failed to create transform!\n"); 1081 goto res_create_fail; 1082 } 1083 1084 pool->base.opps[i] = dce100_opp_create(ctx, i); 1085 if (pool->base.opps[i] == NULL) { 1086 BREAK_TO_DEBUGGER(); 1087 dm_error( 1088 "DC: failed to create output pixel processor!\n"); 1089 goto res_create_fail; 1090 } 1091 } 1092 1093 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1094 pool->base.engines[i] = dce100_aux_engine_create(ctx, i); 1095 if (pool->base.engines[i] == NULL) { 1096 BREAK_TO_DEBUGGER(); 1097 dm_error( 1098 "DC:failed to create aux engine!!\n"); 1099 goto res_create_fail; 1100 } 1101 pool->base.hw_i2cs[i] = dce100_i2c_hw_create(ctx, i); 1102 if (pool->base.hw_i2cs[i] == NULL) { 1103 BREAK_TO_DEBUGGER(); 1104 dm_error( 1105 "DC:failed to create i2c engine!!\n"); 1106 goto res_create_fail; 1107 } 1108 pool->base.sw_i2cs[i] = NULL; 1109 } 1110 1111 dc->caps.max_planes = pool->base.pipe_count; 1112 1113 for (i = 0; i < dc->caps.max_planes; ++i) 1114 dc->caps.planes[i] = plane_cap; 1115 1116 if (!resource_construct(num_virtual_links, dc, &pool->base, 1117 &res_create_funcs)) 1118 goto res_create_fail; 1119 1120 /* Create hardware sequencer */ 1121 dce100_hw_sequencer_construct(dc); 1122 return true; 1123 1124 res_create_fail: 1125 dce100_resource_destruct(pool); 1126 1127 return false; 1128 } 1129 1130 struct resource_pool *dce100_create_resource_pool( 1131 uint8_t num_virtual_links, 1132 struct dc *dc) 1133 { 1134 struct dce110_resource_pool *pool = 1135 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1136 1137 if (!pool) 1138 return NULL; 1139 1140 if (dce100_resource_construct(num_virtual_links, dc, pool)) 1141 return &pool->base; 1142 1143 kfree(pool); 1144 BREAK_TO_DEBUGGER(); 1145 return NULL; 1146 } 1147 1148