1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dmub_psr.h" 27 #include "dc.h" 28 #include "dc_dmub_srv.h" 29 #include "dmub/dmub_srv.h" 30 #include "core_types.h" 31 32 #define DC_TRACE_LEVEL_MESSAGE(...) do {} while (0) /* do nothing */ 33 34 #define MAX_PIPES 6 35 36 static const uint8_t DP_SINK_DEVICE_STR_ID_1[] = {7, 1, 8, 7, 3}; 37 static const uint8_t DP_SINK_DEVICE_STR_ID_2[] = {7, 1, 8, 7, 5}; 38 39 /* 40 * Convert dmcub psr state to dmcu psr state. 41 */ 42 static enum dc_psr_state convert_psr_state(uint32_t raw_state) 43 { 44 enum dc_psr_state state = PSR_STATE0; 45 46 if (raw_state == 0) 47 state = PSR_STATE0; 48 else if (raw_state == 0x10) 49 state = PSR_STATE1; 50 else if (raw_state == 0x11) 51 state = PSR_STATE1a; 52 else if (raw_state == 0x20) 53 state = PSR_STATE2; 54 else if (raw_state == 0x21) 55 state = PSR_STATE2a; 56 else if (raw_state == 0x22) 57 state = PSR_STATE2b; 58 else if (raw_state == 0x30) 59 state = PSR_STATE3; 60 else if (raw_state == 0x31) 61 state = PSR_STATE3Init; 62 else if (raw_state == 0x40) 63 state = PSR_STATE4; 64 else if (raw_state == 0x41) 65 state = PSR_STATE4a; 66 else if (raw_state == 0x42) 67 state = PSR_STATE4b; 68 else if (raw_state == 0x43) 69 state = PSR_STATE4c; 70 else if (raw_state == 0x44) 71 state = PSR_STATE4d; 72 else if (raw_state == 0x50) 73 state = PSR_STATE5; 74 else if (raw_state == 0x51) 75 state = PSR_STATE5a; 76 else if (raw_state == 0x52) 77 state = PSR_STATE5b; 78 else if (raw_state == 0x53) 79 state = PSR_STATE5c; 80 else if (raw_state == 0x4A) 81 state = PSR_STATE4_FULL_FRAME; 82 else if (raw_state == 0x4B) 83 state = PSR_STATE4a_FULL_FRAME; 84 else if (raw_state == 0x4C) 85 state = PSR_STATE4b_FULL_FRAME; 86 else if (raw_state == 0x4D) 87 state = PSR_STATE4c_FULL_FRAME; 88 else if (raw_state == 0x4E) 89 state = PSR_STATE4_FULL_FRAME_POWERUP; 90 else if (raw_state == 0x60) 91 state = PSR_STATE_HWLOCK_MGR; 92 else if (raw_state == 0x61) 93 state = PSR_STATE_POLLVUPDATE; 94 else 95 state = PSR_STATE_INVALID; 96 97 return state; 98 } 99 100 /* 101 * Get PSR state from firmware. 102 */ 103 static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state, uint8_t panel_inst) 104 { 105 struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub; 106 uint32_t raw_state = 0; 107 uint32_t retry_count = 0; 108 enum dmub_status status; 109 110 do { 111 // Send gpint command and wait for ack 112 status = dmub_srv_send_gpint_command(srv, DMUB_GPINT__GET_PSR_STATE, panel_inst, 30); 113 114 if (status == DMUB_STATUS_OK) { 115 // GPINT was executed, get response 116 dmub_srv_get_gpint_response(srv, &raw_state); 117 *state = convert_psr_state(raw_state); 118 } else 119 // Return invalid state when GPINT times out 120 *state = PSR_STATE_INVALID; 121 122 } while (++retry_count <= 1000 && *state == PSR_STATE_INVALID); 123 124 // Assert if max retry hit 125 if (retry_count >= 1000 && *state == PSR_STATE_INVALID) { 126 ASSERT(0); 127 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR, 128 WPP_BIT_FLAG_Firmware_PsrState, 129 "Unable to get PSR state from FW."); 130 } else 131 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_VERBOSE, 132 WPP_BIT_FLAG_Firmware_PsrState, 133 "Got PSR state from FW. PSR state: %d, Retry count: %d", 134 *state, retry_count); 135 } 136 137 /* 138 * Set PSR version. 139 */ 140 static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *stream, uint8_t panel_inst) 141 { 142 union dmub_rb_cmd cmd; 143 struct dc_context *dc = dmub->ctx; 144 145 if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED) 146 return false; 147 148 memset(&cmd, 0, sizeof(cmd)); 149 cmd.psr_set_version.header.type = DMUB_CMD__PSR; 150 cmd.psr_set_version.header.sub_type = DMUB_CMD__PSR_SET_VERSION; 151 switch (stream->link->psr_settings.psr_version) { 152 case DC_PSR_VERSION_1: 153 cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_1; 154 break; 155 case DC_PSR_VERSION_SU_1: 156 cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_SU_1; 157 break; 158 case DC_PSR_VERSION_UNSUPPORTED: 159 default: 160 cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_UNSUPPORTED; 161 break; 162 } 163 164 if (cmd.psr_set_version.psr_set_version_data.version == PSR_VERSION_UNSUPPORTED) 165 return false; 166 167 cmd.psr_set_version.psr_set_version_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; 168 cmd.psr_set_version.psr_set_version_data.panel_inst = panel_inst; 169 cmd.psr_set_version.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_version_data); 170 171 dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd); 172 dc_dmub_srv_cmd_execute(dc->dmub_srv); 173 dc_dmub_srv_wait_idle(dc->dmub_srv); 174 175 return true; 176 } 177 178 /* 179 * Enable/Disable PSR. 180 */ 181 static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait, uint8_t panel_inst) 182 { 183 union dmub_rb_cmd cmd; 184 struct dc_context *dc = dmub->ctx; 185 uint32_t retry_count; 186 enum dc_psr_state state = PSR_STATE0; 187 188 memset(&cmd, 0, sizeof(cmd)); 189 cmd.psr_enable.header.type = DMUB_CMD__PSR; 190 191 cmd.psr_enable.data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; 192 cmd.psr_enable.data.panel_inst = panel_inst; 193 194 if (enable) 195 cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_ENABLE; 196 else 197 cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_DISABLE; 198 199 cmd.psr_enable.header.payload_bytes = 0; // Send header only 200 201 dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd); 202 dc_dmub_srv_cmd_execute(dc->dmub_srv); 203 dc_dmub_srv_wait_idle(dc->dmub_srv); 204 205 /* Below loops 1000 x 500us = 500 ms. 206 * Exit PSR may need to wait 1-2 frames to power up. Timeout after at 207 * least a few frames. Should never hit the max retry assert below. 208 */ 209 if (wait) { 210 for (retry_count = 0; retry_count <= 1000; retry_count++) { 211 dmub_psr_get_state(dmub, &state, panel_inst); 212 213 if (enable) { 214 if (state != PSR_STATE0) 215 break; 216 } else { 217 if (state == PSR_STATE0) 218 break; 219 } 220 221 fsleep(500); 222 } 223 224 /* assert if max retry hit */ 225 if (retry_count >= 1000) 226 ASSERT(0); 227 } 228 } 229 230 /* 231 * Set PSR level. 232 */ 233 static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level, uint8_t panel_inst) 234 { 235 union dmub_rb_cmd cmd; 236 enum dc_psr_state state = PSR_STATE0; 237 struct dc_context *dc = dmub->ctx; 238 239 dmub_psr_get_state(dmub, &state, panel_inst); 240 241 if (state == PSR_STATE0) 242 return; 243 244 memset(&cmd, 0, sizeof(cmd)); 245 cmd.psr_set_level.header.type = DMUB_CMD__PSR; 246 cmd.psr_set_level.header.sub_type = DMUB_CMD__PSR_SET_LEVEL; 247 cmd.psr_set_level.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_level_data); 248 cmd.psr_set_level.psr_set_level_data.psr_level = psr_level; 249 cmd.psr_set_level.psr_set_level_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; 250 cmd.psr_set_level.psr_set_level_data.panel_inst = panel_inst; 251 dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd); 252 dc_dmub_srv_cmd_execute(dc->dmub_srv); 253 dc_dmub_srv_wait_idle(dc->dmub_srv); 254 } 255 256 /* 257 * Set PSR vtotal requirement for FreeSync PSR. 258 */ 259 static void dmub_psr_set_sink_vtotal_in_psr_active(struct dmub_psr *dmub, 260 uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su) 261 { 262 union dmub_rb_cmd cmd; 263 struct dc_context *dc = dmub->ctx; 264 265 memset(&cmd, 0, sizeof(cmd)); 266 cmd.psr_set_vtotal.header.type = DMUB_CMD__PSR; 267 cmd.psr_set_vtotal.header.sub_type = DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE; 268 cmd.psr_set_vtotal.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_vtotal_data); 269 cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_idle = psr_vtotal_idle; 270 cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_su = psr_vtotal_su; 271 272 dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd); 273 dc_dmub_srv_cmd_execute(dc->dmub_srv); 274 dc_dmub_srv_wait_idle(dc->dmub_srv); 275 } 276 277 /* 278 * Set PSR power optimization flags. 279 */ 280 static void dmub_psr_set_power_opt(struct dmub_psr *dmub, unsigned int power_opt, uint8_t panel_inst) 281 { 282 union dmub_rb_cmd cmd; 283 struct dc_context *dc = dmub->ctx; 284 285 memset(&cmd, 0, sizeof(cmd)); 286 cmd.psr_set_power_opt.header.type = DMUB_CMD__PSR; 287 cmd.psr_set_power_opt.header.sub_type = DMUB_CMD__SET_PSR_POWER_OPT; 288 cmd.psr_set_power_opt.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_power_opt_data); 289 cmd.psr_set_power_opt.psr_set_power_opt_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; 290 cmd.psr_set_power_opt.psr_set_power_opt_data.power_opt = power_opt; 291 cmd.psr_set_power_opt.psr_set_power_opt_data.panel_inst = panel_inst; 292 293 dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd); 294 dc_dmub_srv_cmd_execute(dc->dmub_srv); 295 dc_dmub_srv_wait_idle(dc->dmub_srv); 296 } 297 298 /* 299 * Setup PSR by programming phy registers and sending psr hw context values to firmware. 300 */ 301 static bool dmub_psr_copy_settings(struct dmub_psr *dmub, 302 struct dc_link *link, 303 struct psr_context *psr_context, 304 uint8_t panel_inst) 305 { 306 union dmub_rb_cmd cmd; 307 struct dc_context *dc = dmub->ctx; 308 struct dmub_cmd_psr_copy_settings_data *copy_settings_data 309 = &cmd.psr_copy_settings.psr_copy_settings_data; 310 struct pipe_ctx *pipe_ctx = NULL; 311 struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx; 312 int i = 0; 313 314 for (i = 0; i < MAX_PIPES; i++) { 315 if (res_ctx->pipe_ctx[i].stream && 316 res_ctx->pipe_ctx[i].stream->link == link && 317 res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) { 318 pipe_ctx = &res_ctx->pipe_ctx[i]; 319 //TODO: refactor for multi edp support 320 break; 321 } 322 } 323 324 if (!pipe_ctx) 325 return false; 326 327 // First, set the psr version 328 if (!dmub_psr_set_version(dmub, pipe_ctx->stream, panel_inst)) 329 return false; 330 331 // Program DP DPHY fast training registers 332 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 333 psr_context->psrExitLinkTrainingRequired); 334 335 // Program DP_SEC_CNTL1 register to set transmission GPS0 line num and priority to high 336 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 337 psr_context->sdpTransmitLineNumDeadline); 338 339 memset(&cmd, 0, sizeof(cmd)); 340 cmd.psr_copy_settings.header.type = DMUB_CMD__PSR; 341 cmd.psr_copy_settings.header.sub_type = DMUB_CMD__PSR_COPY_SETTINGS; 342 cmd.psr_copy_settings.header.payload_bytes = sizeof(struct dmub_cmd_psr_copy_settings_data); 343 344 // Hw insts 345 copy_settings_data->dpphy_inst = psr_context->transmitterId; 346 copy_settings_data->aux_inst = psr_context->channel; 347 copy_settings_data->digfe_inst = psr_context->engineId; 348 copy_settings_data->digbe_inst = psr_context->transmitterId; 349 350 copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst; 351 352 if (pipe_ctx->plane_res.dpp) 353 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; 354 else 355 copy_settings_data->dpp_inst = 0; 356 if (pipe_ctx->stream_res.opp) 357 copy_settings_data->opp_inst = pipe_ctx->stream_res.opp->inst; 358 else 359 copy_settings_data->opp_inst = 0; 360 if (pipe_ctx->stream_res.tg) 361 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; 362 else 363 copy_settings_data->otg_inst = 0; 364 365 // Misc 366 copy_settings_data->use_phy_fsm = link->ctx->dc->debug.psr_power_use_phy_fsm; 367 copy_settings_data->psr_level = psr_context->psr_level.u32all; 368 copy_settings_data->smu_optimizations_en = psr_context->allow_smu_optimizations; 369 copy_settings_data->multi_disp_optimizations_en = psr_context->allow_multi_disp_optimizations; 370 copy_settings_data->frame_delay = psr_context->frame_delay; 371 copy_settings_data->frame_cap_ind = psr_context->psrFrameCaptureIndicationReq; 372 copy_settings_data->init_sdp_deadline = psr_context->sdpTransmitLineNumDeadline; 373 copy_settings_data->debug.u32All = 0; 374 copy_settings_data->debug.bitfields.visual_confirm = dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR; 375 copy_settings_data->debug.bitfields.use_hw_lock_mgr = 1; 376 copy_settings_data->debug.bitfields.force_full_frame_update = 0; 377 378 if (psr_context->su_granularity_required == 0) 379 copy_settings_data->su_y_granularity = 0; 380 else 381 copy_settings_data->su_y_granularity = psr_context->su_y_granularity; 382 383 copy_settings_data->line_capture_indication = 0; 384 copy_settings_data->line_time_in_us = psr_context->line_time_in_us; 385 copy_settings_data->rate_control_caps = psr_context->rate_control_caps; 386 copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled); 387 copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us; 388 copy_settings_data->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; 389 copy_settings_data->panel_inst = panel_inst; 390 copy_settings_data->dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1); 391 392 /** 393 * WA for PSRSU+DSC on specific TCON, if DSC is enabled, force PSRSU as ffu mode(full frame update) 394 * Note that PSRSU+DSC is still under development. 395 */ 396 if (copy_settings_data->dsc_enable_status && 397 link->dpcd_caps.sink_dev_id == DP_DEVICE_ID_38EC11 && 398 !memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1, 399 sizeof(DP_SINK_DEVICE_STR_ID_1))) 400 link->psr_settings.force_ffu_mode = 1; 401 else 402 link->psr_settings.force_ffu_mode = 0; 403 copy_settings_data->force_ffu_mode = link->psr_settings.force_ffu_mode; 404 405 if (((link->dpcd_caps.fec_cap.bits.FEC_CAPABLE && 406 !link->dc->debug.disable_fec) && 407 (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT && 408 !link->panel_config.dsc.disable_dsc_edp && 409 link->dc->caps.edp_dsc_support)) && 410 link->dpcd_caps.sink_dev_id == DP_DEVICE_ID_38EC11 && 411 (!memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1, 412 sizeof(DP_SINK_DEVICE_STR_ID_1)) || 413 !memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_2, 414 sizeof(DP_SINK_DEVICE_STR_ID_2)))) 415 copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 1; 416 else 417 copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 0; 418 419 //WA for PSR1 on specific TCON, require frame delay for frame re-lock 420 copy_settings_data->relock_delay_frame_cnt = 0; 421 if (link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8) 422 copy_settings_data->relock_delay_frame_cnt = 2; 423 copy_settings_data->dsc_slice_height = psr_context->dsc_slice_height; 424 425 dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd); 426 dc_dmub_srv_cmd_execute(dc->dmub_srv); 427 dc_dmub_srv_wait_idle(dc->dmub_srv); 428 429 return true; 430 } 431 432 /* 433 * Send command to PSR to force static ENTER and ignore all state changes until exit 434 */ 435 static void dmub_psr_force_static(struct dmub_psr *dmub, uint8_t panel_inst) 436 { 437 union dmub_rb_cmd cmd; 438 struct dc_context *dc = dmub->ctx; 439 440 memset(&cmd, 0, sizeof(cmd)); 441 442 cmd.psr_force_static.psr_force_static_data.panel_inst = panel_inst; 443 cmd.psr_force_static.psr_force_static_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; 444 cmd.psr_force_static.header.type = DMUB_CMD__PSR; 445 cmd.psr_force_static.header.sub_type = DMUB_CMD__PSR_FORCE_STATIC; 446 cmd.psr_enable.header.payload_bytes = 0; 447 448 dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd); 449 dc_dmub_srv_cmd_execute(dc->dmub_srv); 450 dc_dmub_srv_wait_idle(dc->dmub_srv); 451 } 452 453 /* 454 * Get PSR residency from firmware. 455 */ 456 static void dmub_psr_get_residency(struct dmub_psr *dmub, uint32_t *residency, uint8_t panel_inst) 457 { 458 struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub; 459 uint16_t param = (uint16_t)(panel_inst << 8); 460 461 /* Send gpint command and wait for ack */ 462 dmub_srv_send_gpint_command(srv, DMUB_GPINT__PSR_RESIDENCY, param, 30); 463 464 dmub_srv_get_gpint_response(srv, residency); 465 } 466 467 static const struct dmub_psr_funcs psr_funcs = { 468 .psr_copy_settings = dmub_psr_copy_settings, 469 .psr_enable = dmub_psr_enable, 470 .psr_get_state = dmub_psr_get_state, 471 .psr_set_level = dmub_psr_set_level, 472 .psr_force_static = dmub_psr_force_static, 473 .psr_get_residency = dmub_psr_get_residency, 474 .psr_set_sink_vtotal_in_psr_active = dmub_psr_set_sink_vtotal_in_psr_active, 475 .psr_set_power_opt = dmub_psr_set_power_opt, 476 }; 477 478 /* 479 * Construct PSR object. 480 */ 481 static void dmub_psr_construct(struct dmub_psr *psr, struct dc_context *ctx) 482 { 483 psr->ctx = ctx; 484 psr->funcs = &psr_funcs; 485 } 486 487 /* 488 * Allocate and initialize PSR object. 489 */ 490 struct dmub_psr *dmub_psr_create(struct dc_context *ctx) 491 { 492 struct dmub_psr *psr = kzalloc(sizeof(struct dmub_psr), GFP_KERNEL); 493 494 if (psr == NULL) { 495 BREAK_TO_DEBUGGER(); 496 return NULL; 497 } 498 499 dmub_psr_construct(psr, ctx); 500 501 return psr; 502 } 503 504 /* 505 * Deallocate PSR object. 506 */ 507 void dmub_psr_destroy(struct dmub_psr **dmub) 508 { 509 kfree(*dmub); 510 *dmub = NULL; 511 } 512