1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dmub_psr.h" 27 #include "dc.h" 28 #include "dc_dmub_srv.h" 29 #include "dmub/dmub_srv.h" 30 #include "core_types.h" 31 32 #define MAX_PIPES 6 33 34 /* 35 * Convert dmcub psr state to dmcu psr state. 36 */ 37 static enum dc_psr_state convert_psr_state(uint32_t raw_state) 38 { 39 enum dc_psr_state state = PSR_STATE0; 40 41 if (raw_state == 0) 42 state = PSR_STATE0; 43 else if (raw_state == 0x10) 44 state = PSR_STATE1; 45 else if (raw_state == 0x11) 46 state = PSR_STATE1a; 47 else if (raw_state == 0x20) 48 state = PSR_STATE2; 49 else if (raw_state == 0x21) 50 state = PSR_STATE2a; 51 else if (raw_state == 0x30) 52 state = PSR_STATE3; 53 else if (raw_state == 0x31) 54 state = PSR_STATE3Init; 55 else if (raw_state == 0x40) 56 state = PSR_STATE4; 57 else if (raw_state == 0x41) 58 state = PSR_STATE4a; 59 else if (raw_state == 0x42) 60 state = PSR_STATE4b; 61 else if (raw_state == 0x43) 62 state = PSR_STATE4c; 63 else if (raw_state == 0x44) 64 state = PSR_STATE4d; 65 else if (raw_state == 0x50) 66 state = PSR_STATE5; 67 else if (raw_state == 0x51) 68 state = PSR_STATE5a; 69 else if (raw_state == 0x52) 70 state = PSR_STATE5b; 71 else if (raw_state == 0x53) 72 state = PSR_STATE5c; 73 74 return state; 75 } 76 77 /* 78 * Get PSR state from firmware. 79 */ 80 static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state) 81 { 82 struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub; 83 uint32_t raw_state; 84 enum dmub_status status; 85 86 // Send gpint command and wait for ack 87 status = dmub_srv_send_gpint_command(srv, DMUB_GPINT__GET_PSR_STATE, 0, 30); 88 89 if (status == DMUB_STATUS_OK) { 90 // GPINT was executed, get response 91 dmub_srv_get_gpint_response(srv, &raw_state); 92 *state = convert_psr_state(raw_state); 93 } else 94 // Return invalid state when GPINT times out 95 *state = 0xFF; 96 } 97 98 /* 99 * Set PSR version. 100 */ 101 static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *stream) 102 { 103 union dmub_rb_cmd cmd; 104 struct dc_context *dc = dmub->ctx; 105 106 if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED) 107 return false; 108 109 memset(&cmd, 0, sizeof(cmd)); 110 cmd.psr_set_version.header.type = DMUB_CMD__PSR; 111 cmd.psr_set_version.header.sub_type = DMUB_CMD__PSR_SET_VERSION; 112 switch (stream->link->psr_settings.psr_version) { 113 case DC_PSR_VERSION_1: 114 cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_1; 115 break; 116 case DC_PSR_VERSION_UNSUPPORTED: 117 default: 118 cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_UNSUPPORTED; 119 break; 120 } 121 cmd.psr_set_version.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_version_data); 122 123 dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd); 124 dc_dmub_srv_cmd_execute(dc->dmub_srv); 125 dc_dmub_srv_wait_idle(dc->dmub_srv); 126 127 return true; 128 } 129 130 /* 131 * Enable/Disable PSR. 132 */ 133 static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait) 134 { 135 union dmub_rb_cmd cmd; 136 struct dc_context *dc = dmub->ctx; 137 uint32_t retry_count; 138 enum dc_psr_state state = PSR_STATE0; 139 140 memset(&cmd, 0, sizeof(cmd)); 141 cmd.psr_enable.header.type = DMUB_CMD__PSR; 142 143 if (enable) 144 cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_ENABLE; 145 else 146 cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_DISABLE; 147 148 cmd.psr_enable.header.payload_bytes = 0; // Send header only 149 150 dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd); 151 dc_dmub_srv_cmd_execute(dc->dmub_srv); 152 dc_dmub_srv_wait_idle(dc->dmub_srv); 153 154 /* Below loops 1000 x 500us = 500 ms. 155 * Exit PSR may need to wait 1-2 frames to power up. Timeout after at 156 * least a few frames. Should never hit the max retry assert below. 157 */ 158 if (wait) { 159 for (retry_count = 0; retry_count <= 1000; retry_count++) { 160 dmub_psr_get_state(dmub, &state); 161 162 if (enable) { 163 if (state != PSR_STATE0) 164 break; 165 } else { 166 if (state == PSR_STATE0) 167 break; 168 } 169 170 udelay(500); 171 } 172 173 /* assert if max retry hit */ 174 if (retry_count >= 1000) 175 ASSERT(0); 176 } 177 } 178 179 /* 180 * Set PSR level. 181 */ 182 static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level) 183 { 184 union dmub_rb_cmd cmd; 185 enum dc_psr_state state = PSR_STATE0; 186 struct dc_context *dc = dmub->ctx; 187 188 dmub_psr_get_state(dmub, &state); 189 190 if (state == PSR_STATE0) 191 return; 192 193 memset(&cmd, 0, sizeof(cmd)); 194 cmd.psr_set_level.header.type = DMUB_CMD__PSR; 195 cmd.psr_set_level.header.sub_type = DMUB_CMD__PSR_SET_LEVEL; 196 cmd.psr_set_level.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_level_data); 197 cmd.psr_set_level.psr_set_level_data.psr_level = psr_level; 198 199 dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd); 200 dc_dmub_srv_cmd_execute(dc->dmub_srv); 201 dc_dmub_srv_wait_idle(dc->dmub_srv); 202 } 203 204 /* 205 * Setup PSR by programming phy registers and sending psr hw context values to firmware. 206 */ 207 static bool dmub_psr_copy_settings(struct dmub_psr *dmub, 208 struct dc_link *link, 209 struct psr_context *psr_context) 210 { 211 union dmub_rb_cmd cmd; 212 struct dc_context *dc = dmub->ctx; 213 struct dmub_cmd_psr_copy_settings_data *copy_settings_data 214 = &cmd.psr_copy_settings.psr_copy_settings_data; 215 struct pipe_ctx *pipe_ctx = NULL; 216 struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx; 217 int i = 0; 218 219 for (i = 0; i < MAX_PIPES; i++) { 220 if (res_ctx->pipe_ctx[i].stream && 221 res_ctx->pipe_ctx[i].stream->link == link && 222 res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) { 223 pipe_ctx = &res_ctx->pipe_ctx[i]; 224 //TODO: refactor for multi edp support 225 break; 226 } 227 } 228 229 if (!pipe_ctx) 230 return false; 231 232 // First, set the psr version 233 if (!dmub_psr_set_version(dmub, pipe_ctx->stream)) 234 return false; 235 236 // Program DP DPHY fast training registers 237 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 238 psr_context->psrExitLinkTrainingRequired); 239 240 // Program DP_SEC_CNTL1 register to set transmission GPS0 line num and priority to high 241 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 242 psr_context->sdpTransmitLineNumDeadline); 243 244 memset(&cmd, 0, sizeof(cmd)); 245 cmd.psr_copy_settings.header.type = DMUB_CMD__PSR; 246 cmd.psr_copy_settings.header.sub_type = DMUB_CMD__PSR_COPY_SETTINGS; 247 cmd.psr_copy_settings.header.payload_bytes = sizeof(struct dmub_cmd_psr_copy_settings_data); 248 249 // Hw insts 250 copy_settings_data->dpphy_inst = psr_context->transmitterId; 251 copy_settings_data->aux_inst = psr_context->channel; 252 copy_settings_data->digfe_inst = psr_context->engineId; 253 copy_settings_data->digbe_inst = psr_context->transmitterId; 254 255 copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst; 256 257 if (pipe_ctx->plane_res.dpp) 258 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; 259 else 260 copy_settings_data->dpp_inst = 0; 261 if (pipe_ctx->stream_res.opp) 262 copy_settings_data->opp_inst = pipe_ctx->stream_res.opp->inst; 263 else 264 copy_settings_data->opp_inst = 0; 265 if (pipe_ctx->stream_res.tg) 266 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; 267 else 268 copy_settings_data->otg_inst = 0; 269 270 // Misc 271 copy_settings_data->psr_level = psr_context->psr_level.u32all; 272 copy_settings_data->smu_optimizations_en = psr_context->allow_smu_optimizations; 273 copy_settings_data->multi_disp_optimizations_en = psr_context->allow_multi_disp_optimizations; 274 copy_settings_data->frame_delay = psr_context->frame_delay; 275 copy_settings_data->frame_cap_ind = psr_context->psrFrameCaptureIndicationReq; 276 copy_settings_data->init_sdp_deadline = psr_context->sdpTransmitLineNumDeadline; 277 copy_settings_data->debug.u32All = 0; 278 copy_settings_data->debug.bitfields.visual_confirm = dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR; 279 copy_settings_data->debug.bitfields.use_hw_lock_mgr = 1; 280 281 dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd); 282 dc_dmub_srv_cmd_execute(dc->dmub_srv); 283 dc_dmub_srv_wait_idle(dc->dmub_srv); 284 285 return true; 286 } 287 288 /* 289 * Send command to PSR to force static ENTER and ignore all state changes until exit 290 */ 291 static void dmub_psr_force_static(struct dmub_psr *dmub) 292 { 293 union dmub_rb_cmd cmd; 294 struct dc_context *dc = dmub->ctx; 295 296 memset(&cmd, 0, sizeof(cmd)); 297 cmd.psr_force_static.header.type = DMUB_CMD__PSR; 298 cmd.psr_force_static.header.sub_type = DMUB_CMD__PSR_FORCE_STATIC; 299 cmd.psr_enable.header.payload_bytes = 0; 300 301 dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd); 302 dc_dmub_srv_cmd_execute(dc->dmub_srv); 303 dc_dmub_srv_wait_idle(dc->dmub_srv); 304 } 305 306 /* 307 * Get PSR residency from firmware. 308 */ 309 static void dmub_psr_get_residency(struct dmub_psr *dmub, uint32_t *residency) 310 { 311 struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub; 312 313 // Send gpint command and wait for ack 314 dmub_srv_send_gpint_command(srv, DMUB_GPINT__PSR_RESIDENCY, 0, 30); 315 316 dmub_srv_get_gpint_response(srv, residency); 317 } 318 319 static const struct dmub_psr_funcs psr_funcs = { 320 .psr_copy_settings = dmub_psr_copy_settings, 321 .psr_enable = dmub_psr_enable, 322 .psr_get_state = dmub_psr_get_state, 323 .psr_set_level = dmub_psr_set_level, 324 .psr_force_static = dmub_psr_force_static, 325 .psr_get_residency = dmub_psr_get_residency, 326 }; 327 328 /* 329 * Construct PSR object. 330 */ 331 static void dmub_psr_construct(struct dmub_psr *psr, struct dc_context *ctx) 332 { 333 psr->ctx = ctx; 334 psr->funcs = &psr_funcs; 335 } 336 337 /* 338 * Allocate and initialize PSR object. 339 */ 340 struct dmub_psr *dmub_psr_create(struct dc_context *ctx) 341 { 342 struct dmub_psr *psr = kzalloc(sizeof(struct dmub_psr), GFP_KERNEL); 343 344 if (psr == NULL) { 345 BREAK_TO_DEBUGGER(); 346 return NULL; 347 } 348 349 dmub_psr_construct(psr, ctx); 350 351 return psr; 352 } 353 354 /* 355 * Deallocate PSR object. 356 */ 357 void dmub_psr_destroy(struct dmub_psr **dmub) 358 { 359 kfree(*dmub); 360 *dmub = NULL; 361 } 362