1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dmub_psr.h" 27 #include "dc.h" 28 #include "dc_dmub_srv.h" 29 #include "dmub/dmub_srv.h" 30 #include "core_types.h" 31 32 #define DC_TRACE_LEVEL_MESSAGE(...) do {} while (0) /* do nothing */ 33 34 #define MAX_PIPES 6 35 36 static const uint8_t DP_SINK_DEVICE_STR_ID_1[] = {7, 1, 8, 7, 3}; 37 static const uint8_t DP_SINK_DEVICE_STR_ID_2[] = {7, 1, 8, 7, 5}; 38 39 /* 40 * Convert dmcub psr state to dmcu psr state. 41 */ 42 static enum dc_psr_state convert_psr_state(uint32_t raw_state) 43 { 44 enum dc_psr_state state = PSR_STATE0; 45 46 if (raw_state == 0) 47 state = PSR_STATE0; 48 else if (raw_state == 0x10) 49 state = PSR_STATE1; 50 else if (raw_state == 0x11) 51 state = PSR_STATE1a; 52 else if (raw_state == 0x20) 53 state = PSR_STATE2; 54 else if (raw_state == 0x21) 55 state = PSR_STATE2a; 56 else if (raw_state == 0x22) 57 state = PSR_STATE2b; 58 else if (raw_state == 0x30) 59 state = PSR_STATE3; 60 else if (raw_state == 0x31) 61 state = PSR_STATE3Init; 62 else if (raw_state == 0x40) 63 state = PSR_STATE4; 64 else if (raw_state == 0x41) 65 state = PSR_STATE4a; 66 else if (raw_state == 0x42) 67 state = PSR_STATE4b; 68 else if (raw_state == 0x43) 69 state = PSR_STATE4c; 70 else if (raw_state == 0x44) 71 state = PSR_STATE4d; 72 else if (raw_state == 0x50) 73 state = PSR_STATE5; 74 else if (raw_state == 0x51) 75 state = PSR_STATE5a; 76 else if (raw_state == 0x52) 77 state = PSR_STATE5b; 78 else if (raw_state == 0x53) 79 state = PSR_STATE5c; 80 else if (raw_state == 0x4A) 81 state = PSR_STATE4_FULL_FRAME; 82 else if (raw_state == 0x4B) 83 state = PSR_STATE4a_FULL_FRAME; 84 else if (raw_state == 0x4C) 85 state = PSR_STATE4b_FULL_FRAME; 86 else if (raw_state == 0x4D) 87 state = PSR_STATE4c_FULL_FRAME; 88 else if (raw_state == 0x4E) 89 state = PSR_STATE4_FULL_FRAME_POWERUP; 90 else if (raw_state == 0x60) 91 state = PSR_STATE_HWLOCK_MGR; 92 else if (raw_state == 0x61) 93 state = PSR_STATE_POLLVUPDATE; 94 else 95 state = PSR_STATE_INVALID; 96 97 return state; 98 } 99 100 /* 101 * Get PSR state from firmware. 102 */ 103 static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state, uint8_t panel_inst) 104 { 105 struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub; 106 uint32_t raw_state = 0; 107 uint32_t retry_count = 0; 108 enum dmub_status status; 109 110 do { 111 // Send gpint command and wait for ack 112 status = dmub_srv_send_gpint_command(srv, DMUB_GPINT__GET_PSR_STATE, panel_inst, 30); 113 114 if (status == DMUB_STATUS_OK) { 115 // GPINT was executed, get response 116 dmub_srv_get_gpint_response(srv, &raw_state); 117 *state = convert_psr_state(raw_state); 118 } else 119 // Return invalid state when GPINT times out 120 *state = PSR_STATE_INVALID; 121 122 } while (++retry_count <= 1000 && *state == PSR_STATE_INVALID); 123 124 // Assert if max retry hit 125 if (retry_count >= 1000 && *state == PSR_STATE_INVALID) { 126 ASSERT(0); 127 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR, 128 WPP_BIT_FLAG_Firmware_PsrState, 129 "Unable to get PSR state from FW."); 130 } else 131 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_VERBOSE, 132 WPP_BIT_FLAG_Firmware_PsrState, 133 "Got PSR state from FW. PSR state: %d, Retry count: %d", 134 *state, retry_count); 135 } 136 137 /* 138 * Set PSR version. 139 */ 140 static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *stream, uint8_t panel_inst) 141 { 142 union dmub_rb_cmd cmd; 143 struct dc_context *dc = dmub->ctx; 144 145 if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED) 146 return false; 147 148 memset(&cmd, 0, sizeof(cmd)); 149 cmd.psr_set_version.header.type = DMUB_CMD__PSR; 150 cmd.psr_set_version.header.sub_type = DMUB_CMD__PSR_SET_VERSION; 151 switch (stream->link->psr_settings.psr_version) { 152 case DC_PSR_VERSION_1: 153 cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_1; 154 break; 155 case DC_PSR_VERSION_SU_1: 156 cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_SU_1; 157 break; 158 case DC_PSR_VERSION_UNSUPPORTED: 159 default: 160 cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_UNSUPPORTED; 161 break; 162 } 163 164 if (cmd.psr_set_version.psr_set_version_data.version == PSR_VERSION_UNSUPPORTED) 165 return false; 166 167 cmd.psr_set_version.psr_set_version_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; 168 cmd.psr_set_version.psr_set_version_data.panel_inst = panel_inst; 169 cmd.psr_set_version.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_version_data); 170 171 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 172 173 return true; 174 } 175 176 /* 177 * Enable/Disable PSR. 178 */ 179 static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait, uint8_t panel_inst) 180 { 181 union dmub_rb_cmd cmd; 182 struct dc_context *dc = dmub->ctx; 183 uint32_t retry_count; 184 enum dc_psr_state state = PSR_STATE0; 185 186 memset(&cmd, 0, sizeof(cmd)); 187 cmd.psr_enable.header.type = DMUB_CMD__PSR; 188 189 cmd.psr_enable.data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; 190 cmd.psr_enable.data.panel_inst = panel_inst; 191 192 if (enable) 193 cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_ENABLE; 194 else 195 cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_DISABLE; 196 197 cmd.psr_enable.header.payload_bytes = 0; // Send header only 198 199 dm_execute_dmub_cmd(dc->dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 200 201 /* Below loops 1000 x 500us = 500 ms. 202 * Exit PSR may need to wait 1-2 frames to power up. Timeout after at 203 * least a few frames. Should never hit the max retry assert below. 204 */ 205 if (wait) { 206 for (retry_count = 0; retry_count <= 1000; retry_count++) { 207 dmub_psr_get_state(dmub, &state, panel_inst); 208 209 if (enable) { 210 if (state != PSR_STATE0) 211 break; 212 } else { 213 if (state == PSR_STATE0) 214 break; 215 } 216 217 fsleep(500); 218 } 219 220 /* assert if max retry hit */ 221 if (retry_count >= 1000) 222 ASSERT(0); 223 } 224 } 225 226 /* 227 * Set PSR level. 228 */ 229 static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level, uint8_t panel_inst) 230 { 231 union dmub_rb_cmd cmd; 232 enum dc_psr_state state = PSR_STATE0; 233 struct dc_context *dc = dmub->ctx; 234 235 dmub_psr_get_state(dmub, &state, panel_inst); 236 237 if (state == PSR_STATE0) 238 return; 239 240 memset(&cmd, 0, sizeof(cmd)); 241 cmd.psr_set_level.header.type = DMUB_CMD__PSR; 242 cmd.psr_set_level.header.sub_type = DMUB_CMD__PSR_SET_LEVEL; 243 cmd.psr_set_level.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_level_data); 244 cmd.psr_set_level.psr_set_level_data.psr_level = psr_level; 245 cmd.psr_set_level.psr_set_level_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; 246 cmd.psr_set_level.psr_set_level_data.panel_inst = panel_inst; 247 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 248 } 249 250 /* 251 * Set PSR vtotal requirement for FreeSync PSR. 252 */ 253 static void dmub_psr_set_sink_vtotal_in_psr_active(struct dmub_psr *dmub, 254 uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su) 255 { 256 union dmub_rb_cmd cmd; 257 struct dc_context *dc = dmub->ctx; 258 259 memset(&cmd, 0, sizeof(cmd)); 260 cmd.psr_set_vtotal.header.type = DMUB_CMD__PSR; 261 cmd.psr_set_vtotal.header.sub_type = DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE; 262 cmd.psr_set_vtotal.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_vtotal_data); 263 cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_idle = psr_vtotal_idle; 264 cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_su = psr_vtotal_su; 265 266 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 267 } 268 269 /* 270 * Set PSR power optimization flags. 271 */ 272 static void dmub_psr_set_power_opt(struct dmub_psr *dmub, unsigned int power_opt, uint8_t panel_inst) 273 { 274 union dmub_rb_cmd cmd; 275 struct dc_context *dc = dmub->ctx; 276 277 memset(&cmd, 0, sizeof(cmd)); 278 cmd.psr_set_power_opt.header.type = DMUB_CMD__PSR; 279 cmd.psr_set_power_opt.header.sub_type = DMUB_CMD__SET_PSR_POWER_OPT; 280 cmd.psr_set_power_opt.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_power_opt_data); 281 cmd.psr_set_power_opt.psr_set_power_opt_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; 282 cmd.psr_set_power_opt.psr_set_power_opt_data.power_opt = power_opt; 283 cmd.psr_set_power_opt.psr_set_power_opt_data.panel_inst = panel_inst; 284 285 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 286 } 287 288 /* 289 * Setup PSR by programming phy registers and sending psr hw context values to firmware. 290 */ 291 static bool dmub_psr_copy_settings(struct dmub_psr *dmub, 292 struct dc_link *link, 293 struct psr_context *psr_context, 294 uint8_t panel_inst) 295 { 296 union dmub_rb_cmd cmd; 297 struct dc_context *dc = dmub->ctx; 298 struct dmub_cmd_psr_copy_settings_data *copy_settings_data 299 = &cmd.psr_copy_settings.psr_copy_settings_data; 300 struct pipe_ctx *pipe_ctx = NULL; 301 struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx; 302 int i = 0; 303 304 for (i = 0; i < MAX_PIPES; i++) { 305 if (res_ctx->pipe_ctx[i].stream && 306 res_ctx->pipe_ctx[i].stream->link == link && 307 res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) { 308 pipe_ctx = &res_ctx->pipe_ctx[i]; 309 //TODO: refactor for multi edp support 310 break; 311 } 312 } 313 314 if (!pipe_ctx) 315 return false; 316 317 // First, set the psr version 318 if (!dmub_psr_set_version(dmub, pipe_ctx->stream, panel_inst)) 319 return false; 320 321 // Program DP DPHY fast training registers 322 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 323 psr_context->psrExitLinkTrainingRequired); 324 325 // Program DP_SEC_CNTL1 register to set transmission GPS0 line num and priority to high 326 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 327 psr_context->sdpTransmitLineNumDeadline); 328 329 memset(&cmd, 0, sizeof(cmd)); 330 cmd.psr_copy_settings.header.type = DMUB_CMD__PSR; 331 cmd.psr_copy_settings.header.sub_type = DMUB_CMD__PSR_COPY_SETTINGS; 332 cmd.psr_copy_settings.header.payload_bytes = sizeof(struct dmub_cmd_psr_copy_settings_data); 333 334 // Hw insts 335 copy_settings_data->dpphy_inst = psr_context->transmitterId; 336 copy_settings_data->aux_inst = psr_context->channel; 337 copy_settings_data->digfe_inst = psr_context->engineId; 338 copy_settings_data->digbe_inst = psr_context->transmitterId; 339 340 copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst; 341 342 if (pipe_ctx->plane_res.dpp) 343 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; 344 else 345 copy_settings_data->dpp_inst = 0; 346 if (pipe_ctx->stream_res.opp) 347 copy_settings_data->opp_inst = pipe_ctx->stream_res.opp->inst; 348 else 349 copy_settings_data->opp_inst = 0; 350 if (pipe_ctx->stream_res.tg) 351 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; 352 else 353 copy_settings_data->otg_inst = 0; 354 355 // Misc 356 copy_settings_data->use_phy_fsm = link->ctx->dc->debug.psr_power_use_phy_fsm; 357 copy_settings_data->psr_level = psr_context->psr_level.u32all; 358 copy_settings_data->smu_optimizations_en = psr_context->allow_smu_optimizations; 359 copy_settings_data->multi_disp_optimizations_en = psr_context->allow_multi_disp_optimizations; 360 copy_settings_data->frame_delay = psr_context->frame_delay; 361 copy_settings_data->frame_cap_ind = psr_context->psrFrameCaptureIndicationReq; 362 copy_settings_data->init_sdp_deadline = psr_context->sdpTransmitLineNumDeadline; 363 copy_settings_data->debug.u32All = 0; 364 copy_settings_data->debug.bitfields.visual_confirm = dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR; 365 copy_settings_data->debug.bitfields.use_hw_lock_mgr = 1; 366 copy_settings_data->debug.bitfields.force_full_frame_update = 0; 367 368 if (psr_context->su_granularity_required == 0) 369 copy_settings_data->su_y_granularity = 0; 370 else 371 copy_settings_data->su_y_granularity = psr_context->su_y_granularity; 372 373 copy_settings_data->line_capture_indication = 0; 374 copy_settings_data->line_time_in_us = psr_context->line_time_in_us; 375 copy_settings_data->rate_control_caps = psr_context->rate_control_caps; 376 copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled); 377 copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us; 378 copy_settings_data->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; 379 copy_settings_data->panel_inst = panel_inst; 380 copy_settings_data->dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1); 381 382 /** 383 * WA for PSRSU+DSC on specific TCON, if DSC is enabled, force PSRSU as ffu mode(full frame update) 384 * Note that PSRSU+DSC is still under development. 385 */ 386 if (copy_settings_data->dsc_enable_status && 387 link->dpcd_caps.sink_dev_id == DP_DEVICE_ID_38EC11 && 388 !memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1, 389 sizeof(DP_SINK_DEVICE_STR_ID_1))) 390 link->psr_settings.force_ffu_mode = 1; 391 else 392 link->psr_settings.force_ffu_mode = 0; 393 copy_settings_data->force_ffu_mode = link->psr_settings.force_ffu_mode; 394 395 if (((link->dpcd_caps.fec_cap.bits.FEC_CAPABLE && 396 !link->dc->debug.disable_fec) && 397 (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT && 398 !link->panel_config.dsc.disable_dsc_edp && 399 link->dc->caps.edp_dsc_support)) && 400 link->dpcd_caps.sink_dev_id == DP_DEVICE_ID_38EC11 && 401 (!memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1, 402 sizeof(DP_SINK_DEVICE_STR_ID_1)) || 403 !memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_2, 404 sizeof(DP_SINK_DEVICE_STR_ID_2)))) 405 copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 1; 406 else 407 copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 0; 408 409 //WA for PSR1 on specific TCON, require frame delay for frame re-lock 410 copy_settings_data->relock_delay_frame_cnt = 0; 411 if (link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8) 412 copy_settings_data->relock_delay_frame_cnt = 2; 413 copy_settings_data->dsc_slice_height = psr_context->dsc_slice_height; 414 415 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 416 417 return true; 418 } 419 420 /* 421 * Send command to PSR to force static ENTER and ignore all state changes until exit 422 */ 423 static void dmub_psr_force_static(struct dmub_psr *dmub, uint8_t panel_inst) 424 { 425 union dmub_rb_cmd cmd; 426 struct dc_context *dc = dmub->ctx; 427 428 memset(&cmd, 0, sizeof(cmd)); 429 430 cmd.psr_force_static.psr_force_static_data.panel_inst = panel_inst; 431 cmd.psr_force_static.psr_force_static_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; 432 cmd.psr_force_static.header.type = DMUB_CMD__PSR; 433 cmd.psr_force_static.header.sub_type = DMUB_CMD__PSR_FORCE_STATIC; 434 cmd.psr_enable.header.payload_bytes = 0; 435 436 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 437 } 438 439 /* 440 * Get PSR residency from firmware. 441 */ 442 static void dmub_psr_get_residency(struct dmub_psr *dmub, uint32_t *residency, uint8_t panel_inst) 443 { 444 struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub; 445 uint16_t param = (uint16_t)(panel_inst << 8); 446 447 /* Send gpint command and wait for ack */ 448 dmub_srv_send_gpint_command(srv, DMUB_GPINT__PSR_RESIDENCY, param, 30); 449 450 dmub_srv_get_gpint_response(srv, residency); 451 } 452 453 static const struct dmub_psr_funcs psr_funcs = { 454 .psr_copy_settings = dmub_psr_copy_settings, 455 .psr_enable = dmub_psr_enable, 456 .psr_get_state = dmub_psr_get_state, 457 .psr_set_level = dmub_psr_set_level, 458 .psr_force_static = dmub_psr_force_static, 459 .psr_get_residency = dmub_psr_get_residency, 460 .psr_set_sink_vtotal_in_psr_active = dmub_psr_set_sink_vtotal_in_psr_active, 461 .psr_set_power_opt = dmub_psr_set_power_opt, 462 }; 463 464 /* 465 * Construct PSR object. 466 */ 467 static void dmub_psr_construct(struct dmub_psr *psr, struct dc_context *ctx) 468 { 469 psr->ctx = ctx; 470 psr->funcs = &psr_funcs; 471 } 472 473 /* 474 * Allocate and initialize PSR object. 475 */ 476 struct dmub_psr *dmub_psr_create(struct dc_context *ctx) 477 { 478 struct dmub_psr *psr = kzalloc(sizeof(struct dmub_psr), GFP_KERNEL); 479 480 if (psr == NULL) { 481 BREAK_TO_DEBUGGER(); 482 return NULL; 483 } 484 485 dmub_psr_construct(psr, ctx); 486 487 return psr; 488 } 489 490 /* 491 * Deallocate PSR object. 492 */ 493 void dmub_psr_destroy(struct dmub_psr **dmub) 494 { 495 kfree(*dmub); 496 *dmub = NULL; 497 } 498