1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dmub_psr.h" 27 #include "dc.h" 28 #include "dc_dmub_srv.h" 29 #include "../../dmub/inc/dmub_srv.h" 30 #include "../../dmub/inc/dmub_gpint_cmd.h" 31 #include "core_types.h" 32 33 #define MAX_PIPES 6 34 35 /** 36 * Get PSR state from firmware. 37 */ 38 static void dmub_psr_get_state(struct dmub_psr *dmub, uint32_t *psr_state) 39 { 40 struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub; 41 42 // Send gpint command and wait for ack 43 dmub_srv_send_gpint_command(srv, DMUB_GPINT__GET_PSR_STATE, 0, 30); 44 45 dmub_srv_get_gpint_response(srv, psr_state); 46 } 47 48 /** 49 * Set PSR version. 50 */ 51 static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *stream) 52 { 53 union dmub_rb_cmd cmd; 54 struct dc_context *dc = dmub->ctx; 55 56 cmd.psr_set_version.header.type = DMUB_CMD__PSR; 57 cmd.psr_set_version.header.sub_type = DMUB_CMD__PSR_SET_VERSION; 58 59 if (stream->psr_version == 0x0) // Unsupported 60 return false; 61 else if (stream->psr_version == 0x1) 62 cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_1; 63 else if (stream->psr_version == 0x2) 64 cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_2; 65 66 cmd.psr_enable.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_version_data); 67 68 dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd.psr_enable.header); 69 dc_dmub_srv_cmd_execute(dc->dmub_srv); 70 dc_dmub_srv_wait_idle(dc->dmub_srv); 71 72 return true; 73 } 74 75 /** 76 * Enable/Disable PSR. 77 */ 78 static void dmub_psr_enable(struct dmub_psr *dmub, bool enable) 79 { 80 union dmub_rb_cmd cmd; 81 struct dc_context *dc = dmub->ctx; 82 83 cmd.psr_enable.header.type = DMUB_CMD__PSR; 84 85 if (enable) 86 cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_ENABLE; 87 else 88 cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_DISABLE; 89 90 cmd.psr_enable.header.payload_bytes = 0; // Send header only 91 92 dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd.psr_enable.header); 93 dc_dmub_srv_cmd_execute(dc->dmub_srv); 94 dc_dmub_srv_wait_idle(dc->dmub_srv); 95 } 96 97 /** 98 * Set PSR level. 99 */ 100 static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level) 101 { 102 union dmub_rb_cmd cmd; 103 uint32_t psr_state = 0; 104 struct dc_context *dc = dmub->ctx; 105 106 dmub_psr_get_state(dmub, &psr_state); 107 108 if (psr_state == 0) 109 return; 110 111 cmd.psr_set_level.header.type = DMUB_CMD__PSR; 112 cmd.psr_set_level.header.sub_type = DMUB_CMD__PSR_SET_LEVEL; 113 cmd.psr_set_level.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_level_data); 114 cmd.psr_set_level.psr_set_level_data.psr_level = psr_level; 115 116 dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd.psr_set_level.header); 117 dc_dmub_srv_cmd_execute(dc->dmub_srv); 118 dc_dmub_srv_wait_idle(dc->dmub_srv); 119 } 120 121 /** 122 * Setup PSR by programming phy registers and sending psr hw context values to firmware. 123 */ 124 static bool dmub_psr_copy_settings(struct dmub_psr *dmub, 125 struct dc_link *link, 126 struct psr_context *psr_context) 127 { 128 union dmub_rb_cmd cmd; 129 struct dc_context *dc = dmub->ctx; 130 struct dmub_cmd_psr_copy_settings_data *copy_settings_data 131 = &cmd.psr_copy_settings.psr_copy_settings_data; 132 struct pipe_ctx *pipe_ctx = NULL; 133 struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx; 134 int i = 0; 135 136 for (i = 0; i < MAX_PIPES; i++) { 137 if (res_ctx && 138 res_ctx->pipe_ctx[i].stream && 139 res_ctx->pipe_ctx[i].stream->link && 140 res_ctx->pipe_ctx[i].stream->link == link && 141 res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) { 142 pipe_ctx = &res_ctx->pipe_ctx[i]; 143 break; 144 } 145 } 146 147 if (!pipe_ctx) 148 return false; 149 150 // First, set the psr version 151 if (!dmub_psr_set_version(dmub, pipe_ctx->stream)) 152 return false; 153 154 // Program DP DPHY fast training registers 155 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 156 psr_context->psrExitLinkTrainingRequired); 157 158 // Program DP_SEC_CNTL1 register to set transmission GPS0 line num and priority to high 159 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 160 psr_context->sdpTransmitLineNumDeadline); 161 162 cmd.psr_copy_settings.header.type = DMUB_CMD__PSR; 163 cmd.psr_copy_settings.header.sub_type = DMUB_CMD__PSR_COPY_SETTINGS; 164 cmd.psr_copy_settings.header.payload_bytes = sizeof(struct dmub_cmd_psr_copy_settings_data); 165 166 // Hw insts 167 copy_settings_data->dpphy_inst = psr_context->phyType; 168 copy_settings_data->aux_inst = psr_context->channel; 169 copy_settings_data->digfe_inst = psr_context->engineId; 170 copy_settings_data->digbe_inst = psr_context->transmitterId; 171 172 copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst; 173 174 if (pipe_ctx->plane_res.dpp) 175 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; 176 else 177 copy_settings_data->dpp_inst = 0; 178 if (pipe_ctx->stream_res.opp) 179 copy_settings_data->opp_inst = pipe_ctx->stream_res.opp->inst; 180 else 181 copy_settings_data->opp_inst = 0; 182 if (pipe_ctx->stream_res.tg) 183 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; 184 else 185 copy_settings_data->otg_inst = 0; 186 187 // Misc 188 copy_settings_data->psr_level = psr_context->psr_level.u32all; 189 copy_settings_data->smu_optimizations_en = psr_context->allow_smu_optimizations; 190 copy_settings_data->frame_delay = psr_context->frame_delay; 191 copy_settings_data->frame_cap_ind = psr_context->psrFrameCaptureIndicationReq; 192 193 dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd.psr_copy_settings.header); 194 dc_dmub_srv_cmd_execute(dc->dmub_srv); 195 dc_dmub_srv_wait_idle(dc->dmub_srv); 196 197 return true; 198 } 199 200 static const struct dmub_psr_funcs psr_funcs = { 201 .psr_copy_settings = dmub_psr_copy_settings, 202 .psr_enable = dmub_psr_enable, 203 .psr_get_state = dmub_psr_get_state, 204 .psr_set_level = dmub_psr_set_level, 205 }; 206 207 /** 208 * Construct PSR object. 209 */ 210 static void dmub_psr_construct(struct dmub_psr *psr, struct dc_context *ctx) 211 { 212 psr->ctx = ctx; 213 psr->funcs = &psr_funcs; 214 } 215 216 /** 217 * Allocate and initialize PSR object. 218 */ 219 struct dmub_psr *dmub_psr_create(struct dc_context *ctx) 220 { 221 struct dmub_psr *psr = kzalloc(sizeof(struct dmub_psr), GFP_KERNEL); 222 223 if (psr == NULL) { 224 BREAK_TO_DEBUGGER(); 225 return NULL; 226 } 227 228 dmub_psr_construct(psr, ctx); 229 230 return psr; 231 } 232 233 /** 234 * Deallocate PSR object. 235 */ 236 void dmub_psr_destroy(struct dmub_psr **dmub) 237 { 238 kfree(*dmub); 239 *dmub = NULL; 240 } 241