1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/delay.h> 27 28 #include "dc_bios_types.h" 29 #include "dce_stream_encoder.h" 30 #include "reg_helper.h" 31 #include "hw_shared.h" 32 33 #define DC_LOGGER \ 34 enc110->base.ctx->logger 35 36 37 #define REG(reg)\ 38 (enc110->regs->reg) 39 40 #undef FN 41 #define FN(reg_name, field_name) \ 42 enc110->se_shift->field_name, enc110->se_mask->field_name 43 44 #define VBI_LINE_0 0 45 #define DP_BLANK_MAX_RETRY 20 46 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 47 48 #ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 49 #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x00000010L 50 #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x00000300L 51 #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x00000004 52 #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x00000008 53 #endif 54 55 enum { 56 DP_MST_UPDATE_MAX_RETRY = 50 57 }; 58 59 #define DCE110_SE(audio)\ 60 container_of(audio, struct dce110_stream_encoder, base) 61 62 #define CTX \ 63 enc110->base.ctx 64 65 static void dce110_update_generic_info_packet( 66 struct dce110_stream_encoder *enc110, 67 uint32_t packet_index, 68 const struct dc_info_packet *info_packet) 69 { 70 /* TODOFPGA Figure out a proper number for max_retries polling for lock 71 * use 50 for now. 72 */ 73 uint32_t max_retries = 50; 74 75 /*we need turn on clock before programming AFMT block*/ 76 if (REG(AFMT_CNTL)) 77 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 78 79 if (REG(AFMT_VBI_PACKET_CONTROL1)) { 80 if (packet_index >= 8) 81 ASSERT(0); 82 83 /* poll dig_update_lock is not locked -> asic internal signal 84 * assume otg master lock will unlock it 85 */ 86 /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, 87 0, 10, max_retries);*/ 88 89 /* check if HW reading GSP memory */ 90 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, 91 0, 10, max_retries); 92 93 /* HW does is not reading GSP memory not reading too long -> 94 * something wrong. clear GPS memory access and notify? 95 * hw SW is writing to GSP memory 96 */ 97 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); 98 } 99 /* choose which generic packet to use */ 100 { 101 REG_READ(AFMT_VBI_PACKET_CONTROL); 102 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, 103 AFMT_GENERIC_INDEX, packet_index); 104 } 105 106 /* write generic packet header 107 * (4th byte is for GENERIC0 only) */ 108 { 109 REG_SET_4(AFMT_GENERIC_HDR, 0, 110 AFMT_GENERIC_HB0, info_packet->hb0, 111 AFMT_GENERIC_HB1, info_packet->hb1, 112 AFMT_GENERIC_HB2, info_packet->hb2, 113 AFMT_GENERIC_HB3, info_packet->hb3); 114 } 115 116 /* write generic packet contents 117 * (we never use last 4 bytes) 118 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers */ 119 { 120 const uint32_t *content = 121 (const uint32_t *) &info_packet->sb[0]; 122 123 REG_WRITE(AFMT_GENERIC_0, *content++); 124 REG_WRITE(AFMT_GENERIC_1, *content++); 125 REG_WRITE(AFMT_GENERIC_2, *content++); 126 REG_WRITE(AFMT_GENERIC_3, *content++); 127 REG_WRITE(AFMT_GENERIC_4, *content++); 128 REG_WRITE(AFMT_GENERIC_5, *content++); 129 REG_WRITE(AFMT_GENERIC_6, *content++); 130 REG_WRITE(AFMT_GENERIC_7, *content); 131 } 132 133 if (!REG(AFMT_VBI_PACKET_CONTROL1)) { 134 /* force double-buffered packet update */ 135 REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL, 136 AFMT_GENERIC0_UPDATE, (packet_index == 0), 137 AFMT_GENERIC2_UPDATE, (packet_index == 2)); 138 } 139 140 if (REG(AFMT_VBI_PACKET_CONTROL1)) { 141 switch (packet_index) { 142 case 0: 143 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 144 AFMT_GENERIC0_FRAME_UPDATE, 1); 145 break; 146 case 1: 147 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 148 AFMT_GENERIC1_FRAME_UPDATE, 1); 149 break; 150 case 2: 151 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 152 AFMT_GENERIC2_FRAME_UPDATE, 1); 153 break; 154 case 3: 155 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 156 AFMT_GENERIC3_FRAME_UPDATE, 1); 157 break; 158 case 4: 159 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 160 AFMT_GENERIC4_FRAME_UPDATE, 1); 161 break; 162 case 5: 163 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 164 AFMT_GENERIC5_FRAME_UPDATE, 1); 165 break; 166 case 6: 167 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 168 AFMT_GENERIC6_FRAME_UPDATE, 1); 169 break; 170 case 7: 171 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 172 AFMT_GENERIC7_FRAME_UPDATE, 1); 173 break; 174 default: 175 break; 176 } 177 } 178 } 179 180 static void dce110_update_hdmi_info_packet( 181 struct dce110_stream_encoder *enc110, 182 uint32_t packet_index, 183 const struct dc_info_packet *info_packet) 184 { 185 uint32_t cont, send, line; 186 187 if (info_packet->valid) { 188 dce110_update_generic_info_packet( 189 enc110, 190 packet_index, 191 info_packet); 192 193 /* enable transmission of packet(s) - 194 * packet transmission begins on the next frame */ 195 cont = 1; 196 /* send packet(s) every frame */ 197 send = 1; 198 /* select line number to send packets on */ 199 line = 2; 200 } else { 201 cont = 0; 202 send = 0; 203 line = 0; 204 } 205 206 /* choose which generic packet control to use */ 207 switch (packet_index) { 208 case 0: 209 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 210 HDMI_GENERIC0_CONT, cont, 211 HDMI_GENERIC0_SEND, send, 212 HDMI_GENERIC0_LINE, line); 213 break; 214 case 1: 215 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 216 HDMI_GENERIC1_CONT, cont, 217 HDMI_GENERIC1_SEND, send, 218 HDMI_GENERIC1_LINE, line); 219 break; 220 case 2: 221 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 222 HDMI_GENERIC0_CONT, cont, 223 HDMI_GENERIC0_SEND, send, 224 HDMI_GENERIC0_LINE, line); 225 break; 226 case 3: 227 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 228 HDMI_GENERIC1_CONT, cont, 229 HDMI_GENERIC1_SEND, send, 230 HDMI_GENERIC1_LINE, line); 231 break; 232 case 4: 233 if (REG(HDMI_GENERIC_PACKET_CONTROL2)) 234 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 235 HDMI_GENERIC0_CONT, cont, 236 HDMI_GENERIC0_SEND, send, 237 HDMI_GENERIC0_LINE, line); 238 break; 239 case 5: 240 if (REG(HDMI_GENERIC_PACKET_CONTROL2)) 241 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 242 HDMI_GENERIC1_CONT, cont, 243 HDMI_GENERIC1_SEND, send, 244 HDMI_GENERIC1_LINE, line); 245 break; 246 case 6: 247 if (REG(HDMI_GENERIC_PACKET_CONTROL3)) 248 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 249 HDMI_GENERIC0_CONT, cont, 250 HDMI_GENERIC0_SEND, send, 251 HDMI_GENERIC0_LINE, line); 252 break; 253 case 7: 254 if (REG(HDMI_GENERIC_PACKET_CONTROL3)) 255 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 256 HDMI_GENERIC1_CONT, cont, 257 HDMI_GENERIC1_SEND, send, 258 HDMI_GENERIC1_LINE, line); 259 break; 260 default: 261 /* invalid HW packet index */ 262 DC_LOG_WARNING( 263 "Invalid HW packet index: %s()\n", 264 __func__); 265 return; 266 } 267 } 268 269 /* setup stream encoder in dp mode */ 270 static void dce110_stream_encoder_dp_set_stream_attribute( 271 struct stream_encoder *enc, 272 struct dc_crtc_timing *crtc_timing, 273 enum dc_color_space output_color_space, 274 bool use_vsc_sdp_for_colorimetry, 275 uint32_t enable_sdp_splitting) 276 { 277 uint32_t h_active_start; 278 uint32_t v_active_start; 279 uint32_t misc0 = 0; 280 uint32_t misc1 = 0; 281 uint32_t h_blank; 282 uint32_t h_back_porch; 283 uint8_t synchronous_clock = 0; /* asynchronous mode */ 284 uint8_t colorimetry_bpc; 285 uint8_t dynamic_range_rgb = 0; /*full range*/ 286 uint8_t dynamic_range_ycbcr = 1; /*bt709*/ 287 288 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 289 struct dc_crtc_timing hw_crtc_timing = *crtc_timing; 290 if (hw_crtc_timing.flags.INTERLACE) { 291 /*the input timing is in VESA spec format with Interlace flag =1*/ 292 hw_crtc_timing.v_total /= 2; 293 hw_crtc_timing.v_border_top /= 2; 294 hw_crtc_timing.v_addressable /= 2; 295 hw_crtc_timing.v_border_bottom /= 2; 296 hw_crtc_timing.v_front_porch /= 2; 297 hw_crtc_timing.v_sync_width /= 2; 298 } 299 /* set pixel encoding */ 300 switch (hw_crtc_timing.pixel_encoding) { 301 case PIXEL_ENCODING_YCBCR422: 302 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 303 DP_PIXEL_ENCODING_TYPE_YCBCR422); 304 break; 305 case PIXEL_ENCODING_YCBCR444: 306 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 307 DP_PIXEL_ENCODING_TYPE_YCBCR444); 308 309 if (hw_crtc_timing.flags.Y_ONLY) 310 if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666) 311 /* HW testing only, no use case yet. 312 * Color depth of Y-only could be 313 * 8, 10, 12, 16 bits */ 314 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 315 DP_PIXEL_ENCODING_TYPE_Y_ONLY); 316 /* Note: DP_MSA_MISC1 bit 7 is the indicator 317 * of Y-only mode. 318 * This bit is set in HW if register 319 * DP_PIXEL_ENCODING is programmed to 0x4 */ 320 break; 321 case PIXEL_ENCODING_YCBCR420: 322 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 323 DP_PIXEL_ENCODING_TYPE_YCBCR420); 324 if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN) 325 REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1); 326 327 if (enc110->se_mask->DP_VID_N_MUL) 328 REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1); 329 break; 330 default: 331 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 332 DP_PIXEL_ENCODING_TYPE_RGB444); 333 break; 334 } 335 336 if (REG(DP_MSA_MISC)) 337 misc1 = REG_READ(DP_MSA_MISC); 338 339 /* set color depth */ 340 341 switch (hw_crtc_timing.display_color_depth) { 342 case COLOR_DEPTH_666: 343 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 344 0); 345 break; 346 case COLOR_DEPTH_888: 347 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 348 DP_COMPONENT_PIXEL_DEPTH_8BPC); 349 break; 350 case COLOR_DEPTH_101010: 351 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 352 DP_COMPONENT_PIXEL_DEPTH_10BPC); 353 354 break; 355 case COLOR_DEPTH_121212: 356 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 357 DP_COMPONENT_PIXEL_DEPTH_12BPC); 358 break; 359 default: 360 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 361 DP_COMPONENT_PIXEL_DEPTH_6BPC); 362 break; 363 } 364 365 /* set dynamic range and YCbCr range */ 366 367 368 switch (hw_crtc_timing.display_color_depth) { 369 case COLOR_DEPTH_666: 370 colorimetry_bpc = 0; 371 break; 372 case COLOR_DEPTH_888: 373 colorimetry_bpc = 1; 374 break; 375 case COLOR_DEPTH_101010: 376 colorimetry_bpc = 2; 377 break; 378 case COLOR_DEPTH_121212: 379 colorimetry_bpc = 3; 380 break; 381 default: 382 colorimetry_bpc = 0; 383 break; 384 } 385 386 misc0 = misc0 | synchronous_clock; 387 misc0 = colorimetry_bpc << 5; 388 389 if (REG(DP_MSA_TIMING_PARAM1)) { 390 switch (output_color_space) { 391 case COLOR_SPACE_SRGB: 392 misc0 = misc0 | 0x0; 393 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 394 dynamic_range_rgb = 0; /*full range*/ 395 break; 396 case COLOR_SPACE_SRGB_LIMITED: 397 misc0 = misc0 | 0x8; /* bit3=1 */ 398 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 399 dynamic_range_rgb = 1; /*limited range*/ 400 break; 401 case COLOR_SPACE_YCBCR601: 402 case COLOR_SPACE_YCBCR601_LIMITED: 403 misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */ 404 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 405 dynamic_range_ycbcr = 0; /*bt601*/ 406 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 407 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 408 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444) 409 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 410 break; 411 case COLOR_SPACE_YCBCR709: 412 case COLOR_SPACE_YCBCR709_LIMITED: 413 case COLOR_SPACE_YCBCR709_BLACK: 414 misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */ 415 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 416 dynamic_range_ycbcr = 1; /*bt709*/ 417 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 418 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 419 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444) 420 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 421 break; 422 case COLOR_SPACE_2020_RGB_LIMITEDRANGE: 423 dynamic_range_rgb = 1; /*limited range*/ 424 break; 425 case COLOR_SPACE_2020_RGB_FULLRANGE: 426 case COLOR_SPACE_2020_YCBCR: 427 case COLOR_SPACE_XR_RGB: 428 case COLOR_SPACE_MSREF_SCRGB: 429 case COLOR_SPACE_ADOBERGB: 430 case COLOR_SPACE_DCIP3: 431 case COLOR_SPACE_XV_YCC_709: 432 case COLOR_SPACE_XV_YCC_601: 433 case COLOR_SPACE_DISPLAYNATIVE: 434 case COLOR_SPACE_DOLBYVISION: 435 case COLOR_SPACE_APPCTRL: 436 case COLOR_SPACE_CUSTOMPOINTS: 437 case COLOR_SPACE_UNKNOWN: 438 /* do nothing */ 439 break; 440 } 441 if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE) 442 REG_UPDATE_2( 443 DP_PIXEL_FORMAT, 444 DP_DYN_RANGE, dynamic_range_rgb, 445 DP_YCBCR_RANGE, dynamic_range_ycbcr); 446 447 if (REG(DP_MSA_COLORIMETRY)) 448 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); 449 450 if (REG(DP_MSA_MISC)) 451 REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */ 452 453 /* dcn new register 454 * dc_crtc_timing is vesa dmt struct. data from edid 455 */ 456 if (REG(DP_MSA_TIMING_PARAM1)) 457 REG_SET_2(DP_MSA_TIMING_PARAM1, 0, 458 DP_MSA_HTOTAL, hw_crtc_timing.h_total, 459 DP_MSA_VTOTAL, hw_crtc_timing.v_total); 460 461 /* calcuate from vesa timing parameters 462 * h_active_start related to leading edge of sync 463 */ 464 465 h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left - 466 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right; 467 468 h_back_porch = h_blank - hw_crtc_timing.h_front_porch - 469 hw_crtc_timing.h_sync_width; 470 471 /* start at begining of left border */ 472 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch; 473 474 475 v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top - 476 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom - 477 hw_crtc_timing.v_front_porch; 478 479 480 /* start at begining of left border */ 481 if (REG(DP_MSA_TIMING_PARAM2)) 482 REG_SET_2(DP_MSA_TIMING_PARAM2, 0, 483 DP_MSA_HSTART, h_active_start, 484 DP_MSA_VSTART, v_active_start); 485 486 if (REG(DP_MSA_TIMING_PARAM3)) 487 REG_SET_4(DP_MSA_TIMING_PARAM3, 0, 488 DP_MSA_HSYNCWIDTH, 489 hw_crtc_timing.h_sync_width, 490 DP_MSA_HSYNCPOLARITY, 491 !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY, 492 DP_MSA_VSYNCWIDTH, 493 hw_crtc_timing.v_sync_width, 494 DP_MSA_VSYNCPOLARITY, 495 !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY); 496 497 /* HWDITH include border or overscan */ 498 if (REG(DP_MSA_TIMING_PARAM4)) 499 REG_SET_2(DP_MSA_TIMING_PARAM4, 0, 500 DP_MSA_HWIDTH, hw_crtc_timing.h_border_left + 501 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right, 502 DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top + 503 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom); 504 } 505 } 506 507 static void dce110_stream_encoder_set_stream_attribute_helper( 508 struct dce110_stream_encoder *enc110, 509 struct dc_crtc_timing *crtc_timing) 510 { 511 if (enc110->regs->TMDS_CNTL) { 512 switch (crtc_timing->pixel_encoding) { 513 case PIXEL_ENCODING_YCBCR422: 514 REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1); 515 break; 516 default: 517 REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0); 518 break; 519 } 520 REG_UPDATE(TMDS_CNTL, TMDS_COLOR_FORMAT, 0); 521 } else if (enc110->regs->DIG_FE_CNTL) { 522 switch (crtc_timing->pixel_encoding) { 523 case PIXEL_ENCODING_YCBCR422: 524 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1); 525 break; 526 default: 527 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0); 528 break; 529 } 530 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0); 531 } 532 533 } 534 535 /* setup stream encoder in hdmi mode */ 536 static void dce110_stream_encoder_hdmi_set_stream_attribute( 537 struct stream_encoder *enc, 538 struct dc_crtc_timing *crtc_timing, 539 int actual_pix_clk_khz, 540 bool enable_audio) 541 { 542 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 543 struct bp_encoder_control cntl = {0}; 544 545 cntl.action = ENCODER_CONTROL_SETUP; 546 cntl.engine_id = enc110->base.id; 547 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; 548 cntl.enable_dp_audio = enable_audio; 549 cntl.pixel_clock = actual_pix_clk_khz; 550 cntl.lanes_number = LANE_COUNT_FOUR; 551 cntl.color_depth = crtc_timing->display_color_depth; 552 553 if (enc110->base.bp->funcs->encoder_control( 554 enc110->base.bp, &cntl) != BP_RESULT_OK) 555 return; 556 557 dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing); 558 559 /* setup HDMI engine */ 560 if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) { 561 REG_UPDATE_3(HDMI_CONTROL, 562 HDMI_PACKET_GEN_VERSION, 1, 563 HDMI_KEEPOUT_MODE, 1, 564 HDMI_DEEP_COLOR_ENABLE, 0); 565 } else if (enc110->regs->DIG_FE_CNTL) { 566 REG_UPDATE_5(HDMI_CONTROL, 567 HDMI_PACKET_GEN_VERSION, 1, 568 HDMI_KEEPOUT_MODE, 1, 569 HDMI_DEEP_COLOR_ENABLE, 0, 570 HDMI_DATA_SCRAMBLE_EN, 0, 571 HDMI_CLOCK_CHANNEL_RATE, 0); 572 } 573 574 switch (crtc_timing->display_color_depth) { 575 case COLOR_DEPTH_888: 576 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 577 break; 578 case COLOR_DEPTH_101010: 579 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 580 REG_UPDATE_2(HDMI_CONTROL, 581 HDMI_DEEP_COLOR_DEPTH, 1, 582 HDMI_DEEP_COLOR_ENABLE, 0); 583 } else { 584 REG_UPDATE_2(HDMI_CONTROL, 585 HDMI_DEEP_COLOR_DEPTH, 1, 586 HDMI_DEEP_COLOR_ENABLE, 1); 587 } 588 break; 589 case COLOR_DEPTH_121212: 590 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 591 REG_UPDATE_2(HDMI_CONTROL, 592 HDMI_DEEP_COLOR_DEPTH, 2, 593 HDMI_DEEP_COLOR_ENABLE, 0); 594 } else { 595 REG_UPDATE_2(HDMI_CONTROL, 596 HDMI_DEEP_COLOR_DEPTH, 2, 597 HDMI_DEEP_COLOR_ENABLE, 1); 598 } 599 break; 600 case COLOR_DEPTH_161616: 601 REG_UPDATE_2(HDMI_CONTROL, 602 HDMI_DEEP_COLOR_DEPTH, 3, 603 HDMI_DEEP_COLOR_ENABLE, 1); 604 break; 605 default: 606 break; 607 } 608 609 if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) { 610 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) { 611 /* enable HDMI data scrambler 612 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M 613 * Clock channel frequency is 1/4 of character rate. 614 */ 615 REG_UPDATE_2(HDMI_CONTROL, 616 HDMI_DATA_SCRAMBLE_EN, 1, 617 HDMI_CLOCK_CHANNEL_RATE, 1); 618 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) { 619 620 /* TODO: New feature for DCE11, still need to implement */ 621 622 /* enable HDMI data scrambler 623 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE 624 * Clock channel frequency is the same 625 * as character rate 626 */ 627 REG_UPDATE_2(HDMI_CONTROL, 628 HDMI_DATA_SCRAMBLE_EN, 1, 629 HDMI_CLOCK_CHANNEL_RATE, 0); 630 } 631 } 632 633 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL, 634 HDMI_GC_CONT, 1, 635 HDMI_GC_SEND, 1, 636 HDMI_NULL_SEND, 1); 637 638 /* following belongs to audio */ 639 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 640 641 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 642 643 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 644 VBI_LINE_0 + 2); 645 646 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); 647 648 } 649 650 /* setup stream encoder in dvi mode */ 651 static void dce110_stream_encoder_dvi_set_stream_attribute( 652 struct stream_encoder *enc, 653 struct dc_crtc_timing *crtc_timing, 654 bool is_dual_link) 655 { 656 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 657 struct bp_encoder_control cntl = {0}; 658 659 cntl.action = ENCODER_CONTROL_SETUP; 660 cntl.engine_id = enc110->base.id; 661 cntl.signal = is_dual_link ? 662 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK; 663 cntl.enable_dp_audio = false; 664 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10; 665 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; 666 667 if (enc110->base.bp->funcs->encoder_control( 668 enc110->base.bp, &cntl) != BP_RESULT_OK) 669 return; 670 671 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); 672 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888); 673 dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing); 674 } 675 676 /* setup stream encoder in LVDS mode */ 677 static void dce110_stream_encoder_lvds_set_stream_attribute( 678 struct stream_encoder *enc, 679 struct dc_crtc_timing *crtc_timing) 680 { 681 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 682 struct bp_encoder_control cntl = {0}; 683 684 cntl.action = ENCODER_CONTROL_SETUP; 685 cntl.engine_id = enc110->base.id; 686 cntl.signal = SIGNAL_TYPE_LVDS; 687 cntl.enable_dp_audio = false; 688 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10; 689 cntl.lanes_number = LANE_COUNT_FOUR; 690 691 if (enc110->base.bp->funcs->encoder_control( 692 enc110->base.bp, &cntl) != BP_RESULT_OK) 693 return; 694 695 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); 696 } 697 698 static void dce110_stream_encoder_set_throttled_vcp_size( 699 struct stream_encoder *enc, 700 struct fixed31_32 avg_time_slots_per_mtp) 701 { 702 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 703 uint32_t x = dc_fixpt_floor( 704 avg_time_slots_per_mtp); 705 uint32_t y = dc_fixpt_ceil( 706 dc_fixpt_shl( 707 dc_fixpt_sub_int( 708 avg_time_slots_per_mtp, 709 x), 710 26)); 711 712 { 713 REG_SET_2(DP_MSE_RATE_CNTL, 0, 714 DP_MSE_RATE_X, x, 715 DP_MSE_RATE_Y, y); 716 } 717 718 /* wait for update to be completed on the link */ 719 /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */ 720 /* is reset to 0 (not pending) */ 721 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, 722 0, 723 10, DP_MST_UPDATE_MAX_RETRY); 724 } 725 726 static void dce110_stream_encoder_update_hdmi_info_packets( 727 struct stream_encoder *enc, 728 const struct encoder_info_frame *info_frame) 729 { 730 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 731 732 if (enc110->se_mask->HDMI_AVI_INFO_CONT && 733 enc110->se_mask->HDMI_AVI_INFO_SEND) { 734 735 if (info_frame->avi.valid) { 736 const uint32_t *content = 737 (const uint32_t *) &info_frame->avi.sb[0]; 738 /*we need turn on clock before programming AFMT block*/ 739 if (REG(AFMT_CNTL)) 740 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 741 742 REG_WRITE(AFMT_AVI_INFO0, content[0]); 743 744 REG_WRITE(AFMT_AVI_INFO1, content[1]); 745 746 REG_WRITE(AFMT_AVI_INFO2, content[2]); 747 748 REG_WRITE(AFMT_AVI_INFO3, content[3]); 749 750 REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, 751 info_frame->avi.hb1); 752 753 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0, 754 HDMI_AVI_INFO_SEND, 1, 755 HDMI_AVI_INFO_CONT, 1); 756 757 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 758 VBI_LINE_0 + 2); 759 760 } else { 761 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0, 762 HDMI_AVI_INFO_SEND, 0, 763 HDMI_AVI_INFO_CONT, 0); 764 } 765 } 766 767 if (enc110->se_mask->HDMI_AVI_INFO_CONT && 768 enc110->se_mask->HDMI_AVI_INFO_SEND) { 769 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor); 770 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut); 771 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd); 772 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd); 773 } 774 775 if (enc110->se_mask->HDMI_DB_DISABLE) { 776 /* for bring up, disable dp double TODO */ 777 if (REG(HDMI_DB_CONTROL)) 778 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); 779 780 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->avi); 781 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->vendor); 782 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->gamut); 783 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd); 784 dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd); 785 } 786 } 787 788 static void dce110_stream_encoder_stop_hdmi_info_packets( 789 struct stream_encoder *enc) 790 { 791 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 792 793 /* stop generic packets 0 & 1 on HDMI */ 794 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0, 795 HDMI_GENERIC1_CONT, 0, 796 HDMI_GENERIC1_LINE, 0, 797 HDMI_GENERIC1_SEND, 0, 798 HDMI_GENERIC0_CONT, 0, 799 HDMI_GENERIC0_LINE, 0, 800 HDMI_GENERIC0_SEND, 0); 801 802 /* stop generic packets 2 & 3 on HDMI */ 803 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0, 804 HDMI_GENERIC0_CONT, 0, 805 HDMI_GENERIC0_LINE, 0, 806 HDMI_GENERIC0_SEND, 0, 807 HDMI_GENERIC1_CONT, 0, 808 HDMI_GENERIC1_LINE, 0, 809 HDMI_GENERIC1_SEND, 0); 810 811 /* stop generic packets 2 & 3 on HDMI */ 812 if (REG(HDMI_GENERIC_PACKET_CONTROL2)) 813 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0, 814 HDMI_GENERIC0_CONT, 0, 815 HDMI_GENERIC0_LINE, 0, 816 HDMI_GENERIC0_SEND, 0, 817 HDMI_GENERIC1_CONT, 0, 818 HDMI_GENERIC1_LINE, 0, 819 HDMI_GENERIC1_SEND, 0); 820 821 if (REG(HDMI_GENERIC_PACKET_CONTROL3)) 822 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0, 823 HDMI_GENERIC0_CONT, 0, 824 HDMI_GENERIC0_LINE, 0, 825 HDMI_GENERIC0_SEND, 0, 826 HDMI_GENERIC1_CONT, 0, 827 HDMI_GENERIC1_LINE, 0, 828 HDMI_GENERIC1_SEND, 0); 829 } 830 831 static void dce110_stream_encoder_update_dp_info_packets( 832 struct stream_encoder *enc, 833 const struct encoder_info_frame *info_frame) 834 { 835 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 836 uint32_t value = 0; 837 838 if (info_frame->vsc.valid) 839 dce110_update_generic_info_packet( 840 enc110, 841 0, /* packetIndex */ 842 &info_frame->vsc); 843 844 if (info_frame->spd.valid) 845 dce110_update_generic_info_packet( 846 enc110, 847 2, /* packetIndex */ 848 &info_frame->spd); 849 850 if (info_frame->hdrsmd.valid) 851 dce110_update_generic_info_packet( 852 enc110, 853 3, /* packetIndex */ 854 &info_frame->hdrsmd); 855 856 /* enable/disable transmission of packet(s). 857 * If enabled, packet transmission begins on the next frame 858 */ 859 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); 860 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); 861 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); 862 863 /* This bit is the master enable bit. 864 * When enabling secondary stream engine, 865 * this master bit must also be set. 866 * This register shared with audio info frame. 867 * Therefore we need to enable master bit 868 * if at least on of the fields is not 0 869 */ 870 value = REG_READ(DP_SEC_CNTL); 871 if (value) 872 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 873 } 874 875 static void dce110_stream_encoder_stop_dp_info_packets( 876 struct stream_encoder *enc) 877 { 878 /* stop generic packets on DP */ 879 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 880 uint32_t value = 0; 881 882 if (enc110->se_mask->DP_SEC_AVI_ENABLE) { 883 REG_SET_7(DP_SEC_CNTL, 0, 884 DP_SEC_GSP0_ENABLE, 0, 885 DP_SEC_GSP1_ENABLE, 0, 886 DP_SEC_GSP2_ENABLE, 0, 887 DP_SEC_GSP3_ENABLE, 0, 888 DP_SEC_AVI_ENABLE, 0, 889 DP_SEC_MPG_ENABLE, 0, 890 DP_SEC_STREAM_ENABLE, 0); 891 } 892 893 /* this register shared with audio info frame. 894 * therefore we need to keep master enabled 895 * if at least one of the fields is not 0 */ 896 value = REG_READ(DP_SEC_CNTL); 897 if (value) 898 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 899 900 } 901 902 static void dce110_stream_encoder_dp_blank( 903 struct dc_link *link, 904 struct stream_encoder *enc) 905 { 906 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 907 uint32_t reg1 = 0; 908 uint32_t max_retries = DP_BLANK_MAX_RETRY * 10; 909 910 /* Note: For CZ, we are changing driver default to disable 911 * stream deferred to next VBLANK. If results are positive, we 912 * will make the same change to all DCE versions. There are a 913 * handful of panels that cannot handle disable stream at 914 * HBLANK and will result in a white line flash across the 915 * screen on stream disable. */ 916 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1); 917 if ((reg1 & 0x1) == 0) 918 /*stream not enabled*/ 919 return; 920 /* Specify the video stream disable point 921 * (2 = start of the next vertical blank) */ 922 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2); 923 /* Larger delay to wait until VBLANK - use max retry of 924 * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode + 925 * a little more because we may not trust delay accuracy. 926 */ 927 max_retries = DP_BLANK_MAX_RETRY * 150; 928 929 /* disable DP stream */ 930 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); 931 932 /* the encoder stops sending the video stream 933 * at the start of the vertical blanking. 934 * Poll for DP_VID_STREAM_STATUS == 0 935 */ 936 937 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 938 0, 939 10, max_retries); 940 941 /* Tell the DP encoder to ignore timing from CRTC, must be done after 942 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is 943 * complete, stream status will be stuck in video stream enabled state, 944 * i.e. DP_VID_STREAM_STATUS stuck at 1. 945 */ 946 947 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true); 948 } 949 950 /* output video stream to link encoder */ 951 static void dce110_stream_encoder_dp_unblank( 952 struct dc_link *link, 953 struct stream_encoder *enc, 954 const struct encoder_unblank_param *param) 955 { 956 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 957 958 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { 959 uint32_t n_vid = 0x8000; 960 uint32_t m_vid; 961 962 /* M / N = Fstream / Flink 963 * m_vid / n_vid = pixel rate / link rate 964 */ 965 966 uint64_t m_vid_l = n_vid; 967 968 m_vid_l *= param->timing.pix_clk_100hz / 10; 969 m_vid_l = div_u64(m_vid_l, 970 param->link_settings.link_rate 971 * LINK_RATE_REF_FREQ_IN_KHZ); 972 973 m_vid = (uint32_t) m_vid_l; 974 975 /* enable auto measurement */ 976 977 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0); 978 979 /* auto measurement need 1 full 0x8000 symbol cycle to kick in, 980 * therefore program initial value for Mvid and Nvid 981 */ 982 983 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid); 984 985 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid); 986 987 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1); 988 } 989 990 /* set DIG_START to 0x1 to resync FIFO */ 991 992 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); 993 994 /* switch DP encoder to CRTC data */ 995 996 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); 997 998 /* wait 100us for DIG/DP logic to prime 999 * (i.e. a few video lines) 1000 */ 1001 udelay(100); 1002 1003 /* the hardware would start sending video at the start of the next DP 1004 * frame (i.e. rising edge of the vblank). 1005 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this 1006 * register has no effect on enable transition! HW always guarantees 1007 * VID_STREAM enable at start of next frame, and this is not 1008 * programmable 1009 */ 1010 1011 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); 1012 } 1013 1014 static void dce110_stream_encoder_set_avmute( 1015 struct stream_encoder *enc, 1016 bool enable) 1017 { 1018 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1019 unsigned int value = enable ? 1 : 0; 1020 1021 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value); 1022 } 1023 1024 1025 static void dce110_reset_hdmi_stream_attribute( 1026 struct stream_encoder *enc) 1027 { 1028 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1029 if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) 1030 REG_UPDATE_5(HDMI_CONTROL, 1031 HDMI_PACKET_GEN_VERSION, 1, 1032 HDMI_KEEPOUT_MODE, 1, 1033 HDMI_DEEP_COLOR_ENABLE, 0, 1034 HDMI_DATA_SCRAMBLE_EN, 0, 1035 HDMI_CLOCK_CHANNEL_RATE, 0); 1036 else 1037 REG_UPDATE_3(HDMI_CONTROL, 1038 HDMI_PACKET_GEN_VERSION, 1, 1039 HDMI_KEEPOUT_MODE, 1, 1040 HDMI_DEEP_COLOR_ENABLE, 0); 1041 } 1042 1043 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000 1044 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1 1045 1046 #include "include/audio_types.h" 1047 1048 1049 /* 25.2MHz/1.001*/ 1050 /* 25.2MHz/1.001*/ 1051 /* 25.2MHz*/ 1052 /* 27MHz */ 1053 /* 27MHz*1.001*/ 1054 /* 27MHz*1.001*/ 1055 /* 54MHz*/ 1056 /* 54MHz*1.001*/ 1057 /* 74.25MHz/1.001*/ 1058 /* 74.25MHz*/ 1059 /* 148.5MHz/1.001*/ 1060 /* 148.5MHz*/ 1061 1062 static const struct audio_clock_info audio_clock_info_table[16] = { 1063 {2517, 4576, 28125, 7007, 31250, 6864, 28125}, 1064 {2518, 4576, 28125, 7007, 31250, 6864, 28125}, 1065 {2520, 4096, 25200, 6272, 28000, 6144, 25200}, 1066 {2700, 4096, 27000, 6272, 30000, 6144, 27000}, 1067 {2702, 4096, 27027, 6272, 30030, 6144, 27027}, 1068 {2703, 4096, 27027, 6272, 30030, 6144, 27027}, 1069 {5400, 4096, 54000, 6272, 60000, 6144, 54000}, 1070 {5405, 4096, 54054, 6272, 60060, 6144, 54054}, 1071 {7417, 11648, 210937, 17836, 234375, 11648, 140625}, 1072 {7425, 4096, 74250, 6272, 82500, 6144, 74250}, 1073 {14835, 11648, 421875, 8918, 234375, 5824, 140625}, 1074 {14850, 4096, 148500, 6272, 165000, 6144, 148500}, 1075 {29670, 5824, 421875, 4459, 234375, 5824, 281250}, 1076 {29700, 3072, 222750, 4704, 247500, 5120, 247500}, 1077 {59340, 5824, 843750, 8918, 937500, 5824, 562500}, 1078 {59400, 3072, 445500, 9408, 990000, 6144, 594000} 1079 }; 1080 1081 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = { 1082 {2517, 9152, 84375, 7007, 48875, 9152, 56250}, 1083 {2518, 9152, 84375, 7007, 48875, 9152, 56250}, 1084 {2520, 4096, 37800, 6272, 42000, 6144, 37800}, 1085 {2700, 4096, 40500, 6272, 45000, 6144, 40500}, 1086 {2702, 8192, 81081, 6272, 45045, 8192, 54054}, 1087 {2703, 8192, 81081, 6272, 45045, 8192, 54054}, 1088 {5400, 4096, 81000, 6272, 90000, 6144, 81000}, 1089 {5405, 4096, 81081, 6272, 90090, 6144, 81081}, 1090 {7417, 11648, 316406, 17836, 351562, 11648, 210937}, 1091 {7425, 4096, 111375, 6272, 123750, 6144, 111375}, 1092 {14835, 11648, 632812, 17836, 703125, 11648, 421875}, 1093 {14850, 4096, 222750, 6272, 247500, 6144, 222750}, 1094 {29670, 5824, 632812, 8918, 703125, 5824, 421875}, 1095 {29700, 4096, 445500, 4704, 371250, 5120, 371250} 1096 }; 1097 1098 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = { 1099 {2517, 4576, 56250, 7007, 62500, 6864, 56250}, 1100 {2518, 4576, 56250, 7007, 62500, 6864, 56250}, 1101 {2520, 4096, 50400, 6272, 56000, 6144, 50400}, 1102 {2700, 4096, 54000, 6272, 60000, 6144, 54000}, 1103 {2702, 4096, 54054, 6267, 60060, 8192, 54054}, 1104 {2703, 4096, 54054, 6272, 60060, 8192, 54054}, 1105 {5400, 4096, 108000, 6272, 120000, 6144, 108000}, 1106 {5405, 4096, 108108, 6272, 120120, 6144, 108108}, 1107 {7417, 11648, 421875, 17836, 468750, 11648, 281250}, 1108 {7425, 4096, 148500, 6272, 165000, 6144, 148500}, 1109 {14835, 11648, 843750, 8918, 468750, 11648, 281250}, 1110 {14850, 4096, 297000, 6272, 330000, 6144, 297000}, 1111 {29670, 5824, 843750, 4459, 468750, 5824, 562500}, 1112 {29700, 3072, 445500, 4704, 495000, 5120, 495000} 1113 1114 1115 }; 1116 1117 static union audio_cea_channels speakers_to_channels( 1118 struct audio_speaker_flags speaker_flags) 1119 { 1120 union audio_cea_channels cea_channels = {0}; 1121 1122 /* these are one to one */ 1123 cea_channels.channels.FL = speaker_flags.FL_FR; 1124 cea_channels.channels.FR = speaker_flags.FL_FR; 1125 cea_channels.channels.LFE = speaker_flags.LFE; 1126 cea_channels.channels.FC = speaker_flags.FC; 1127 1128 /* if Rear Left and Right exist move RC speaker to channel 7 1129 * otherwise to channel 5 1130 */ 1131 if (speaker_flags.RL_RR) { 1132 cea_channels.channels.RL_RC = speaker_flags.RL_RR; 1133 cea_channels.channels.RR = speaker_flags.RL_RR; 1134 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC; 1135 } else { 1136 cea_channels.channels.RL_RC = speaker_flags.RC; 1137 } 1138 1139 /* FRONT Left Right Center and REAR Left Right Center are exclusive */ 1140 if (speaker_flags.FLC_FRC) { 1141 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC; 1142 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC; 1143 } else { 1144 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC; 1145 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC; 1146 } 1147 1148 return cea_channels; 1149 } 1150 1151 static uint32_t calc_max_audio_packets_per_line( 1152 const struct audio_crtc_info *crtc_info) 1153 { 1154 uint32_t max_packets_per_line; 1155 1156 max_packets_per_line = 1157 crtc_info->h_total - crtc_info->h_active; 1158 1159 if (crtc_info->pixel_repetition) 1160 max_packets_per_line *= crtc_info->pixel_repetition; 1161 1162 /* for other hdmi features */ 1163 max_packets_per_line -= 58; 1164 /* for Control Period */ 1165 max_packets_per_line -= 16; 1166 /* Number of Audio Packets per Line */ 1167 max_packets_per_line /= 32; 1168 1169 return max_packets_per_line; 1170 } 1171 1172 static void get_audio_clock_info( 1173 enum dc_color_depth color_depth, 1174 uint32_t crtc_pixel_clock_100Hz, 1175 uint32_t actual_pixel_clock_100Hz, 1176 struct audio_clock_info *audio_clock_info) 1177 { 1178 const struct audio_clock_info *clock_info; 1179 uint32_t index; 1180 uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100; 1181 uint32_t audio_array_size; 1182 1183 switch (color_depth) { 1184 case COLOR_DEPTH_161616: 1185 clock_info = audio_clock_info_table_48bpc; 1186 audio_array_size = ARRAY_SIZE( 1187 audio_clock_info_table_48bpc); 1188 break; 1189 case COLOR_DEPTH_121212: 1190 clock_info = audio_clock_info_table_36bpc; 1191 audio_array_size = ARRAY_SIZE( 1192 audio_clock_info_table_36bpc); 1193 break; 1194 default: 1195 clock_info = audio_clock_info_table; 1196 audio_array_size = ARRAY_SIZE( 1197 audio_clock_info_table); 1198 break; 1199 } 1200 1201 if (clock_info != NULL) { 1202 /* search for exact pixel clock in table */ 1203 for (index = 0; index < audio_array_size; index++) { 1204 if (clock_info[index].pixel_clock_in_10khz > 1205 crtc_pixel_clock_in_10khz) 1206 break; /* not match */ 1207 else if (clock_info[index].pixel_clock_in_10khz == 1208 crtc_pixel_clock_in_10khz) { 1209 /* match found */ 1210 *audio_clock_info = clock_info[index]; 1211 return; 1212 } 1213 } 1214 } 1215 1216 /* not found */ 1217 if (actual_pixel_clock_100Hz == 0) 1218 actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz; 1219 1220 /* See HDMI spec the table entry under 1221 * pixel clock of "Other". */ 1222 audio_clock_info->pixel_clock_in_10khz = 1223 actual_pixel_clock_100Hz / 100; 1224 audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10; 1225 audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10; 1226 audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10; 1227 1228 audio_clock_info->n_32khz = 4096; 1229 audio_clock_info->n_44khz = 6272; 1230 audio_clock_info->n_48khz = 6144; 1231 } 1232 1233 static void dce110_se_audio_setup( 1234 struct stream_encoder *enc, 1235 unsigned int az_inst, 1236 struct audio_info *audio_info) 1237 { 1238 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1239 1240 uint32_t channels = 0; 1241 1242 ASSERT(audio_info); 1243 if (audio_info == NULL) 1244 /* This should not happen.it does so we don't get BSOD*/ 1245 return; 1246 1247 channels = speakers_to_channels(audio_info->flags.speaker_flags).all; 1248 1249 /* setup the audio stream source select (audio -> dig mapping) */ 1250 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); 1251 1252 /* Channel allocation */ 1253 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels); 1254 } 1255 1256 static void dce110_se_setup_hdmi_audio( 1257 struct stream_encoder *enc, 1258 const struct audio_crtc_info *crtc_info) 1259 { 1260 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1261 1262 struct audio_clock_info audio_clock_info = {0}; 1263 uint32_t max_packets_per_line; 1264 1265 /* For now still do calculation, although this field is ignored when 1266 above HDMI_PACKET_GEN_VERSION set to 1 */ 1267 max_packets_per_line = calc_max_audio_packets_per_line(crtc_info); 1268 1269 /* HDMI_AUDIO_PACKET_CONTROL */ 1270 REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL, 1271 HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line, 1272 HDMI_AUDIO_DELAY_EN, 1); 1273 1274 /* AFMT_AUDIO_PACKET_CONTROL */ 1275 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1276 1277 /* AFMT_AUDIO_PACKET_CONTROL2 */ 1278 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 1279 AFMT_AUDIO_LAYOUT_OVRD, 0, 1280 AFMT_60958_OSF_OVRD, 0); 1281 1282 /* HDMI_ACR_PACKET_CONTROL */ 1283 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, 1284 HDMI_ACR_AUTO_SEND, 1, 1285 HDMI_ACR_SOURCE, 0, 1286 HDMI_ACR_AUDIO_PRIORITY, 0); 1287 1288 /* Program audio clock sample/regeneration parameters */ 1289 get_audio_clock_info(crtc_info->color_depth, 1290 crtc_info->requested_pixel_clock_100Hz, 1291 crtc_info->calculated_pixel_clock_100Hz, 1292 &audio_clock_info); 1293 DC_LOG_HW_AUDIO( 1294 "\n%s:Input::requested_pixel_clock_100Hz = %d" \ 1295 "calculated_pixel_clock_100Hz = %d \n", __func__, \ 1296 crtc_info->requested_pixel_clock_100Hz, \ 1297 crtc_info->calculated_pixel_clock_100Hz); 1298 1299 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */ 1300 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); 1301 1302 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */ 1303 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); 1304 1305 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */ 1306 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); 1307 1308 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */ 1309 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); 1310 1311 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */ 1312 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); 1313 1314 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */ 1315 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz); 1316 1317 /* Video driver cannot know in advance which sample rate will 1318 be used by HD Audio driver 1319 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is 1320 programmed below in interruppt callback */ 1321 1322 /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK & 1323 AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */ 1324 REG_UPDATE_2(AFMT_60958_0, 1325 AFMT_60958_CS_CHANNEL_NUMBER_L, 1, 1326 AFMT_60958_CS_CLOCK_ACCURACY, 0); 1327 1328 /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */ 1329 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1330 1331 /*AFMT_60958_2 now keep this settings until 1332 * Programming guide comes out*/ 1333 REG_UPDATE_6(AFMT_60958_2, 1334 AFMT_60958_CS_CHANNEL_NUMBER_2, 3, 1335 AFMT_60958_CS_CHANNEL_NUMBER_3, 4, 1336 AFMT_60958_CS_CHANNEL_NUMBER_4, 5, 1337 AFMT_60958_CS_CHANNEL_NUMBER_5, 6, 1338 AFMT_60958_CS_CHANNEL_NUMBER_6, 7, 1339 AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1340 } 1341 1342 static void dce110_se_setup_dp_audio( 1343 struct stream_encoder *enc) 1344 { 1345 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1346 1347 /* --- DP Audio packet configurations --- */ 1348 1349 /* ATP Configuration */ 1350 REG_SET(DP_SEC_AUD_N, 0, 1351 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT); 1352 1353 /* Async/auto-calc timestamp mode */ 1354 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE, 1355 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC); 1356 1357 /* --- The following are the registers 1358 * copied from the SetupHDMI --- */ 1359 1360 /* AFMT_AUDIO_PACKET_CONTROL */ 1361 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1362 1363 /* AFMT_AUDIO_PACKET_CONTROL2 */ 1364 /* Program the ATP and AIP next */ 1365 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 1366 AFMT_AUDIO_LAYOUT_OVRD, 0, 1367 AFMT_60958_OSF_OVRD, 0); 1368 1369 /* AFMT_INFOFRAME_CONTROL0 */ 1370 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1371 1372 /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */ 1373 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0); 1374 } 1375 1376 static void dce110_se_enable_audio_clock( 1377 struct stream_encoder *enc, 1378 bool enable) 1379 { 1380 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1381 1382 if (REG(AFMT_CNTL) == 0) 1383 return; /* DCE8/10 does not have this register */ 1384 1385 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable); 1386 1387 /* wait for AFMT clock to turn on, 1388 * expectation: this should complete in 1-2 reads 1389 * 1390 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10); 1391 * 1392 * TODO: wait for clock_on does not work well. May need HW 1393 * program sequence. But audio seems work normally even without wait 1394 * for clock_on status change 1395 */ 1396 } 1397 1398 static void dce110_se_enable_dp_audio( 1399 struct stream_encoder *enc) 1400 { 1401 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1402 1403 /* Enable Audio packets */ 1404 REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); 1405 1406 /* Program the ATP and AIP next */ 1407 REG_UPDATE_2(DP_SEC_CNTL, 1408 DP_SEC_ATP_ENABLE, 1, 1409 DP_SEC_AIP_ENABLE, 1); 1410 1411 /* Program STREAM_ENABLE after all the other enables. */ 1412 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1413 } 1414 1415 static void dce110_se_disable_dp_audio( 1416 struct stream_encoder *enc) 1417 { 1418 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1419 uint32_t value = 0; 1420 1421 /* Disable Audio packets */ 1422 REG_UPDATE_5(DP_SEC_CNTL, 1423 DP_SEC_ASP_ENABLE, 0, 1424 DP_SEC_ATP_ENABLE, 0, 1425 DP_SEC_AIP_ENABLE, 0, 1426 DP_SEC_ACM_ENABLE, 0, 1427 DP_SEC_STREAM_ENABLE, 0); 1428 1429 /* This register shared with encoder info frame. Therefore we need to 1430 keep master enabled if at least on of the fields is not 0 */ 1431 value = REG_READ(DP_SEC_CNTL); 1432 if (value != 0) 1433 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1434 1435 } 1436 1437 void dce110_se_audio_mute_control( 1438 struct stream_encoder *enc, 1439 bool mute) 1440 { 1441 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1442 1443 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute); 1444 } 1445 1446 void dce110_se_dp_audio_setup( 1447 struct stream_encoder *enc, 1448 unsigned int az_inst, 1449 struct audio_info *info) 1450 { 1451 dce110_se_audio_setup(enc, az_inst, info); 1452 } 1453 1454 void dce110_se_dp_audio_enable( 1455 struct stream_encoder *enc) 1456 { 1457 dce110_se_enable_audio_clock(enc, true); 1458 dce110_se_setup_dp_audio(enc); 1459 dce110_se_enable_dp_audio(enc); 1460 } 1461 1462 void dce110_se_dp_audio_disable( 1463 struct stream_encoder *enc) 1464 { 1465 dce110_se_disable_dp_audio(enc); 1466 dce110_se_enable_audio_clock(enc, false); 1467 } 1468 1469 void dce110_se_hdmi_audio_setup( 1470 struct stream_encoder *enc, 1471 unsigned int az_inst, 1472 struct audio_info *info, 1473 struct audio_crtc_info *audio_crtc_info) 1474 { 1475 dce110_se_enable_audio_clock(enc, true); 1476 dce110_se_setup_hdmi_audio(enc, audio_crtc_info); 1477 dce110_se_audio_setup(enc, az_inst, info); 1478 } 1479 1480 void dce110_se_hdmi_audio_disable( 1481 struct stream_encoder *enc) 1482 { 1483 dce110_se_enable_audio_clock(enc, false); 1484 } 1485 1486 1487 static void setup_stereo_sync( 1488 struct stream_encoder *enc, 1489 int tg_inst, bool enable) 1490 { 1491 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1492 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); 1493 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable); 1494 } 1495 1496 static void dig_connect_to_otg( 1497 struct stream_encoder *enc, 1498 int tg_inst) 1499 { 1500 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1501 1502 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); 1503 } 1504 1505 static unsigned int dig_source_otg( 1506 struct stream_encoder *enc) 1507 { 1508 uint32_t tg_inst = 0; 1509 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1510 1511 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); 1512 1513 return tg_inst; 1514 } 1515 1516 static const struct stream_encoder_funcs dce110_str_enc_funcs = { 1517 .dp_set_stream_attribute = 1518 dce110_stream_encoder_dp_set_stream_attribute, 1519 .hdmi_set_stream_attribute = 1520 dce110_stream_encoder_hdmi_set_stream_attribute, 1521 .dvi_set_stream_attribute = 1522 dce110_stream_encoder_dvi_set_stream_attribute, 1523 .lvds_set_stream_attribute = 1524 dce110_stream_encoder_lvds_set_stream_attribute, 1525 .set_throttled_vcp_size = 1526 dce110_stream_encoder_set_throttled_vcp_size, 1527 .update_hdmi_info_packets = 1528 dce110_stream_encoder_update_hdmi_info_packets, 1529 .stop_hdmi_info_packets = 1530 dce110_stream_encoder_stop_hdmi_info_packets, 1531 .update_dp_info_packets = 1532 dce110_stream_encoder_update_dp_info_packets, 1533 .stop_dp_info_packets = 1534 dce110_stream_encoder_stop_dp_info_packets, 1535 .dp_blank = 1536 dce110_stream_encoder_dp_blank, 1537 .dp_unblank = 1538 dce110_stream_encoder_dp_unblank, 1539 .audio_mute_control = dce110_se_audio_mute_control, 1540 1541 .dp_audio_setup = dce110_se_dp_audio_setup, 1542 .dp_audio_enable = dce110_se_dp_audio_enable, 1543 .dp_audio_disable = dce110_se_dp_audio_disable, 1544 1545 .hdmi_audio_setup = dce110_se_hdmi_audio_setup, 1546 .hdmi_audio_disable = dce110_se_hdmi_audio_disable, 1547 .setup_stereo_sync = setup_stereo_sync, 1548 .set_avmute = dce110_stream_encoder_set_avmute, 1549 .dig_connect_to_otg = dig_connect_to_otg, 1550 .hdmi_reset_stream_attribute = dce110_reset_hdmi_stream_attribute, 1551 .dig_source_otg = dig_source_otg, 1552 }; 1553 1554 void dce110_stream_encoder_construct( 1555 struct dce110_stream_encoder *enc110, 1556 struct dc_context *ctx, 1557 struct dc_bios *bp, 1558 enum engine_id eng_id, 1559 const struct dce110_stream_enc_registers *regs, 1560 const struct dce_stream_encoder_shift *se_shift, 1561 const struct dce_stream_encoder_mask *se_mask) 1562 { 1563 enc110->base.funcs = &dce110_str_enc_funcs; 1564 enc110->base.ctx = ctx; 1565 enc110->base.id = eng_id; 1566 enc110->base.bp = bp; 1567 enc110->regs = regs; 1568 enc110->se_shift = se_shift; 1569 enc110->se_mask = se_mask; 1570 } 1571