1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dc_bios_types.h" 27 #include "dce_stream_encoder.h" 28 #include "reg_helper.h" 29 #include "hw_shared.h" 30 31 #define DC_LOGGER \ 32 enc110->base.ctx->logger 33 34 35 #define REG(reg)\ 36 (enc110->regs->reg) 37 38 #undef FN 39 #define FN(reg_name, field_name) \ 40 enc110->se_shift->field_name, enc110->se_mask->field_name 41 42 #define VBI_LINE_0 0 43 #define DP_BLANK_MAX_RETRY 20 44 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 45 46 #ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 47 #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x00000010L 48 #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x00000300L 49 #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x00000004 50 #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x00000008 51 #endif 52 53 enum { 54 DP_MST_UPDATE_MAX_RETRY = 50 55 }; 56 57 #define DCE110_SE(audio)\ 58 container_of(audio, struct dce110_stream_encoder, base) 59 60 #define CTX \ 61 enc110->base.ctx 62 63 static void dce110_update_generic_info_packet( 64 struct dce110_stream_encoder *enc110, 65 uint32_t packet_index, 66 const struct dc_info_packet *info_packet) 67 { 68 uint32_t regval; 69 /* TODOFPGA Figure out a proper number for max_retries polling for lock 70 * use 50 for now. 71 */ 72 uint32_t max_retries = 50; 73 74 /*we need turn on clock before programming AFMT block*/ 75 if (REG(AFMT_CNTL)) 76 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 77 78 if (REG(AFMT_VBI_PACKET_CONTROL1)) { 79 if (packet_index >= 8) 80 ASSERT(0); 81 82 /* poll dig_update_lock is not locked -> asic internal signal 83 * assume otg master lock will unlock it 84 */ 85 /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, 86 0, 10, max_retries);*/ 87 88 /* check if HW reading GSP memory */ 89 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, 90 0, 10, max_retries); 91 92 /* HW does is not reading GSP memory not reading too long -> 93 * something wrong. clear GPS memory access and notify? 94 * hw SW is writing to GSP memory 95 */ 96 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); 97 } 98 /* choose which generic packet to use */ 99 { 100 regval = REG_READ(AFMT_VBI_PACKET_CONTROL); 101 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, 102 AFMT_GENERIC_INDEX, packet_index); 103 } 104 105 /* write generic packet header 106 * (4th byte is for GENERIC0 only) */ 107 { 108 REG_SET_4(AFMT_GENERIC_HDR, 0, 109 AFMT_GENERIC_HB0, info_packet->hb0, 110 AFMT_GENERIC_HB1, info_packet->hb1, 111 AFMT_GENERIC_HB2, info_packet->hb2, 112 AFMT_GENERIC_HB3, info_packet->hb3); 113 } 114 115 /* write generic packet contents 116 * (we never use last 4 bytes) 117 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers */ 118 { 119 const uint32_t *content = 120 (const uint32_t *) &info_packet->sb[0]; 121 122 REG_WRITE(AFMT_GENERIC_0, *content++); 123 REG_WRITE(AFMT_GENERIC_1, *content++); 124 REG_WRITE(AFMT_GENERIC_2, *content++); 125 REG_WRITE(AFMT_GENERIC_3, *content++); 126 REG_WRITE(AFMT_GENERIC_4, *content++); 127 REG_WRITE(AFMT_GENERIC_5, *content++); 128 REG_WRITE(AFMT_GENERIC_6, *content++); 129 REG_WRITE(AFMT_GENERIC_7, *content); 130 } 131 132 if (!REG(AFMT_VBI_PACKET_CONTROL1)) { 133 /* force double-buffered packet update */ 134 REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL, 135 AFMT_GENERIC0_UPDATE, (packet_index == 0), 136 AFMT_GENERIC2_UPDATE, (packet_index == 2)); 137 } 138 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 139 if (REG(AFMT_VBI_PACKET_CONTROL1)) { 140 switch (packet_index) { 141 case 0: 142 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 143 AFMT_GENERIC0_FRAME_UPDATE, 1); 144 break; 145 case 1: 146 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 147 AFMT_GENERIC1_FRAME_UPDATE, 1); 148 break; 149 case 2: 150 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 151 AFMT_GENERIC2_FRAME_UPDATE, 1); 152 break; 153 case 3: 154 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 155 AFMT_GENERIC3_FRAME_UPDATE, 1); 156 break; 157 case 4: 158 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 159 AFMT_GENERIC4_FRAME_UPDATE, 1); 160 break; 161 case 5: 162 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 163 AFMT_GENERIC5_FRAME_UPDATE, 1); 164 break; 165 case 6: 166 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 167 AFMT_GENERIC6_FRAME_UPDATE, 1); 168 break; 169 case 7: 170 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 171 AFMT_GENERIC7_FRAME_UPDATE, 1); 172 break; 173 default: 174 break; 175 } 176 } 177 #endif 178 } 179 180 static void dce110_update_hdmi_info_packet( 181 struct dce110_stream_encoder *enc110, 182 uint32_t packet_index, 183 const struct dc_info_packet *info_packet) 184 { 185 uint32_t cont, send, line; 186 187 if (info_packet->valid) { 188 dce110_update_generic_info_packet( 189 enc110, 190 packet_index, 191 info_packet); 192 193 /* enable transmission of packet(s) - 194 * packet transmission begins on the next frame */ 195 cont = 1; 196 /* send packet(s) every frame */ 197 send = 1; 198 /* select line number to send packets on */ 199 line = 2; 200 } else { 201 cont = 0; 202 send = 0; 203 line = 0; 204 } 205 206 /* choose which generic packet control to use */ 207 switch (packet_index) { 208 case 0: 209 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 210 HDMI_GENERIC0_CONT, cont, 211 HDMI_GENERIC0_SEND, send, 212 HDMI_GENERIC0_LINE, line); 213 break; 214 case 1: 215 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 216 HDMI_GENERIC1_CONT, cont, 217 HDMI_GENERIC1_SEND, send, 218 HDMI_GENERIC1_LINE, line); 219 break; 220 case 2: 221 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 222 HDMI_GENERIC0_CONT, cont, 223 HDMI_GENERIC0_SEND, send, 224 HDMI_GENERIC0_LINE, line); 225 break; 226 case 3: 227 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 228 HDMI_GENERIC1_CONT, cont, 229 HDMI_GENERIC1_SEND, send, 230 HDMI_GENERIC1_LINE, line); 231 break; 232 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 233 case 4: 234 if (REG(HDMI_GENERIC_PACKET_CONTROL2)) 235 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 236 HDMI_GENERIC0_CONT, cont, 237 HDMI_GENERIC0_SEND, send, 238 HDMI_GENERIC0_LINE, line); 239 break; 240 case 5: 241 if (REG(HDMI_GENERIC_PACKET_CONTROL2)) 242 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 243 HDMI_GENERIC1_CONT, cont, 244 HDMI_GENERIC1_SEND, send, 245 HDMI_GENERIC1_LINE, line); 246 break; 247 case 6: 248 if (REG(HDMI_GENERIC_PACKET_CONTROL3)) 249 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 250 HDMI_GENERIC0_CONT, cont, 251 HDMI_GENERIC0_SEND, send, 252 HDMI_GENERIC0_LINE, line); 253 break; 254 case 7: 255 if (REG(HDMI_GENERIC_PACKET_CONTROL3)) 256 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 257 HDMI_GENERIC1_CONT, cont, 258 HDMI_GENERIC1_SEND, send, 259 HDMI_GENERIC1_LINE, line); 260 break; 261 #endif 262 default: 263 /* invalid HW packet index */ 264 DC_LOG_WARNING( 265 "Invalid HW packet index: %s()\n", 266 __func__); 267 return; 268 } 269 } 270 271 /* setup stream encoder in dp mode */ 272 static void dce110_stream_encoder_dp_set_stream_attribute( 273 struct stream_encoder *enc, 274 struct dc_crtc_timing *crtc_timing, 275 enum dc_color_space output_color_space) 276 { 277 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 278 uint32_t h_active_start; 279 uint32_t v_active_start; 280 uint32_t misc0 = 0; 281 uint32_t misc1 = 0; 282 uint32_t h_blank; 283 uint32_t h_back_porch; 284 uint8_t synchronous_clock = 0; /* asynchronous mode */ 285 uint8_t colorimetry_bpc; 286 uint8_t dynamic_range_rgb = 0; /*full range*/ 287 uint8_t dynamic_range_ycbcr = 1; /*bt709*/ 288 #endif 289 290 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 291 292 /* set pixel encoding */ 293 switch (crtc_timing->pixel_encoding) { 294 case PIXEL_ENCODING_YCBCR422: 295 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 296 DP_PIXEL_ENCODING_TYPE_YCBCR422); 297 break; 298 case PIXEL_ENCODING_YCBCR444: 299 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 300 DP_PIXEL_ENCODING_TYPE_YCBCR444); 301 302 if (crtc_timing->flags.Y_ONLY) 303 if (crtc_timing->display_color_depth != COLOR_DEPTH_666) 304 /* HW testing only, no use case yet. 305 * Color depth of Y-only could be 306 * 8, 10, 12, 16 bits */ 307 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 308 DP_PIXEL_ENCODING_TYPE_Y_ONLY); 309 /* Note: DP_MSA_MISC1 bit 7 is the indicator 310 * of Y-only mode. 311 * This bit is set in HW if register 312 * DP_PIXEL_ENCODING is programmed to 0x4 */ 313 break; 314 case PIXEL_ENCODING_YCBCR420: 315 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 316 DP_PIXEL_ENCODING_TYPE_YCBCR420); 317 if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN) 318 REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1); 319 320 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 321 if (enc110->se_mask->DP_VID_N_MUL) 322 REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1); 323 #endif 324 break; 325 default: 326 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 327 DP_PIXEL_ENCODING_TYPE_RGB444); 328 break; 329 } 330 331 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 332 if (REG(DP_MSA_MISC)) 333 misc1 = REG_READ(DP_MSA_MISC); 334 #endif 335 336 /* set color depth */ 337 338 switch (crtc_timing->display_color_depth) { 339 case COLOR_DEPTH_666: 340 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 341 0); 342 break; 343 case COLOR_DEPTH_888: 344 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 345 DP_COMPONENT_PIXEL_DEPTH_8BPC); 346 break; 347 case COLOR_DEPTH_101010: 348 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 349 DP_COMPONENT_PIXEL_DEPTH_10BPC); 350 351 break; 352 case COLOR_DEPTH_121212: 353 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 354 DP_COMPONENT_PIXEL_DEPTH_12BPC); 355 break; 356 default: 357 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 358 DP_COMPONENT_PIXEL_DEPTH_6BPC); 359 break; 360 } 361 362 /* set dynamic range and YCbCr range */ 363 364 365 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 366 switch (crtc_timing->display_color_depth) { 367 case COLOR_DEPTH_666: 368 colorimetry_bpc = 0; 369 break; 370 case COLOR_DEPTH_888: 371 colorimetry_bpc = 1; 372 break; 373 case COLOR_DEPTH_101010: 374 colorimetry_bpc = 2; 375 break; 376 case COLOR_DEPTH_121212: 377 colorimetry_bpc = 3; 378 break; 379 default: 380 colorimetry_bpc = 0; 381 break; 382 } 383 384 misc0 = misc0 | synchronous_clock; 385 misc0 = colorimetry_bpc << 5; 386 387 if (REG(DP_MSA_TIMING_PARAM1)) { 388 switch (output_color_space) { 389 case COLOR_SPACE_SRGB: 390 misc0 = misc0 | 0x0; 391 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 392 dynamic_range_rgb = 0; /*full range*/ 393 break; 394 case COLOR_SPACE_SRGB_LIMITED: 395 misc0 = misc0 | 0x8; /* bit3=1 */ 396 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 397 dynamic_range_rgb = 1; /*limited range*/ 398 break; 399 case COLOR_SPACE_YCBCR601: 400 case COLOR_SPACE_YCBCR601_LIMITED: 401 misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */ 402 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 403 dynamic_range_ycbcr = 0; /*bt601*/ 404 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) 405 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 406 else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) 407 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 408 break; 409 case COLOR_SPACE_YCBCR709: 410 case COLOR_SPACE_YCBCR709_LIMITED: 411 misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */ 412 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 413 dynamic_range_ycbcr = 1; /*bt709*/ 414 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) 415 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 416 else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) 417 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 418 break; 419 case COLOR_SPACE_2020_RGB_LIMITEDRANGE: 420 dynamic_range_rgb = 1; /*limited range*/ 421 break; 422 case COLOR_SPACE_2020_RGB_FULLRANGE: 423 case COLOR_SPACE_2020_YCBCR: 424 case COLOR_SPACE_XR_RGB: 425 case COLOR_SPACE_MSREF_SCRGB: 426 case COLOR_SPACE_ADOBERGB: 427 case COLOR_SPACE_DCIP3: 428 case COLOR_SPACE_XV_YCC_709: 429 case COLOR_SPACE_XV_YCC_601: 430 case COLOR_SPACE_DISPLAYNATIVE: 431 case COLOR_SPACE_DOLBYVISION: 432 case COLOR_SPACE_APPCTRL: 433 case COLOR_SPACE_CUSTOMPOINTS: 434 case COLOR_SPACE_UNKNOWN: 435 /* do nothing */ 436 break; 437 } 438 if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE) 439 REG_UPDATE_2( 440 DP_PIXEL_FORMAT, 441 DP_DYN_RANGE, dynamic_range_rgb, 442 DP_YCBCR_RANGE, dynamic_range_ycbcr); 443 444 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 445 if (REG(DP_MSA_COLORIMETRY)) 446 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); 447 448 if (REG(DP_MSA_MISC)) 449 REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */ 450 451 /* dcn new register 452 * dc_crtc_timing is vesa dmt struct. data from edid 453 */ 454 if (REG(DP_MSA_TIMING_PARAM1)) 455 REG_SET_2(DP_MSA_TIMING_PARAM1, 0, 456 DP_MSA_HTOTAL, crtc_timing->h_total, 457 DP_MSA_VTOTAL, crtc_timing->v_total); 458 #endif 459 460 /* calcuate from vesa timing parameters 461 * h_active_start related to leading edge of sync 462 */ 463 464 h_blank = crtc_timing->h_total - crtc_timing->h_border_left - 465 crtc_timing->h_addressable - crtc_timing->h_border_right; 466 467 h_back_porch = h_blank - crtc_timing->h_front_porch - 468 crtc_timing->h_sync_width; 469 470 /* start at begining of left border */ 471 h_active_start = crtc_timing->h_sync_width + h_back_porch; 472 473 474 v_active_start = crtc_timing->v_total - crtc_timing->v_border_top - 475 crtc_timing->v_addressable - crtc_timing->v_border_bottom - 476 crtc_timing->v_front_porch; 477 478 479 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 480 /* start at begining of left border */ 481 if (REG(DP_MSA_TIMING_PARAM2)) 482 REG_SET_2(DP_MSA_TIMING_PARAM2, 0, 483 DP_MSA_HSTART, h_active_start, 484 DP_MSA_VSTART, v_active_start); 485 486 if (REG(DP_MSA_TIMING_PARAM3)) 487 REG_SET_4(DP_MSA_TIMING_PARAM3, 0, 488 DP_MSA_HSYNCWIDTH, 489 crtc_timing->h_sync_width, 490 DP_MSA_HSYNCPOLARITY, 491 !crtc_timing->flags.HSYNC_POSITIVE_POLARITY, 492 DP_MSA_VSYNCWIDTH, 493 crtc_timing->v_sync_width, 494 DP_MSA_VSYNCPOLARITY, 495 !crtc_timing->flags.VSYNC_POSITIVE_POLARITY); 496 497 /* HWDITH include border or overscan */ 498 if (REG(DP_MSA_TIMING_PARAM4)) 499 REG_SET_2(DP_MSA_TIMING_PARAM4, 0, 500 DP_MSA_HWIDTH, crtc_timing->h_border_left + 501 crtc_timing->h_addressable + crtc_timing->h_border_right, 502 DP_MSA_VHEIGHT, crtc_timing->v_border_top + 503 crtc_timing->v_addressable + crtc_timing->v_border_bottom); 504 #endif 505 } 506 #endif 507 } 508 509 static void dce110_stream_encoder_set_stream_attribute_helper( 510 struct dce110_stream_encoder *enc110, 511 struct dc_crtc_timing *crtc_timing) 512 { 513 if (enc110->regs->TMDS_CNTL) { 514 switch (crtc_timing->pixel_encoding) { 515 case PIXEL_ENCODING_YCBCR422: 516 REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1); 517 break; 518 default: 519 REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0); 520 break; 521 } 522 REG_UPDATE(TMDS_CNTL, TMDS_COLOR_FORMAT, 0); 523 } else if (enc110->regs->DIG_FE_CNTL) { 524 switch (crtc_timing->pixel_encoding) { 525 case PIXEL_ENCODING_YCBCR422: 526 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1); 527 break; 528 default: 529 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0); 530 break; 531 } 532 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0); 533 } 534 535 } 536 537 /* setup stream encoder in hdmi mode */ 538 static void dce110_stream_encoder_hdmi_set_stream_attribute( 539 struct stream_encoder *enc, 540 struct dc_crtc_timing *crtc_timing, 541 int actual_pix_clk_khz, 542 bool enable_audio) 543 { 544 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 545 struct bp_encoder_control cntl = {0}; 546 547 cntl.action = ENCODER_CONTROL_SETUP; 548 cntl.engine_id = enc110->base.id; 549 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; 550 cntl.enable_dp_audio = enable_audio; 551 cntl.pixel_clock = actual_pix_clk_khz; 552 cntl.lanes_number = LANE_COUNT_FOUR; 553 554 if (enc110->base.bp->funcs->encoder_control( 555 enc110->base.bp, &cntl) != BP_RESULT_OK) 556 return; 557 558 dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing); 559 560 /* setup HDMI engine */ 561 if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) { 562 REG_UPDATE_3(HDMI_CONTROL, 563 HDMI_PACKET_GEN_VERSION, 1, 564 HDMI_KEEPOUT_MODE, 1, 565 HDMI_DEEP_COLOR_ENABLE, 0); 566 } else if (enc110->regs->DIG_FE_CNTL) { 567 REG_UPDATE_5(HDMI_CONTROL, 568 HDMI_PACKET_GEN_VERSION, 1, 569 HDMI_KEEPOUT_MODE, 1, 570 HDMI_DEEP_COLOR_ENABLE, 0, 571 HDMI_DATA_SCRAMBLE_EN, 0, 572 HDMI_CLOCK_CHANNEL_RATE, 0); 573 } 574 575 switch (crtc_timing->display_color_depth) { 576 case COLOR_DEPTH_888: 577 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 578 break; 579 case COLOR_DEPTH_101010: 580 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 581 REG_UPDATE_2(HDMI_CONTROL, 582 HDMI_DEEP_COLOR_DEPTH, 1, 583 HDMI_DEEP_COLOR_ENABLE, 0); 584 } else { 585 REG_UPDATE_2(HDMI_CONTROL, 586 HDMI_DEEP_COLOR_DEPTH, 1, 587 HDMI_DEEP_COLOR_ENABLE, 1); 588 } 589 break; 590 case COLOR_DEPTH_121212: 591 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 592 REG_UPDATE_2(HDMI_CONTROL, 593 HDMI_DEEP_COLOR_DEPTH, 2, 594 HDMI_DEEP_COLOR_ENABLE, 0); 595 } else { 596 REG_UPDATE_2(HDMI_CONTROL, 597 HDMI_DEEP_COLOR_DEPTH, 2, 598 HDMI_DEEP_COLOR_ENABLE, 1); 599 } 600 break; 601 case COLOR_DEPTH_161616: 602 REG_UPDATE_2(HDMI_CONTROL, 603 HDMI_DEEP_COLOR_DEPTH, 3, 604 HDMI_DEEP_COLOR_ENABLE, 1); 605 break; 606 default: 607 break; 608 } 609 610 if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) { 611 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) { 612 /* enable HDMI data scrambler 613 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M 614 * Clock channel frequency is 1/4 of character rate. 615 */ 616 REG_UPDATE_2(HDMI_CONTROL, 617 HDMI_DATA_SCRAMBLE_EN, 1, 618 HDMI_CLOCK_CHANNEL_RATE, 1); 619 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) { 620 621 /* TODO: New feature for DCE11, still need to implement */ 622 623 /* enable HDMI data scrambler 624 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE 625 * Clock channel frequency is the same 626 * as character rate 627 */ 628 REG_UPDATE_2(HDMI_CONTROL, 629 HDMI_DATA_SCRAMBLE_EN, 1, 630 HDMI_CLOCK_CHANNEL_RATE, 0); 631 } 632 } 633 634 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL, 635 HDMI_GC_CONT, 1, 636 HDMI_GC_SEND, 1, 637 HDMI_NULL_SEND, 1); 638 639 /* following belongs to audio */ 640 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 641 642 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 643 644 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 645 VBI_LINE_0 + 2); 646 647 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); 648 649 } 650 651 /* setup stream encoder in dvi mode */ 652 static void dce110_stream_encoder_dvi_set_stream_attribute( 653 struct stream_encoder *enc, 654 struct dc_crtc_timing *crtc_timing, 655 bool is_dual_link) 656 { 657 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 658 struct bp_encoder_control cntl = {0}; 659 660 cntl.action = ENCODER_CONTROL_SETUP; 661 cntl.engine_id = enc110->base.id; 662 cntl.signal = is_dual_link ? 663 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK; 664 cntl.enable_dp_audio = false; 665 cntl.pixel_clock = crtc_timing->pix_clk_khz; 666 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; 667 668 if (enc110->base.bp->funcs->encoder_control( 669 enc110->base.bp, &cntl) != BP_RESULT_OK) 670 return; 671 672 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); 673 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888); 674 dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing); 675 } 676 677 static void dce110_stream_encoder_set_mst_bandwidth( 678 struct stream_encoder *enc, 679 struct fixed31_32 avg_time_slots_per_mtp) 680 { 681 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 682 uint32_t x = dc_fixpt_floor( 683 avg_time_slots_per_mtp); 684 uint32_t y = dc_fixpt_ceil( 685 dc_fixpt_shl( 686 dc_fixpt_sub_int( 687 avg_time_slots_per_mtp, 688 x), 689 26)); 690 691 { 692 REG_SET_2(DP_MSE_RATE_CNTL, 0, 693 DP_MSE_RATE_X, x, 694 DP_MSE_RATE_Y, y); 695 } 696 697 /* wait for update to be completed on the link */ 698 /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */ 699 /* is reset to 0 (not pending) */ 700 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, 701 0, 702 10, DP_MST_UPDATE_MAX_RETRY); 703 } 704 705 static void dce110_stream_encoder_update_hdmi_info_packets( 706 struct stream_encoder *enc, 707 const struct encoder_info_frame *info_frame) 708 { 709 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 710 711 if (enc110->se_mask->HDMI_AVI_INFO_CONT && 712 enc110->se_mask->HDMI_AVI_INFO_SEND) { 713 714 if (info_frame->avi.valid) { 715 const uint32_t *content = 716 (const uint32_t *) &info_frame->avi.sb[0]; 717 /*we need turn on clock before programming AFMT block*/ 718 if (REG(AFMT_CNTL)) 719 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 720 721 REG_WRITE(AFMT_AVI_INFO0, content[0]); 722 723 REG_WRITE(AFMT_AVI_INFO1, content[1]); 724 725 REG_WRITE(AFMT_AVI_INFO2, content[2]); 726 727 REG_WRITE(AFMT_AVI_INFO3, content[3]); 728 729 REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, 730 info_frame->avi.hb1); 731 732 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0, 733 HDMI_AVI_INFO_SEND, 1, 734 HDMI_AVI_INFO_CONT, 1); 735 736 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 737 VBI_LINE_0 + 2); 738 739 } else { 740 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0, 741 HDMI_AVI_INFO_SEND, 0, 742 HDMI_AVI_INFO_CONT, 0); 743 } 744 } 745 746 if (enc110->se_mask->HDMI_AVI_INFO_CONT && 747 enc110->se_mask->HDMI_AVI_INFO_SEND) { 748 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor); 749 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut); 750 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd); 751 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd); 752 } 753 754 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 755 if (enc110->se_mask->HDMI_DB_DISABLE) { 756 /* for bring up, disable dp double TODO */ 757 if (REG(HDMI_DB_CONTROL)) 758 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); 759 760 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->avi); 761 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->vendor); 762 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->gamut); 763 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd); 764 dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd); 765 } 766 #endif 767 } 768 769 static void dce110_stream_encoder_stop_hdmi_info_packets( 770 struct stream_encoder *enc) 771 { 772 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 773 774 /* stop generic packets 0 & 1 on HDMI */ 775 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0, 776 HDMI_GENERIC1_CONT, 0, 777 HDMI_GENERIC1_LINE, 0, 778 HDMI_GENERIC1_SEND, 0, 779 HDMI_GENERIC0_CONT, 0, 780 HDMI_GENERIC0_LINE, 0, 781 HDMI_GENERIC0_SEND, 0); 782 783 /* stop generic packets 2 & 3 on HDMI */ 784 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0, 785 HDMI_GENERIC0_CONT, 0, 786 HDMI_GENERIC0_LINE, 0, 787 HDMI_GENERIC0_SEND, 0, 788 HDMI_GENERIC1_CONT, 0, 789 HDMI_GENERIC1_LINE, 0, 790 HDMI_GENERIC1_SEND, 0); 791 792 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 793 /* stop generic packets 2 & 3 on HDMI */ 794 if (REG(HDMI_GENERIC_PACKET_CONTROL2)) 795 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0, 796 HDMI_GENERIC0_CONT, 0, 797 HDMI_GENERIC0_LINE, 0, 798 HDMI_GENERIC0_SEND, 0, 799 HDMI_GENERIC1_CONT, 0, 800 HDMI_GENERIC1_LINE, 0, 801 HDMI_GENERIC1_SEND, 0); 802 803 if (REG(HDMI_GENERIC_PACKET_CONTROL3)) 804 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0, 805 HDMI_GENERIC0_CONT, 0, 806 HDMI_GENERIC0_LINE, 0, 807 HDMI_GENERIC0_SEND, 0, 808 HDMI_GENERIC1_CONT, 0, 809 HDMI_GENERIC1_LINE, 0, 810 HDMI_GENERIC1_SEND, 0); 811 #endif 812 } 813 814 static void dce110_stream_encoder_update_dp_info_packets( 815 struct stream_encoder *enc, 816 const struct encoder_info_frame *info_frame) 817 { 818 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 819 uint32_t value = 0; 820 821 if (info_frame->vsc.valid) 822 dce110_update_generic_info_packet( 823 enc110, 824 0, /* packetIndex */ 825 &info_frame->vsc); 826 827 if (info_frame->spd.valid) 828 dce110_update_generic_info_packet( 829 enc110, 830 2, /* packetIndex */ 831 &info_frame->spd); 832 833 if (info_frame->hdrsmd.valid) 834 dce110_update_generic_info_packet( 835 enc110, 836 3, /* packetIndex */ 837 &info_frame->hdrsmd); 838 839 /* enable/disable transmission of packet(s). 840 * If enabled, packet transmission begins on the next frame 841 */ 842 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); 843 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); 844 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); 845 846 /* This bit is the master enable bit. 847 * When enabling secondary stream engine, 848 * this master bit must also be set. 849 * This register shared with audio info frame. 850 * Therefore we need to enable master bit 851 * if at least on of the fields is not 0 852 */ 853 value = REG_READ(DP_SEC_CNTL); 854 if (value) 855 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 856 } 857 858 static void dce110_stream_encoder_stop_dp_info_packets( 859 struct stream_encoder *enc) 860 { 861 /* stop generic packets on DP */ 862 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 863 uint32_t value = 0; 864 865 if (enc110->se_mask->DP_SEC_AVI_ENABLE) { 866 REG_SET_7(DP_SEC_CNTL, 0, 867 DP_SEC_GSP0_ENABLE, 0, 868 DP_SEC_GSP1_ENABLE, 0, 869 DP_SEC_GSP2_ENABLE, 0, 870 DP_SEC_GSP3_ENABLE, 0, 871 DP_SEC_AVI_ENABLE, 0, 872 DP_SEC_MPG_ENABLE, 0, 873 DP_SEC_STREAM_ENABLE, 0); 874 } 875 876 /* this register shared with audio info frame. 877 * therefore we need to keep master enabled 878 * if at least one of the fields is not 0 */ 879 value = REG_READ(DP_SEC_CNTL); 880 if (value) 881 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 882 883 } 884 885 static void dce110_stream_encoder_dp_blank( 886 struct stream_encoder *enc) 887 { 888 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 889 uint32_t retries = 0; 890 uint32_t reg1 = 0; 891 uint32_t max_retries = DP_BLANK_MAX_RETRY * 10; 892 893 /* Note: For CZ, we are changing driver default to disable 894 * stream deferred to next VBLANK. If results are positive, we 895 * will make the same change to all DCE versions. There are a 896 * handful of panels that cannot handle disable stream at 897 * HBLANK and will result in a white line flash across the 898 * screen on stream disable. */ 899 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1); 900 if ((reg1 & 0x1) == 0) 901 /*stream not enabled*/ 902 return; 903 /* Specify the video stream disable point 904 * (2 = start of the next vertical blank) */ 905 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2); 906 /* Larger delay to wait until VBLANK - use max retry of 907 * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode + 908 * a little more because we may not trust delay accuracy. 909 */ 910 max_retries = DP_BLANK_MAX_RETRY * 150; 911 912 /* disable DP stream */ 913 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); 914 915 /* the encoder stops sending the video stream 916 * at the start of the vertical blanking. 917 * Poll for DP_VID_STREAM_STATUS == 0 918 */ 919 920 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 921 0, 922 10, max_retries); 923 924 ASSERT(retries <= max_retries); 925 926 /* Tell the DP encoder to ignore timing from CRTC, must be done after 927 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is 928 * complete, stream status will be stuck in video stream enabled state, 929 * i.e. DP_VID_STREAM_STATUS stuck at 1. 930 */ 931 932 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true); 933 } 934 935 /* output video stream to link encoder */ 936 static void dce110_stream_encoder_dp_unblank( 937 struct stream_encoder *enc, 938 const struct encoder_unblank_param *param) 939 { 940 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 941 942 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { 943 uint32_t n_vid = 0x8000; 944 uint32_t m_vid; 945 946 /* M / N = Fstream / Flink 947 * m_vid / n_vid = pixel rate / link rate 948 */ 949 950 uint64_t m_vid_l = n_vid; 951 952 m_vid_l *= param->pixel_clk_khz; 953 m_vid_l = div_u64(m_vid_l, 954 param->link_settings.link_rate 955 * LINK_RATE_REF_FREQ_IN_KHZ); 956 957 m_vid = (uint32_t) m_vid_l; 958 959 /* enable auto measurement */ 960 961 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0); 962 963 /* auto measurement need 1 full 0x8000 symbol cycle to kick in, 964 * therefore program initial value for Mvid and Nvid 965 */ 966 967 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid); 968 969 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid); 970 971 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1); 972 } 973 974 /* set DIG_START to 0x1 to resync FIFO */ 975 976 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); 977 978 /* switch DP encoder to CRTC data */ 979 980 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); 981 982 /* wait 100us for DIG/DP logic to prime 983 * (i.e. a few video lines) 984 */ 985 udelay(100); 986 987 /* the hardware would start sending video at the start of the next DP 988 * frame (i.e. rising edge of the vblank). 989 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this 990 * register has no effect on enable transition! HW always guarantees 991 * VID_STREAM enable at start of next frame, and this is not 992 * programmable 993 */ 994 995 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); 996 } 997 998 static void dce110_stream_encoder_set_avmute( 999 struct stream_encoder *enc, 1000 bool enable) 1001 { 1002 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1003 unsigned int value = enable ? 1 : 0; 1004 1005 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value); 1006 } 1007 1008 1009 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000 1010 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1 1011 1012 #include "include/audio_types.h" 1013 1014 /** 1015 * speakersToChannels 1016 * 1017 * @brief 1018 * translate speakers to channels 1019 * 1020 * FL - Front Left 1021 * FR - Front Right 1022 * RL - Rear Left 1023 * RR - Rear Right 1024 * RC - Rear Center 1025 * FC - Front Center 1026 * FLC - Front Left Center 1027 * FRC - Front Right Center 1028 * RLC - Rear Left Center 1029 * RRC - Rear Right Center 1030 * LFE - Low Freq Effect 1031 * 1032 * FC 1033 * FLC FRC 1034 * FL FR 1035 * 1036 * LFE 1037 * () 1038 * 1039 * 1040 * RL RR 1041 * RLC RRC 1042 * RC 1043 * 1044 * ch 8 7 6 5 4 3 2 1 1045 * 0b00000011 - - - - - - FR FL 1046 * 0b00000111 - - - - - LFE FR FL 1047 * 0b00001011 - - - - FC - FR FL 1048 * 0b00001111 - - - - FC LFE FR FL 1049 * 0b00010011 - - - RC - - FR FL 1050 * 0b00010111 - - - RC - LFE FR FL 1051 * 0b00011011 - - - RC FC - FR FL 1052 * 0b00011111 - - - RC FC LFE FR FL 1053 * 0b00110011 - - RR RL - - FR FL 1054 * 0b00110111 - - RR RL - LFE FR FL 1055 * 0b00111011 - - RR RL FC - FR FL 1056 * 0b00111111 - - RR RL FC LFE FR FL 1057 * 0b01110011 - RC RR RL - - FR FL 1058 * 0b01110111 - RC RR RL - LFE FR FL 1059 * 0b01111011 - RC RR RL FC - FR FL 1060 * 0b01111111 - RC RR RL FC LFE FR FL 1061 * 0b11110011 RRC RLC RR RL - - FR FL 1062 * 0b11110111 RRC RLC RR RL - LFE FR FL 1063 * 0b11111011 RRC RLC RR RL FC - FR FL 1064 * 0b11111111 RRC RLC RR RL FC LFE FR FL 1065 * 0b11000011 FRC FLC - - - - FR FL 1066 * 0b11000111 FRC FLC - - - LFE FR FL 1067 * 0b11001011 FRC FLC - - FC - FR FL 1068 * 0b11001111 FRC FLC - - FC LFE FR FL 1069 * 0b11010011 FRC FLC - RC - - FR FL 1070 * 0b11010111 FRC FLC - RC - LFE FR FL 1071 * 0b11011011 FRC FLC - RC FC - FR FL 1072 * 0b11011111 FRC FLC - RC FC LFE FR FL 1073 * 0b11110011 FRC FLC RR RL - - FR FL 1074 * 0b11110111 FRC FLC RR RL - LFE FR FL 1075 * 0b11111011 FRC FLC RR RL FC - FR FL 1076 * 0b11111111 FRC FLC RR RL FC LFE FR FL 1077 * 1078 * @param 1079 * speakers - speaker information as it comes from CEA audio block 1080 */ 1081 /* translate speakers to channels */ 1082 1083 union audio_cea_channels { 1084 uint8_t all; 1085 struct audio_cea_channels_bits { 1086 uint32_t FL:1; 1087 uint32_t FR:1; 1088 uint32_t LFE:1; 1089 uint32_t FC:1; 1090 uint32_t RL_RC:1; 1091 uint32_t RR:1; 1092 uint32_t RC_RLC_FLC:1; 1093 uint32_t RRC_FRC:1; 1094 } channels; 1095 }; 1096 1097 struct audio_clock_info { 1098 /* pixel clock frequency*/ 1099 uint32_t pixel_clock_in_10khz; 1100 /* N - 32KHz audio */ 1101 uint32_t n_32khz; 1102 /* CTS - 32KHz audio*/ 1103 uint32_t cts_32khz; 1104 uint32_t n_44khz; 1105 uint32_t cts_44khz; 1106 uint32_t n_48khz; 1107 uint32_t cts_48khz; 1108 }; 1109 1110 /* 25.2MHz/1.001*/ 1111 /* 25.2MHz/1.001*/ 1112 /* 25.2MHz*/ 1113 /* 27MHz */ 1114 /* 27MHz*1.001*/ 1115 /* 27MHz*1.001*/ 1116 /* 54MHz*/ 1117 /* 54MHz*1.001*/ 1118 /* 74.25MHz/1.001*/ 1119 /* 74.25MHz*/ 1120 /* 148.5MHz/1.001*/ 1121 /* 148.5MHz*/ 1122 1123 static const struct audio_clock_info audio_clock_info_table[16] = { 1124 {2517, 4576, 28125, 7007, 31250, 6864, 28125}, 1125 {2518, 4576, 28125, 7007, 31250, 6864, 28125}, 1126 {2520, 4096, 25200, 6272, 28000, 6144, 25200}, 1127 {2700, 4096, 27000, 6272, 30000, 6144, 27000}, 1128 {2702, 4096, 27027, 6272, 30030, 6144, 27027}, 1129 {2703, 4096, 27027, 6272, 30030, 6144, 27027}, 1130 {5400, 4096, 54000, 6272, 60000, 6144, 54000}, 1131 {5405, 4096, 54054, 6272, 60060, 6144, 54054}, 1132 {7417, 11648, 210937, 17836, 234375, 11648, 140625}, 1133 {7425, 4096, 74250, 6272, 82500, 6144, 74250}, 1134 {14835, 11648, 421875, 8918, 234375, 5824, 140625}, 1135 {14850, 4096, 148500, 6272, 165000, 6144, 148500}, 1136 {29670, 5824, 421875, 4459, 234375, 5824, 281250}, 1137 {29700, 3072, 222750, 4704, 247500, 5120, 247500}, 1138 {59340, 5824, 843750, 8918, 937500, 5824, 562500}, 1139 {59400, 3072, 445500, 9408, 990000, 6144, 594000} 1140 }; 1141 1142 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = { 1143 {2517, 9152, 84375, 7007, 48875, 9152, 56250}, 1144 {2518, 9152, 84375, 7007, 48875, 9152, 56250}, 1145 {2520, 4096, 37800, 6272, 42000, 6144, 37800}, 1146 {2700, 4096, 40500, 6272, 45000, 6144, 40500}, 1147 {2702, 8192, 81081, 6272, 45045, 8192, 54054}, 1148 {2703, 8192, 81081, 6272, 45045, 8192, 54054}, 1149 {5400, 4096, 81000, 6272, 90000, 6144, 81000}, 1150 {5405, 4096, 81081, 6272, 90090, 6144, 81081}, 1151 {7417, 11648, 316406, 17836, 351562, 11648, 210937}, 1152 {7425, 4096, 111375, 6272, 123750, 6144, 111375}, 1153 {14835, 11648, 632812, 17836, 703125, 11648, 421875}, 1154 {14850, 4096, 222750, 6272, 247500, 6144, 222750}, 1155 {29670, 5824, 632812, 8918, 703125, 5824, 421875}, 1156 {29700, 4096, 445500, 4704, 371250, 5120, 371250} 1157 }; 1158 1159 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = { 1160 {2517, 4576, 56250, 7007, 62500, 6864, 56250}, 1161 {2518, 4576, 56250, 7007, 62500, 6864, 56250}, 1162 {2520, 4096, 50400, 6272, 56000, 6144, 50400}, 1163 {2700, 4096, 54000, 6272, 60000, 6144, 54000}, 1164 {2702, 4096, 54054, 6267, 60060, 8192, 54054}, 1165 {2703, 4096, 54054, 6272, 60060, 8192, 54054}, 1166 {5400, 4096, 108000, 6272, 120000, 6144, 108000}, 1167 {5405, 4096, 108108, 6272, 120120, 6144, 108108}, 1168 {7417, 11648, 421875, 17836, 468750, 11648, 281250}, 1169 {7425, 4096, 148500, 6272, 165000, 6144, 148500}, 1170 {14835, 11648, 843750, 8918, 468750, 11648, 281250}, 1171 {14850, 4096, 297000, 6272, 330000, 6144, 297000}, 1172 {29670, 5824, 843750, 4459, 468750, 5824, 562500}, 1173 {29700, 3072, 445500, 4704, 495000, 5120, 495000} 1174 1175 1176 }; 1177 1178 static union audio_cea_channels speakers_to_channels( 1179 struct audio_speaker_flags speaker_flags) 1180 { 1181 union audio_cea_channels cea_channels = {0}; 1182 1183 /* these are one to one */ 1184 cea_channels.channels.FL = speaker_flags.FL_FR; 1185 cea_channels.channels.FR = speaker_flags.FL_FR; 1186 cea_channels.channels.LFE = speaker_flags.LFE; 1187 cea_channels.channels.FC = speaker_flags.FC; 1188 1189 /* if Rear Left and Right exist move RC speaker to channel 7 1190 * otherwise to channel 5 1191 */ 1192 if (speaker_flags.RL_RR) { 1193 cea_channels.channels.RL_RC = speaker_flags.RL_RR; 1194 cea_channels.channels.RR = speaker_flags.RL_RR; 1195 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC; 1196 } else { 1197 cea_channels.channels.RL_RC = speaker_flags.RC; 1198 } 1199 1200 /* FRONT Left Right Center and REAR Left Right Center are exclusive */ 1201 if (speaker_flags.FLC_FRC) { 1202 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC; 1203 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC; 1204 } else { 1205 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC; 1206 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC; 1207 } 1208 1209 return cea_channels; 1210 } 1211 1212 static uint32_t calc_max_audio_packets_per_line( 1213 const struct audio_crtc_info *crtc_info) 1214 { 1215 uint32_t max_packets_per_line; 1216 1217 max_packets_per_line = 1218 crtc_info->h_total - crtc_info->h_active; 1219 1220 if (crtc_info->pixel_repetition) 1221 max_packets_per_line *= crtc_info->pixel_repetition; 1222 1223 /* for other hdmi features */ 1224 max_packets_per_line -= 58; 1225 /* for Control Period */ 1226 max_packets_per_line -= 16; 1227 /* Number of Audio Packets per Line */ 1228 max_packets_per_line /= 32; 1229 1230 return max_packets_per_line; 1231 } 1232 1233 static void get_audio_clock_info( 1234 enum dc_color_depth color_depth, 1235 uint32_t crtc_pixel_clock_in_khz, 1236 uint32_t actual_pixel_clock_in_khz, 1237 struct audio_clock_info *audio_clock_info) 1238 { 1239 const struct audio_clock_info *clock_info; 1240 uint32_t index; 1241 uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10; 1242 uint32_t audio_array_size; 1243 1244 switch (color_depth) { 1245 case COLOR_DEPTH_161616: 1246 clock_info = audio_clock_info_table_48bpc; 1247 audio_array_size = ARRAY_SIZE( 1248 audio_clock_info_table_48bpc); 1249 break; 1250 case COLOR_DEPTH_121212: 1251 clock_info = audio_clock_info_table_36bpc; 1252 audio_array_size = ARRAY_SIZE( 1253 audio_clock_info_table_36bpc); 1254 break; 1255 default: 1256 clock_info = audio_clock_info_table; 1257 audio_array_size = ARRAY_SIZE( 1258 audio_clock_info_table); 1259 break; 1260 } 1261 1262 if (clock_info != NULL) { 1263 /* search for exact pixel clock in table */ 1264 for (index = 0; index < audio_array_size; index++) { 1265 if (clock_info[index].pixel_clock_in_10khz > 1266 crtc_pixel_clock_in_10khz) 1267 break; /* not match */ 1268 else if (clock_info[index].pixel_clock_in_10khz == 1269 crtc_pixel_clock_in_10khz) { 1270 /* match found */ 1271 *audio_clock_info = clock_info[index]; 1272 return; 1273 } 1274 } 1275 } 1276 1277 /* not found */ 1278 if (actual_pixel_clock_in_khz == 0) 1279 actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz; 1280 1281 /* See HDMI spec the table entry under 1282 * pixel clock of "Other". */ 1283 audio_clock_info->pixel_clock_in_10khz = 1284 actual_pixel_clock_in_khz / 10; 1285 audio_clock_info->cts_32khz = actual_pixel_clock_in_khz; 1286 audio_clock_info->cts_44khz = actual_pixel_clock_in_khz; 1287 audio_clock_info->cts_48khz = actual_pixel_clock_in_khz; 1288 1289 audio_clock_info->n_32khz = 4096; 1290 audio_clock_info->n_44khz = 6272; 1291 audio_clock_info->n_48khz = 6144; 1292 } 1293 1294 static void dce110_se_audio_setup( 1295 struct stream_encoder *enc, 1296 unsigned int az_inst, 1297 struct audio_info *audio_info) 1298 { 1299 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1300 1301 uint32_t speakers = 0; 1302 uint32_t channels = 0; 1303 1304 ASSERT(audio_info); 1305 if (audio_info == NULL) 1306 /* This should not happen.it does so we don't get BSOD*/ 1307 return; 1308 1309 speakers = audio_info->flags.info.ALLSPEAKERS; 1310 channels = speakers_to_channels(audio_info->flags.speaker_flags).all; 1311 1312 /* setup the audio stream source select (audio -> dig mapping) */ 1313 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); 1314 1315 /* Channel allocation */ 1316 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels); 1317 } 1318 1319 static void dce110_se_setup_hdmi_audio( 1320 struct stream_encoder *enc, 1321 const struct audio_crtc_info *crtc_info) 1322 { 1323 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1324 1325 struct audio_clock_info audio_clock_info = {0}; 1326 uint32_t max_packets_per_line; 1327 1328 /* For now still do calculation, although this field is ignored when 1329 above HDMI_PACKET_GEN_VERSION set to 1 */ 1330 max_packets_per_line = calc_max_audio_packets_per_line(crtc_info); 1331 1332 /* HDMI_AUDIO_PACKET_CONTROL */ 1333 REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL, 1334 HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line, 1335 HDMI_AUDIO_DELAY_EN, 1); 1336 1337 /* AFMT_AUDIO_PACKET_CONTROL */ 1338 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1339 1340 /* AFMT_AUDIO_PACKET_CONTROL2 */ 1341 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 1342 AFMT_AUDIO_LAYOUT_OVRD, 0, 1343 AFMT_60958_OSF_OVRD, 0); 1344 1345 /* HDMI_ACR_PACKET_CONTROL */ 1346 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, 1347 HDMI_ACR_AUTO_SEND, 1, 1348 HDMI_ACR_SOURCE, 0, 1349 HDMI_ACR_AUDIO_PRIORITY, 0); 1350 1351 /* Program audio clock sample/regeneration parameters */ 1352 get_audio_clock_info(crtc_info->color_depth, 1353 crtc_info->requested_pixel_clock, 1354 crtc_info->calculated_pixel_clock, 1355 &audio_clock_info); 1356 DC_LOG_HW_AUDIO( 1357 "\n%s:Input::requested_pixel_clock = %d" \ 1358 "calculated_pixel_clock = %d \n", __func__, \ 1359 crtc_info->requested_pixel_clock, \ 1360 crtc_info->calculated_pixel_clock); 1361 1362 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */ 1363 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); 1364 1365 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */ 1366 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); 1367 1368 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */ 1369 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); 1370 1371 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */ 1372 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); 1373 1374 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */ 1375 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); 1376 1377 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */ 1378 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz); 1379 1380 /* Video driver cannot know in advance which sample rate will 1381 be used by HD Audio driver 1382 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is 1383 programmed below in interruppt callback */ 1384 1385 /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK & 1386 AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */ 1387 REG_UPDATE_2(AFMT_60958_0, 1388 AFMT_60958_CS_CHANNEL_NUMBER_L, 1, 1389 AFMT_60958_CS_CLOCK_ACCURACY, 0); 1390 1391 /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */ 1392 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1393 1394 /*AFMT_60958_2 now keep this settings until 1395 * Programming guide comes out*/ 1396 REG_UPDATE_6(AFMT_60958_2, 1397 AFMT_60958_CS_CHANNEL_NUMBER_2, 3, 1398 AFMT_60958_CS_CHANNEL_NUMBER_3, 4, 1399 AFMT_60958_CS_CHANNEL_NUMBER_4, 5, 1400 AFMT_60958_CS_CHANNEL_NUMBER_5, 6, 1401 AFMT_60958_CS_CHANNEL_NUMBER_6, 7, 1402 AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1403 } 1404 1405 static void dce110_se_setup_dp_audio( 1406 struct stream_encoder *enc) 1407 { 1408 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1409 1410 /* --- DP Audio packet configurations --- */ 1411 1412 /* ATP Configuration */ 1413 REG_SET(DP_SEC_AUD_N, 0, 1414 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT); 1415 1416 /* Async/auto-calc timestamp mode */ 1417 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE, 1418 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC); 1419 1420 /* --- The following are the registers 1421 * copied from the SetupHDMI --- */ 1422 1423 /* AFMT_AUDIO_PACKET_CONTROL */ 1424 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1425 1426 /* AFMT_AUDIO_PACKET_CONTROL2 */ 1427 /* Program the ATP and AIP next */ 1428 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 1429 AFMT_AUDIO_LAYOUT_OVRD, 0, 1430 AFMT_60958_OSF_OVRD, 0); 1431 1432 /* AFMT_INFOFRAME_CONTROL0 */ 1433 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1434 1435 /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */ 1436 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0); 1437 } 1438 1439 static void dce110_se_enable_audio_clock( 1440 struct stream_encoder *enc, 1441 bool enable) 1442 { 1443 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1444 1445 if (REG(AFMT_CNTL) == 0) 1446 return; /* DCE8/10 does not have this register */ 1447 1448 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable); 1449 1450 /* wait for AFMT clock to turn on, 1451 * expectation: this should complete in 1-2 reads 1452 * 1453 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10); 1454 * 1455 * TODO: wait for clock_on does not work well. May need HW 1456 * program sequence. But audio seems work normally even without wait 1457 * for clock_on status change 1458 */ 1459 } 1460 1461 static void dce110_se_enable_dp_audio( 1462 struct stream_encoder *enc) 1463 { 1464 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1465 1466 /* Enable Audio packets */ 1467 REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); 1468 1469 /* Program the ATP and AIP next */ 1470 REG_UPDATE_2(DP_SEC_CNTL, 1471 DP_SEC_ATP_ENABLE, 1, 1472 DP_SEC_AIP_ENABLE, 1); 1473 1474 /* Program STREAM_ENABLE after all the other enables. */ 1475 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1476 } 1477 1478 static void dce110_se_disable_dp_audio( 1479 struct stream_encoder *enc) 1480 { 1481 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1482 uint32_t value = 0; 1483 1484 /* Disable Audio packets */ 1485 REG_UPDATE_5(DP_SEC_CNTL, 1486 DP_SEC_ASP_ENABLE, 0, 1487 DP_SEC_ATP_ENABLE, 0, 1488 DP_SEC_AIP_ENABLE, 0, 1489 DP_SEC_ACM_ENABLE, 0, 1490 DP_SEC_STREAM_ENABLE, 0); 1491 1492 /* This register shared with encoder info frame. Therefore we need to 1493 keep master enabled if at least on of the fields is not 0 */ 1494 value = REG_READ(DP_SEC_CNTL); 1495 if (value != 0) 1496 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1497 1498 } 1499 1500 void dce110_se_audio_mute_control( 1501 struct stream_encoder *enc, 1502 bool mute) 1503 { 1504 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1505 1506 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute); 1507 } 1508 1509 void dce110_se_dp_audio_setup( 1510 struct stream_encoder *enc, 1511 unsigned int az_inst, 1512 struct audio_info *info) 1513 { 1514 dce110_se_audio_setup(enc, az_inst, info); 1515 } 1516 1517 void dce110_se_dp_audio_enable( 1518 struct stream_encoder *enc) 1519 { 1520 dce110_se_enable_audio_clock(enc, true); 1521 dce110_se_setup_dp_audio(enc); 1522 dce110_se_enable_dp_audio(enc); 1523 } 1524 1525 void dce110_se_dp_audio_disable( 1526 struct stream_encoder *enc) 1527 { 1528 dce110_se_disable_dp_audio(enc); 1529 dce110_se_enable_audio_clock(enc, false); 1530 } 1531 1532 void dce110_se_hdmi_audio_setup( 1533 struct stream_encoder *enc, 1534 unsigned int az_inst, 1535 struct audio_info *info, 1536 struct audio_crtc_info *audio_crtc_info) 1537 { 1538 dce110_se_enable_audio_clock(enc, true); 1539 dce110_se_setup_hdmi_audio(enc, audio_crtc_info); 1540 dce110_se_audio_setup(enc, az_inst, info); 1541 } 1542 1543 void dce110_se_hdmi_audio_disable( 1544 struct stream_encoder *enc) 1545 { 1546 dce110_se_enable_audio_clock(enc, false); 1547 } 1548 1549 1550 static void setup_stereo_sync( 1551 struct stream_encoder *enc, 1552 int tg_inst, bool enable) 1553 { 1554 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1555 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); 1556 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable); 1557 } 1558 1559 1560 static const struct stream_encoder_funcs dce110_str_enc_funcs = { 1561 .dp_set_stream_attribute = 1562 dce110_stream_encoder_dp_set_stream_attribute, 1563 .hdmi_set_stream_attribute = 1564 dce110_stream_encoder_hdmi_set_stream_attribute, 1565 .dvi_set_stream_attribute = 1566 dce110_stream_encoder_dvi_set_stream_attribute, 1567 .set_mst_bandwidth = 1568 dce110_stream_encoder_set_mst_bandwidth, 1569 .update_hdmi_info_packets = 1570 dce110_stream_encoder_update_hdmi_info_packets, 1571 .stop_hdmi_info_packets = 1572 dce110_stream_encoder_stop_hdmi_info_packets, 1573 .update_dp_info_packets = 1574 dce110_stream_encoder_update_dp_info_packets, 1575 .stop_dp_info_packets = 1576 dce110_stream_encoder_stop_dp_info_packets, 1577 .dp_blank = 1578 dce110_stream_encoder_dp_blank, 1579 .dp_unblank = 1580 dce110_stream_encoder_dp_unblank, 1581 .audio_mute_control = dce110_se_audio_mute_control, 1582 1583 .dp_audio_setup = dce110_se_dp_audio_setup, 1584 .dp_audio_enable = dce110_se_dp_audio_enable, 1585 .dp_audio_disable = dce110_se_dp_audio_disable, 1586 1587 .hdmi_audio_setup = dce110_se_hdmi_audio_setup, 1588 .hdmi_audio_disable = dce110_se_hdmi_audio_disable, 1589 .setup_stereo_sync = setup_stereo_sync, 1590 .set_avmute = dce110_stream_encoder_set_avmute, 1591 1592 }; 1593 1594 void dce110_stream_encoder_construct( 1595 struct dce110_stream_encoder *enc110, 1596 struct dc_context *ctx, 1597 struct dc_bios *bp, 1598 enum engine_id eng_id, 1599 const struct dce110_stream_enc_registers *regs, 1600 const struct dce_stream_encoder_shift *se_shift, 1601 const struct dce_stream_encoder_mask *se_mask) 1602 { 1603 enc110->base.funcs = &dce110_str_enc_funcs; 1604 enc110->base.ctx = ctx; 1605 enc110->base.id = eng_id; 1606 enc110->base.bp = bp; 1607 enc110->regs = regs; 1608 enc110->se_shift = se_shift; 1609 enc110->se_mask = se_mask; 1610 } 1611