1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/delay.h> 27 28 #include "dc_bios_types.h" 29 #include "dce_stream_encoder.h" 30 #include "reg_helper.h" 31 #include "hw_shared.h" 32 33 #define DC_LOGGER \ 34 enc110->base.ctx->logger 35 36 37 #define REG(reg)\ 38 (enc110->regs->reg) 39 40 #undef FN 41 #define FN(reg_name, field_name) \ 42 enc110->se_shift->field_name, enc110->se_mask->field_name 43 44 #define VBI_LINE_0 0 45 #define DP_BLANK_MAX_RETRY 20 46 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 47 48 #ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 49 #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x00000010L 50 #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x00000300L 51 #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x00000004 52 #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x00000008 53 #endif 54 55 enum { 56 DP_MST_UPDATE_MAX_RETRY = 50 57 }; 58 59 #define DCE110_SE(audio)\ 60 container_of(audio, struct dce110_stream_encoder, base) 61 62 #define CTX \ 63 enc110->base.ctx 64 65 static void dce110_update_generic_info_packet( 66 struct dce110_stream_encoder *enc110, 67 uint32_t packet_index, 68 const struct dc_info_packet *info_packet) 69 { 70 /* TODOFPGA Figure out a proper number for max_retries polling for lock 71 * use 50 for now. 72 */ 73 uint32_t max_retries = 50; 74 75 /*we need turn on clock before programming AFMT block*/ 76 if (REG(AFMT_CNTL)) 77 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 78 79 if (REG(AFMT_VBI_PACKET_CONTROL1)) { 80 if (packet_index >= 8) 81 ASSERT(0); 82 83 /* poll dig_update_lock is not locked -> asic internal signal 84 * assume otg master lock will unlock it 85 */ 86 /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, 87 0, 10, max_retries);*/ 88 89 /* check if HW reading GSP memory */ 90 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, 91 0, 10, max_retries); 92 93 /* HW does is not reading GSP memory not reading too long -> 94 * something wrong. clear GPS memory access and notify? 95 * hw SW is writing to GSP memory 96 */ 97 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); 98 } 99 /* choose which generic packet to use */ 100 { 101 REG_READ(AFMT_VBI_PACKET_CONTROL); 102 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, 103 AFMT_GENERIC_INDEX, packet_index); 104 } 105 106 /* write generic packet header 107 * (4th byte is for GENERIC0 only) */ 108 { 109 REG_SET_4(AFMT_GENERIC_HDR, 0, 110 AFMT_GENERIC_HB0, info_packet->hb0, 111 AFMT_GENERIC_HB1, info_packet->hb1, 112 AFMT_GENERIC_HB2, info_packet->hb2, 113 AFMT_GENERIC_HB3, info_packet->hb3); 114 } 115 116 /* write generic packet contents 117 * (we never use last 4 bytes) 118 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers */ 119 { 120 const uint32_t *content = 121 (const uint32_t *) &info_packet->sb[0]; 122 123 REG_WRITE(AFMT_GENERIC_0, *content++); 124 REG_WRITE(AFMT_GENERIC_1, *content++); 125 REG_WRITE(AFMT_GENERIC_2, *content++); 126 REG_WRITE(AFMT_GENERIC_3, *content++); 127 REG_WRITE(AFMT_GENERIC_4, *content++); 128 REG_WRITE(AFMT_GENERIC_5, *content++); 129 REG_WRITE(AFMT_GENERIC_6, *content++); 130 REG_WRITE(AFMT_GENERIC_7, *content); 131 } 132 133 if (!REG(AFMT_VBI_PACKET_CONTROL1)) { 134 /* force double-buffered packet update */ 135 REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL, 136 AFMT_GENERIC0_UPDATE, (packet_index == 0), 137 AFMT_GENERIC2_UPDATE, (packet_index == 2)); 138 } 139 #if defined(CONFIG_DRM_AMD_DC_DCN) 140 if (REG(AFMT_VBI_PACKET_CONTROL1)) { 141 switch (packet_index) { 142 case 0: 143 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 144 AFMT_GENERIC0_FRAME_UPDATE, 1); 145 break; 146 case 1: 147 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 148 AFMT_GENERIC1_FRAME_UPDATE, 1); 149 break; 150 case 2: 151 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 152 AFMT_GENERIC2_FRAME_UPDATE, 1); 153 break; 154 case 3: 155 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 156 AFMT_GENERIC3_FRAME_UPDATE, 1); 157 break; 158 case 4: 159 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 160 AFMT_GENERIC4_FRAME_UPDATE, 1); 161 break; 162 case 5: 163 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 164 AFMT_GENERIC5_FRAME_UPDATE, 1); 165 break; 166 case 6: 167 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 168 AFMT_GENERIC6_FRAME_UPDATE, 1); 169 break; 170 case 7: 171 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 172 AFMT_GENERIC7_FRAME_UPDATE, 1); 173 break; 174 default: 175 break; 176 } 177 } 178 #endif 179 } 180 181 static void dce110_update_hdmi_info_packet( 182 struct dce110_stream_encoder *enc110, 183 uint32_t packet_index, 184 const struct dc_info_packet *info_packet) 185 { 186 uint32_t cont, send, line; 187 188 if (info_packet->valid) { 189 dce110_update_generic_info_packet( 190 enc110, 191 packet_index, 192 info_packet); 193 194 /* enable transmission of packet(s) - 195 * packet transmission begins on the next frame */ 196 cont = 1; 197 /* send packet(s) every frame */ 198 send = 1; 199 /* select line number to send packets on */ 200 line = 2; 201 } else { 202 cont = 0; 203 send = 0; 204 line = 0; 205 } 206 207 /* choose which generic packet control to use */ 208 switch (packet_index) { 209 case 0: 210 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 211 HDMI_GENERIC0_CONT, cont, 212 HDMI_GENERIC0_SEND, send, 213 HDMI_GENERIC0_LINE, line); 214 break; 215 case 1: 216 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 217 HDMI_GENERIC1_CONT, cont, 218 HDMI_GENERIC1_SEND, send, 219 HDMI_GENERIC1_LINE, line); 220 break; 221 case 2: 222 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 223 HDMI_GENERIC0_CONT, cont, 224 HDMI_GENERIC0_SEND, send, 225 HDMI_GENERIC0_LINE, line); 226 break; 227 case 3: 228 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 229 HDMI_GENERIC1_CONT, cont, 230 HDMI_GENERIC1_SEND, send, 231 HDMI_GENERIC1_LINE, line); 232 break; 233 #if defined(CONFIG_DRM_AMD_DC_DCN) 234 case 4: 235 if (REG(HDMI_GENERIC_PACKET_CONTROL2)) 236 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 237 HDMI_GENERIC0_CONT, cont, 238 HDMI_GENERIC0_SEND, send, 239 HDMI_GENERIC0_LINE, line); 240 break; 241 case 5: 242 if (REG(HDMI_GENERIC_PACKET_CONTROL2)) 243 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 244 HDMI_GENERIC1_CONT, cont, 245 HDMI_GENERIC1_SEND, send, 246 HDMI_GENERIC1_LINE, line); 247 break; 248 case 6: 249 if (REG(HDMI_GENERIC_PACKET_CONTROL3)) 250 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 251 HDMI_GENERIC0_CONT, cont, 252 HDMI_GENERIC0_SEND, send, 253 HDMI_GENERIC0_LINE, line); 254 break; 255 case 7: 256 if (REG(HDMI_GENERIC_PACKET_CONTROL3)) 257 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 258 HDMI_GENERIC1_CONT, cont, 259 HDMI_GENERIC1_SEND, send, 260 HDMI_GENERIC1_LINE, line); 261 break; 262 #endif 263 default: 264 /* invalid HW packet index */ 265 DC_LOG_WARNING( 266 "Invalid HW packet index: %s()\n", 267 __func__); 268 return; 269 } 270 } 271 272 /* setup stream encoder in dp mode */ 273 static void dce110_stream_encoder_dp_set_stream_attribute( 274 struct stream_encoder *enc, 275 struct dc_crtc_timing *crtc_timing, 276 enum dc_color_space output_color_space, 277 bool use_vsc_sdp_for_colorimetry, 278 uint32_t enable_sdp_splitting) 279 { 280 #if defined(CONFIG_DRM_AMD_DC_DCN) 281 uint32_t h_active_start; 282 uint32_t v_active_start; 283 uint32_t misc0 = 0; 284 uint32_t misc1 = 0; 285 uint32_t h_blank; 286 uint32_t h_back_porch; 287 uint8_t synchronous_clock = 0; /* asynchronous mode */ 288 uint8_t colorimetry_bpc; 289 uint8_t dynamic_range_rgb = 0; /*full range*/ 290 uint8_t dynamic_range_ycbcr = 1; /*bt709*/ 291 #endif 292 293 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 294 struct dc_crtc_timing hw_crtc_timing = *crtc_timing; 295 if (hw_crtc_timing.flags.INTERLACE) { 296 /*the input timing is in VESA spec format with Interlace flag =1*/ 297 hw_crtc_timing.v_total /= 2; 298 hw_crtc_timing.v_border_top /= 2; 299 hw_crtc_timing.v_addressable /= 2; 300 hw_crtc_timing.v_border_bottom /= 2; 301 hw_crtc_timing.v_front_porch /= 2; 302 hw_crtc_timing.v_sync_width /= 2; 303 } 304 /* set pixel encoding */ 305 switch (hw_crtc_timing.pixel_encoding) { 306 case PIXEL_ENCODING_YCBCR422: 307 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 308 DP_PIXEL_ENCODING_TYPE_YCBCR422); 309 break; 310 case PIXEL_ENCODING_YCBCR444: 311 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 312 DP_PIXEL_ENCODING_TYPE_YCBCR444); 313 314 if (hw_crtc_timing.flags.Y_ONLY) 315 if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666) 316 /* HW testing only, no use case yet. 317 * Color depth of Y-only could be 318 * 8, 10, 12, 16 bits */ 319 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 320 DP_PIXEL_ENCODING_TYPE_Y_ONLY); 321 /* Note: DP_MSA_MISC1 bit 7 is the indicator 322 * of Y-only mode. 323 * This bit is set in HW if register 324 * DP_PIXEL_ENCODING is programmed to 0x4 */ 325 break; 326 case PIXEL_ENCODING_YCBCR420: 327 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 328 DP_PIXEL_ENCODING_TYPE_YCBCR420); 329 if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN) 330 REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1); 331 332 #if defined(CONFIG_DRM_AMD_DC_DCN) 333 if (enc110->se_mask->DP_VID_N_MUL) 334 REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1); 335 #endif 336 break; 337 default: 338 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 339 DP_PIXEL_ENCODING_TYPE_RGB444); 340 break; 341 } 342 343 #if defined(CONFIG_DRM_AMD_DC_DCN) 344 if (REG(DP_MSA_MISC)) 345 misc1 = REG_READ(DP_MSA_MISC); 346 #endif 347 348 /* set color depth */ 349 350 switch (hw_crtc_timing.display_color_depth) { 351 case COLOR_DEPTH_666: 352 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 353 0); 354 break; 355 case COLOR_DEPTH_888: 356 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 357 DP_COMPONENT_PIXEL_DEPTH_8BPC); 358 break; 359 case COLOR_DEPTH_101010: 360 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 361 DP_COMPONENT_PIXEL_DEPTH_10BPC); 362 363 break; 364 case COLOR_DEPTH_121212: 365 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 366 DP_COMPONENT_PIXEL_DEPTH_12BPC); 367 break; 368 default: 369 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 370 DP_COMPONENT_PIXEL_DEPTH_6BPC); 371 break; 372 } 373 374 /* set dynamic range and YCbCr range */ 375 376 377 #if defined(CONFIG_DRM_AMD_DC_DCN) 378 switch (hw_crtc_timing.display_color_depth) { 379 case COLOR_DEPTH_666: 380 colorimetry_bpc = 0; 381 break; 382 case COLOR_DEPTH_888: 383 colorimetry_bpc = 1; 384 break; 385 case COLOR_DEPTH_101010: 386 colorimetry_bpc = 2; 387 break; 388 case COLOR_DEPTH_121212: 389 colorimetry_bpc = 3; 390 break; 391 default: 392 colorimetry_bpc = 0; 393 break; 394 } 395 396 misc0 = misc0 | synchronous_clock; 397 misc0 = colorimetry_bpc << 5; 398 399 if (REG(DP_MSA_TIMING_PARAM1)) { 400 switch (output_color_space) { 401 case COLOR_SPACE_SRGB: 402 misc0 = misc0 | 0x0; 403 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 404 dynamic_range_rgb = 0; /*full range*/ 405 break; 406 case COLOR_SPACE_SRGB_LIMITED: 407 misc0 = misc0 | 0x8; /* bit3=1 */ 408 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 409 dynamic_range_rgb = 1; /*limited range*/ 410 break; 411 case COLOR_SPACE_YCBCR601: 412 case COLOR_SPACE_YCBCR601_LIMITED: 413 misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */ 414 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 415 dynamic_range_ycbcr = 0; /*bt601*/ 416 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 417 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 418 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444) 419 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 420 break; 421 case COLOR_SPACE_YCBCR709: 422 case COLOR_SPACE_YCBCR709_LIMITED: 423 case COLOR_SPACE_YCBCR709_BLACK: 424 misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */ 425 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 426 dynamic_range_ycbcr = 1; /*bt709*/ 427 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 428 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 429 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444) 430 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 431 break; 432 case COLOR_SPACE_2020_RGB_LIMITEDRANGE: 433 dynamic_range_rgb = 1; /*limited range*/ 434 break; 435 case COLOR_SPACE_2020_RGB_FULLRANGE: 436 case COLOR_SPACE_2020_YCBCR: 437 case COLOR_SPACE_XR_RGB: 438 case COLOR_SPACE_MSREF_SCRGB: 439 case COLOR_SPACE_ADOBERGB: 440 case COLOR_SPACE_DCIP3: 441 case COLOR_SPACE_XV_YCC_709: 442 case COLOR_SPACE_XV_YCC_601: 443 case COLOR_SPACE_DISPLAYNATIVE: 444 case COLOR_SPACE_DOLBYVISION: 445 case COLOR_SPACE_APPCTRL: 446 case COLOR_SPACE_CUSTOMPOINTS: 447 case COLOR_SPACE_UNKNOWN: 448 /* do nothing */ 449 break; 450 } 451 if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE) 452 REG_UPDATE_2( 453 DP_PIXEL_FORMAT, 454 DP_DYN_RANGE, dynamic_range_rgb, 455 DP_YCBCR_RANGE, dynamic_range_ycbcr); 456 457 #if defined(CONFIG_DRM_AMD_DC_DCN) 458 if (REG(DP_MSA_COLORIMETRY)) 459 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); 460 461 if (REG(DP_MSA_MISC)) 462 REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */ 463 464 /* dcn new register 465 * dc_crtc_timing is vesa dmt struct. data from edid 466 */ 467 if (REG(DP_MSA_TIMING_PARAM1)) 468 REG_SET_2(DP_MSA_TIMING_PARAM1, 0, 469 DP_MSA_HTOTAL, hw_crtc_timing.h_total, 470 DP_MSA_VTOTAL, hw_crtc_timing.v_total); 471 #endif 472 473 /* calcuate from vesa timing parameters 474 * h_active_start related to leading edge of sync 475 */ 476 477 h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left - 478 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right; 479 480 h_back_porch = h_blank - hw_crtc_timing.h_front_porch - 481 hw_crtc_timing.h_sync_width; 482 483 /* start at begining of left border */ 484 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch; 485 486 487 v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top - 488 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom - 489 hw_crtc_timing.v_front_porch; 490 491 492 #if defined(CONFIG_DRM_AMD_DC_DCN) 493 /* start at begining of left border */ 494 if (REG(DP_MSA_TIMING_PARAM2)) 495 REG_SET_2(DP_MSA_TIMING_PARAM2, 0, 496 DP_MSA_HSTART, h_active_start, 497 DP_MSA_VSTART, v_active_start); 498 499 if (REG(DP_MSA_TIMING_PARAM3)) 500 REG_SET_4(DP_MSA_TIMING_PARAM3, 0, 501 DP_MSA_HSYNCWIDTH, 502 hw_crtc_timing.h_sync_width, 503 DP_MSA_HSYNCPOLARITY, 504 !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY, 505 DP_MSA_VSYNCWIDTH, 506 hw_crtc_timing.v_sync_width, 507 DP_MSA_VSYNCPOLARITY, 508 !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY); 509 510 /* HWDITH include border or overscan */ 511 if (REG(DP_MSA_TIMING_PARAM4)) 512 REG_SET_2(DP_MSA_TIMING_PARAM4, 0, 513 DP_MSA_HWIDTH, hw_crtc_timing.h_border_left + 514 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right, 515 DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top + 516 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom); 517 #endif 518 } 519 #endif 520 } 521 522 static void dce110_stream_encoder_set_stream_attribute_helper( 523 struct dce110_stream_encoder *enc110, 524 struct dc_crtc_timing *crtc_timing) 525 { 526 if (enc110->regs->TMDS_CNTL) { 527 switch (crtc_timing->pixel_encoding) { 528 case PIXEL_ENCODING_YCBCR422: 529 REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1); 530 break; 531 default: 532 REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0); 533 break; 534 } 535 REG_UPDATE(TMDS_CNTL, TMDS_COLOR_FORMAT, 0); 536 } else if (enc110->regs->DIG_FE_CNTL) { 537 switch (crtc_timing->pixel_encoding) { 538 case PIXEL_ENCODING_YCBCR422: 539 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1); 540 break; 541 default: 542 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0); 543 break; 544 } 545 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0); 546 } 547 548 } 549 550 /* setup stream encoder in hdmi mode */ 551 static void dce110_stream_encoder_hdmi_set_stream_attribute( 552 struct stream_encoder *enc, 553 struct dc_crtc_timing *crtc_timing, 554 int actual_pix_clk_khz, 555 bool enable_audio) 556 { 557 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 558 struct bp_encoder_control cntl = {0}; 559 560 cntl.action = ENCODER_CONTROL_SETUP; 561 cntl.engine_id = enc110->base.id; 562 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; 563 cntl.enable_dp_audio = enable_audio; 564 cntl.pixel_clock = actual_pix_clk_khz; 565 cntl.lanes_number = LANE_COUNT_FOUR; 566 cntl.color_depth = crtc_timing->display_color_depth; 567 568 if (enc110->base.bp->funcs->encoder_control( 569 enc110->base.bp, &cntl) != BP_RESULT_OK) 570 return; 571 572 dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing); 573 574 /* setup HDMI engine */ 575 if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) { 576 REG_UPDATE_3(HDMI_CONTROL, 577 HDMI_PACKET_GEN_VERSION, 1, 578 HDMI_KEEPOUT_MODE, 1, 579 HDMI_DEEP_COLOR_ENABLE, 0); 580 } else if (enc110->regs->DIG_FE_CNTL) { 581 REG_UPDATE_5(HDMI_CONTROL, 582 HDMI_PACKET_GEN_VERSION, 1, 583 HDMI_KEEPOUT_MODE, 1, 584 HDMI_DEEP_COLOR_ENABLE, 0, 585 HDMI_DATA_SCRAMBLE_EN, 0, 586 HDMI_CLOCK_CHANNEL_RATE, 0); 587 } 588 589 switch (crtc_timing->display_color_depth) { 590 case COLOR_DEPTH_888: 591 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 592 break; 593 case COLOR_DEPTH_101010: 594 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 595 REG_UPDATE_2(HDMI_CONTROL, 596 HDMI_DEEP_COLOR_DEPTH, 1, 597 HDMI_DEEP_COLOR_ENABLE, 0); 598 } else { 599 REG_UPDATE_2(HDMI_CONTROL, 600 HDMI_DEEP_COLOR_DEPTH, 1, 601 HDMI_DEEP_COLOR_ENABLE, 1); 602 } 603 break; 604 case COLOR_DEPTH_121212: 605 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 606 REG_UPDATE_2(HDMI_CONTROL, 607 HDMI_DEEP_COLOR_DEPTH, 2, 608 HDMI_DEEP_COLOR_ENABLE, 0); 609 } else { 610 REG_UPDATE_2(HDMI_CONTROL, 611 HDMI_DEEP_COLOR_DEPTH, 2, 612 HDMI_DEEP_COLOR_ENABLE, 1); 613 } 614 break; 615 case COLOR_DEPTH_161616: 616 REG_UPDATE_2(HDMI_CONTROL, 617 HDMI_DEEP_COLOR_DEPTH, 3, 618 HDMI_DEEP_COLOR_ENABLE, 1); 619 break; 620 default: 621 break; 622 } 623 624 if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) { 625 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) { 626 /* enable HDMI data scrambler 627 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M 628 * Clock channel frequency is 1/4 of character rate. 629 */ 630 REG_UPDATE_2(HDMI_CONTROL, 631 HDMI_DATA_SCRAMBLE_EN, 1, 632 HDMI_CLOCK_CHANNEL_RATE, 1); 633 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) { 634 635 /* TODO: New feature for DCE11, still need to implement */ 636 637 /* enable HDMI data scrambler 638 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE 639 * Clock channel frequency is the same 640 * as character rate 641 */ 642 REG_UPDATE_2(HDMI_CONTROL, 643 HDMI_DATA_SCRAMBLE_EN, 1, 644 HDMI_CLOCK_CHANNEL_RATE, 0); 645 } 646 } 647 648 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL, 649 HDMI_GC_CONT, 1, 650 HDMI_GC_SEND, 1, 651 HDMI_NULL_SEND, 1); 652 653 /* following belongs to audio */ 654 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 655 656 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 657 658 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 659 VBI_LINE_0 + 2); 660 661 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); 662 663 } 664 665 /* setup stream encoder in dvi mode */ 666 static void dce110_stream_encoder_dvi_set_stream_attribute( 667 struct stream_encoder *enc, 668 struct dc_crtc_timing *crtc_timing, 669 bool is_dual_link) 670 { 671 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 672 struct bp_encoder_control cntl = {0}; 673 674 cntl.action = ENCODER_CONTROL_SETUP; 675 cntl.engine_id = enc110->base.id; 676 cntl.signal = is_dual_link ? 677 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK; 678 cntl.enable_dp_audio = false; 679 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10; 680 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; 681 682 if (enc110->base.bp->funcs->encoder_control( 683 enc110->base.bp, &cntl) != BP_RESULT_OK) 684 return; 685 686 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); 687 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888); 688 dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing); 689 } 690 691 /* setup stream encoder in LVDS mode */ 692 static void dce110_stream_encoder_lvds_set_stream_attribute( 693 struct stream_encoder *enc, 694 struct dc_crtc_timing *crtc_timing) 695 { 696 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 697 struct bp_encoder_control cntl = {0}; 698 699 cntl.action = ENCODER_CONTROL_SETUP; 700 cntl.engine_id = enc110->base.id; 701 cntl.signal = SIGNAL_TYPE_LVDS; 702 cntl.enable_dp_audio = false; 703 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10; 704 cntl.lanes_number = LANE_COUNT_FOUR; 705 706 if (enc110->base.bp->funcs->encoder_control( 707 enc110->base.bp, &cntl) != BP_RESULT_OK) 708 return; 709 710 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); 711 } 712 713 static void dce110_stream_encoder_set_throttled_vcp_size( 714 struct stream_encoder *enc, 715 struct fixed31_32 avg_time_slots_per_mtp) 716 { 717 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 718 uint32_t x = dc_fixpt_floor( 719 avg_time_slots_per_mtp); 720 uint32_t y = dc_fixpt_ceil( 721 dc_fixpt_shl( 722 dc_fixpt_sub_int( 723 avg_time_slots_per_mtp, 724 x), 725 26)); 726 727 { 728 REG_SET_2(DP_MSE_RATE_CNTL, 0, 729 DP_MSE_RATE_X, x, 730 DP_MSE_RATE_Y, y); 731 } 732 733 /* wait for update to be completed on the link */ 734 /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */ 735 /* is reset to 0 (not pending) */ 736 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, 737 0, 738 10, DP_MST_UPDATE_MAX_RETRY); 739 } 740 741 static void dce110_stream_encoder_update_hdmi_info_packets( 742 struct stream_encoder *enc, 743 const struct encoder_info_frame *info_frame) 744 { 745 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 746 747 if (enc110->se_mask->HDMI_AVI_INFO_CONT && 748 enc110->se_mask->HDMI_AVI_INFO_SEND) { 749 750 if (info_frame->avi.valid) { 751 const uint32_t *content = 752 (const uint32_t *) &info_frame->avi.sb[0]; 753 /*we need turn on clock before programming AFMT block*/ 754 if (REG(AFMT_CNTL)) 755 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 756 757 REG_WRITE(AFMT_AVI_INFO0, content[0]); 758 759 REG_WRITE(AFMT_AVI_INFO1, content[1]); 760 761 REG_WRITE(AFMT_AVI_INFO2, content[2]); 762 763 REG_WRITE(AFMT_AVI_INFO3, content[3]); 764 765 REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, 766 info_frame->avi.hb1); 767 768 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0, 769 HDMI_AVI_INFO_SEND, 1, 770 HDMI_AVI_INFO_CONT, 1); 771 772 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 773 VBI_LINE_0 + 2); 774 775 } else { 776 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0, 777 HDMI_AVI_INFO_SEND, 0, 778 HDMI_AVI_INFO_CONT, 0); 779 } 780 } 781 782 if (enc110->se_mask->HDMI_AVI_INFO_CONT && 783 enc110->se_mask->HDMI_AVI_INFO_SEND) { 784 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor); 785 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut); 786 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd); 787 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd); 788 } 789 790 #if defined(CONFIG_DRM_AMD_DC_DCN) 791 if (enc110->se_mask->HDMI_DB_DISABLE) { 792 /* for bring up, disable dp double TODO */ 793 if (REG(HDMI_DB_CONTROL)) 794 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); 795 796 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->avi); 797 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->vendor); 798 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->gamut); 799 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd); 800 dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd); 801 } 802 #endif 803 } 804 805 static void dce110_stream_encoder_stop_hdmi_info_packets( 806 struct stream_encoder *enc) 807 { 808 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 809 810 /* stop generic packets 0 & 1 on HDMI */ 811 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0, 812 HDMI_GENERIC1_CONT, 0, 813 HDMI_GENERIC1_LINE, 0, 814 HDMI_GENERIC1_SEND, 0, 815 HDMI_GENERIC0_CONT, 0, 816 HDMI_GENERIC0_LINE, 0, 817 HDMI_GENERIC0_SEND, 0); 818 819 /* stop generic packets 2 & 3 on HDMI */ 820 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0, 821 HDMI_GENERIC0_CONT, 0, 822 HDMI_GENERIC0_LINE, 0, 823 HDMI_GENERIC0_SEND, 0, 824 HDMI_GENERIC1_CONT, 0, 825 HDMI_GENERIC1_LINE, 0, 826 HDMI_GENERIC1_SEND, 0); 827 828 #if defined(CONFIG_DRM_AMD_DC_DCN) 829 /* stop generic packets 2 & 3 on HDMI */ 830 if (REG(HDMI_GENERIC_PACKET_CONTROL2)) 831 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0, 832 HDMI_GENERIC0_CONT, 0, 833 HDMI_GENERIC0_LINE, 0, 834 HDMI_GENERIC0_SEND, 0, 835 HDMI_GENERIC1_CONT, 0, 836 HDMI_GENERIC1_LINE, 0, 837 HDMI_GENERIC1_SEND, 0); 838 839 if (REG(HDMI_GENERIC_PACKET_CONTROL3)) 840 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0, 841 HDMI_GENERIC0_CONT, 0, 842 HDMI_GENERIC0_LINE, 0, 843 HDMI_GENERIC0_SEND, 0, 844 HDMI_GENERIC1_CONT, 0, 845 HDMI_GENERIC1_LINE, 0, 846 HDMI_GENERIC1_SEND, 0); 847 #endif 848 } 849 850 static void dce110_stream_encoder_update_dp_info_packets( 851 struct stream_encoder *enc, 852 const struct encoder_info_frame *info_frame) 853 { 854 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 855 uint32_t value = 0; 856 857 if (info_frame->vsc.valid) 858 dce110_update_generic_info_packet( 859 enc110, 860 0, /* packetIndex */ 861 &info_frame->vsc); 862 863 if (info_frame->spd.valid) 864 dce110_update_generic_info_packet( 865 enc110, 866 2, /* packetIndex */ 867 &info_frame->spd); 868 869 if (info_frame->hdrsmd.valid) 870 dce110_update_generic_info_packet( 871 enc110, 872 3, /* packetIndex */ 873 &info_frame->hdrsmd); 874 875 /* enable/disable transmission of packet(s). 876 * If enabled, packet transmission begins on the next frame 877 */ 878 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); 879 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); 880 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); 881 882 /* This bit is the master enable bit. 883 * When enabling secondary stream engine, 884 * this master bit must also be set. 885 * This register shared with audio info frame. 886 * Therefore we need to enable master bit 887 * if at least on of the fields is not 0 888 */ 889 value = REG_READ(DP_SEC_CNTL); 890 if (value) 891 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 892 } 893 894 static void dce110_stream_encoder_stop_dp_info_packets( 895 struct stream_encoder *enc) 896 { 897 /* stop generic packets on DP */ 898 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 899 uint32_t value = 0; 900 901 if (enc110->se_mask->DP_SEC_AVI_ENABLE) { 902 REG_SET_7(DP_SEC_CNTL, 0, 903 DP_SEC_GSP0_ENABLE, 0, 904 DP_SEC_GSP1_ENABLE, 0, 905 DP_SEC_GSP2_ENABLE, 0, 906 DP_SEC_GSP3_ENABLE, 0, 907 DP_SEC_AVI_ENABLE, 0, 908 DP_SEC_MPG_ENABLE, 0, 909 DP_SEC_STREAM_ENABLE, 0); 910 } 911 912 /* this register shared with audio info frame. 913 * therefore we need to keep master enabled 914 * if at least one of the fields is not 0 */ 915 value = REG_READ(DP_SEC_CNTL); 916 if (value) 917 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 918 919 } 920 921 static void dce110_stream_encoder_dp_blank( 922 struct stream_encoder *enc) 923 { 924 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 925 uint32_t reg1 = 0; 926 uint32_t max_retries = DP_BLANK_MAX_RETRY * 10; 927 928 /* Note: For CZ, we are changing driver default to disable 929 * stream deferred to next VBLANK. If results are positive, we 930 * will make the same change to all DCE versions. There are a 931 * handful of panels that cannot handle disable stream at 932 * HBLANK and will result in a white line flash across the 933 * screen on stream disable. */ 934 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1); 935 if ((reg1 & 0x1) == 0) 936 /*stream not enabled*/ 937 return; 938 /* Specify the video stream disable point 939 * (2 = start of the next vertical blank) */ 940 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2); 941 /* Larger delay to wait until VBLANK - use max retry of 942 * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode + 943 * a little more because we may not trust delay accuracy. 944 */ 945 max_retries = DP_BLANK_MAX_RETRY * 150; 946 947 /* disable DP stream */ 948 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); 949 950 /* the encoder stops sending the video stream 951 * at the start of the vertical blanking. 952 * Poll for DP_VID_STREAM_STATUS == 0 953 */ 954 955 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 956 0, 957 10, max_retries); 958 959 /* Tell the DP encoder to ignore timing from CRTC, must be done after 960 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is 961 * complete, stream status will be stuck in video stream enabled state, 962 * i.e. DP_VID_STREAM_STATUS stuck at 1. 963 */ 964 965 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true); 966 } 967 968 /* output video stream to link encoder */ 969 static void dce110_stream_encoder_dp_unblank( 970 struct stream_encoder *enc, 971 const struct encoder_unblank_param *param) 972 { 973 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 974 975 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { 976 uint32_t n_vid = 0x8000; 977 uint32_t m_vid; 978 979 /* M / N = Fstream / Flink 980 * m_vid / n_vid = pixel rate / link rate 981 */ 982 983 uint64_t m_vid_l = n_vid; 984 985 m_vid_l *= param->timing.pix_clk_100hz / 10; 986 m_vid_l = div_u64(m_vid_l, 987 param->link_settings.link_rate 988 * LINK_RATE_REF_FREQ_IN_KHZ); 989 990 m_vid = (uint32_t) m_vid_l; 991 992 /* enable auto measurement */ 993 994 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0); 995 996 /* auto measurement need 1 full 0x8000 symbol cycle to kick in, 997 * therefore program initial value for Mvid and Nvid 998 */ 999 1000 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid); 1001 1002 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid); 1003 1004 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1); 1005 } 1006 1007 /* set DIG_START to 0x1 to resync FIFO */ 1008 1009 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); 1010 1011 /* switch DP encoder to CRTC data */ 1012 1013 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); 1014 1015 /* wait 100us for DIG/DP logic to prime 1016 * (i.e. a few video lines) 1017 */ 1018 udelay(100); 1019 1020 /* the hardware would start sending video at the start of the next DP 1021 * frame (i.e. rising edge of the vblank). 1022 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this 1023 * register has no effect on enable transition! HW always guarantees 1024 * VID_STREAM enable at start of next frame, and this is not 1025 * programmable 1026 */ 1027 1028 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); 1029 } 1030 1031 static void dce110_stream_encoder_set_avmute( 1032 struct stream_encoder *enc, 1033 bool enable) 1034 { 1035 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1036 unsigned int value = enable ? 1 : 0; 1037 1038 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value); 1039 } 1040 1041 1042 static void dce110_reset_hdmi_stream_attribute( 1043 struct stream_encoder *enc) 1044 { 1045 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1046 if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) 1047 REG_UPDATE_5(HDMI_CONTROL, 1048 HDMI_PACKET_GEN_VERSION, 1, 1049 HDMI_KEEPOUT_MODE, 1, 1050 HDMI_DEEP_COLOR_ENABLE, 0, 1051 HDMI_DATA_SCRAMBLE_EN, 0, 1052 HDMI_CLOCK_CHANNEL_RATE, 0); 1053 else 1054 REG_UPDATE_3(HDMI_CONTROL, 1055 HDMI_PACKET_GEN_VERSION, 1, 1056 HDMI_KEEPOUT_MODE, 1, 1057 HDMI_DEEP_COLOR_ENABLE, 0); 1058 } 1059 1060 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000 1061 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1 1062 1063 #include "include/audio_types.h" 1064 1065 1066 /* 25.2MHz/1.001*/ 1067 /* 25.2MHz/1.001*/ 1068 /* 25.2MHz*/ 1069 /* 27MHz */ 1070 /* 27MHz*1.001*/ 1071 /* 27MHz*1.001*/ 1072 /* 54MHz*/ 1073 /* 54MHz*1.001*/ 1074 /* 74.25MHz/1.001*/ 1075 /* 74.25MHz*/ 1076 /* 148.5MHz/1.001*/ 1077 /* 148.5MHz*/ 1078 1079 static const struct audio_clock_info audio_clock_info_table[16] = { 1080 {2517, 4576, 28125, 7007, 31250, 6864, 28125}, 1081 {2518, 4576, 28125, 7007, 31250, 6864, 28125}, 1082 {2520, 4096, 25200, 6272, 28000, 6144, 25200}, 1083 {2700, 4096, 27000, 6272, 30000, 6144, 27000}, 1084 {2702, 4096, 27027, 6272, 30030, 6144, 27027}, 1085 {2703, 4096, 27027, 6272, 30030, 6144, 27027}, 1086 {5400, 4096, 54000, 6272, 60000, 6144, 54000}, 1087 {5405, 4096, 54054, 6272, 60060, 6144, 54054}, 1088 {7417, 11648, 210937, 17836, 234375, 11648, 140625}, 1089 {7425, 4096, 74250, 6272, 82500, 6144, 74250}, 1090 {14835, 11648, 421875, 8918, 234375, 5824, 140625}, 1091 {14850, 4096, 148500, 6272, 165000, 6144, 148500}, 1092 {29670, 5824, 421875, 4459, 234375, 5824, 281250}, 1093 {29700, 3072, 222750, 4704, 247500, 5120, 247500}, 1094 {59340, 5824, 843750, 8918, 937500, 5824, 562500}, 1095 {59400, 3072, 445500, 9408, 990000, 6144, 594000} 1096 }; 1097 1098 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = { 1099 {2517, 9152, 84375, 7007, 48875, 9152, 56250}, 1100 {2518, 9152, 84375, 7007, 48875, 9152, 56250}, 1101 {2520, 4096, 37800, 6272, 42000, 6144, 37800}, 1102 {2700, 4096, 40500, 6272, 45000, 6144, 40500}, 1103 {2702, 8192, 81081, 6272, 45045, 8192, 54054}, 1104 {2703, 8192, 81081, 6272, 45045, 8192, 54054}, 1105 {5400, 4096, 81000, 6272, 90000, 6144, 81000}, 1106 {5405, 4096, 81081, 6272, 90090, 6144, 81081}, 1107 {7417, 11648, 316406, 17836, 351562, 11648, 210937}, 1108 {7425, 4096, 111375, 6272, 123750, 6144, 111375}, 1109 {14835, 11648, 632812, 17836, 703125, 11648, 421875}, 1110 {14850, 4096, 222750, 6272, 247500, 6144, 222750}, 1111 {29670, 5824, 632812, 8918, 703125, 5824, 421875}, 1112 {29700, 4096, 445500, 4704, 371250, 5120, 371250} 1113 }; 1114 1115 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = { 1116 {2517, 4576, 56250, 7007, 62500, 6864, 56250}, 1117 {2518, 4576, 56250, 7007, 62500, 6864, 56250}, 1118 {2520, 4096, 50400, 6272, 56000, 6144, 50400}, 1119 {2700, 4096, 54000, 6272, 60000, 6144, 54000}, 1120 {2702, 4096, 54054, 6267, 60060, 8192, 54054}, 1121 {2703, 4096, 54054, 6272, 60060, 8192, 54054}, 1122 {5400, 4096, 108000, 6272, 120000, 6144, 108000}, 1123 {5405, 4096, 108108, 6272, 120120, 6144, 108108}, 1124 {7417, 11648, 421875, 17836, 468750, 11648, 281250}, 1125 {7425, 4096, 148500, 6272, 165000, 6144, 148500}, 1126 {14835, 11648, 843750, 8918, 468750, 11648, 281250}, 1127 {14850, 4096, 297000, 6272, 330000, 6144, 297000}, 1128 {29670, 5824, 843750, 4459, 468750, 5824, 562500}, 1129 {29700, 3072, 445500, 4704, 495000, 5120, 495000} 1130 1131 1132 }; 1133 1134 static union audio_cea_channels speakers_to_channels( 1135 struct audio_speaker_flags speaker_flags) 1136 { 1137 union audio_cea_channels cea_channels = {0}; 1138 1139 /* these are one to one */ 1140 cea_channels.channels.FL = speaker_flags.FL_FR; 1141 cea_channels.channels.FR = speaker_flags.FL_FR; 1142 cea_channels.channels.LFE = speaker_flags.LFE; 1143 cea_channels.channels.FC = speaker_flags.FC; 1144 1145 /* if Rear Left and Right exist move RC speaker to channel 7 1146 * otherwise to channel 5 1147 */ 1148 if (speaker_flags.RL_RR) { 1149 cea_channels.channels.RL_RC = speaker_flags.RL_RR; 1150 cea_channels.channels.RR = speaker_flags.RL_RR; 1151 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC; 1152 } else { 1153 cea_channels.channels.RL_RC = speaker_flags.RC; 1154 } 1155 1156 /* FRONT Left Right Center and REAR Left Right Center are exclusive */ 1157 if (speaker_flags.FLC_FRC) { 1158 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC; 1159 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC; 1160 } else { 1161 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC; 1162 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC; 1163 } 1164 1165 return cea_channels; 1166 } 1167 1168 static uint32_t calc_max_audio_packets_per_line( 1169 const struct audio_crtc_info *crtc_info) 1170 { 1171 uint32_t max_packets_per_line; 1172 1173 max_packets_per_line = 1174 crtc_info->h_total - crtc_info->h_active; 1175 1176 if (crtc_info->pixel_repetition) 1177 max_packets_per_line *= crtc_info->pixel_repetition; 1178 1179 /* for other hdmi features */ 1180 max_packets_per_line -= 58; 1181 /* for Control Period */ 1182 max_packets_per_line -= 16; 1183 /* Number of Audio Packets per Line */ 1184 max_packets_per_line /= 32; 1185 1186 return max_packets_per_line; 1187 } 1188 1189 static void get_audio_clock_info( 1190 enum dc_color_depth color_depth, 1191 uint32_t crtc_pixel_clock_100Hz, 1192 uint32_t actual_pixel_clock_100Hz, 1193 struct audio_clock_info *audio_clock_info) 1194 { 1195 const struct audio_clock_info *clock_info; 1196 uint32_t index; 1197 uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100; 1198 uint32_t audio_array_size; 1199 1200 switch (color_depth) { 1201 case COLOR_DEPTH_161616: 1202 clock_info = audio_clock_info_table_48bpc; 1203 audio_array_size = ARRAY_SIZE( 1204 audio_clock_info_table_48bpc); 1205 break; 1206 case COLOR_DEPTH_121212: 1207 clock_info = audio_clock_info_table_36bpc; 1208 audio_array_size = ARRAY_SIZE( 1209 audio_clock_info_table_36bpc); 1210 break; 1211 default: 1212 clock_info = audio_clock_info_table; 1213 audio_array_size = ARRAY_SIZE( 1214 audio_clock_info_table); 1215 break; 1216 } 1217 1218 if (clock_info != NULL) { 1219 /* search for exact pixel clock in table */ 1220 for (index = 0; index < audio_array_size; index++) { 1221 if (clock_info[index].pixel_clock_in_10khz > 1222 crtc_pixel_clock_in_10khz) 1223 break; /* not match */ 1224 else if (clock_info[index].pixel_clock_in_10khz == 1225 crtc_pixel_clock_in_10khz) { 1226 /* match found */ 1227 *audio_clock_info = clock_info[index]; 1228 return; 1229 } 1230 } 1231 } 1232 1233 /* not found */ 1234 if (actual_pixel_clock_100Hz == 0) 1235 actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz; 1236 1237 /* See HDMI spec the table entry under 1238 * pixel clock of "Other". */ 1239 audio_clock_info->pixel_clock_in_10khz = 1240 actual_pixel_clock_100Hz / 100; 1241 audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10; 1242 audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10; 1243 audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10; 1244 1245 audio_clock_info->n_32khz = 4096; 1246 audio_clock_info->n_44khz = 6272; 1247 audio_clock_info->n_48khz = 6144; 1248 } 1249 1250 static void dce110_se_audio_setup( 1251 struct stream_encoder *enc, 1252 unsigned int az_inst, 1253 struct audio_info *audio_info) 1254 { 1255 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1256 1257 uint32_t channels = 0; 1258 1259 ASSERT(audio_info); 1260 if (audio_info == NULL) 1261 /* This should not happen.it does so we don't get BSOD*/ 1262 return; 1263 1264 channels = speakers_to_channels(audio_info->flags.speaker_flags).all; 1265 1266 /* setup the audio stream source select (audio -> dig mapping) */ 1267 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); 1268 1269 /* Channel allocation */ 1270 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels); 1271 } 1272 1273 static void dce110_se_setup_hdmi_audio( 1274 struct stream_encoder *enc, 1275 const struct audio_crtc_info *crtc_info) 1276 { 1277 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1278 1279 struct audio_clock_info audio_clock_info = {0}; 1280 uint32_t max_packets_per_line; 1281 1282 /* For now still do calculation, although this field is ignored when 1283 above HDMI_PACKET_GEN_VERSION set to 1 */ 1284 max_packets_per_line = calc_max_audio_packets_per_line(crtc_info); 1285 1286 /* HDMI_AUDIO_PACKET_CONTROL */ 1287 REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL, 1288 HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line, 1289 HDMI_AUDIO_DELAY_EN, 1); 1290 1291 /* AFMT_AUDIO_PACKET_CONTROL */ 1292 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1293 1294 /* AFMT_AUDIO_PACKET_CONTROL2 */ 1295 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 1296 AFMT_AUDIO_LAYOUT_OVRD, 0, 1297 AFMT_60958_OSF_OVRD, 0); 1298 1299 /* HDMI_ACR_PACKET_CONTROL */ 1300 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, 1301 HDMI_ACR_AUTO_SEND, 1, 1302 HDMI_ACR_SOURCE, 0, 1303 HDMI_ACR_AUDIO_PRIORITY, 0); 1304 1305 /* Program audio clock sample/regeneration parameters */ 1306 get_audio_clock_info(crtc_info->color_depth, 1307 crtc_info->requested_pixel_clock_100Hz, 1308 crtc_info->calculated_pixel_clock_100Hz, 1309 &audio_clock_info); 1310 DC_LOG_HW_AUDIO( 1311 "\n%s:Input::requested_pixel_clock_100Hz = %d" \ 1312 "calculated_pixel_clock_100Hz = %d \n", __func__, \ 1313 crtc_info->requested_pixel_clock_100Hz, \ 1314 crtc_info->calculated_pixel_clock_100Hz); 1315 1316 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */ 1317 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); 1318 1319 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */ 1320 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); 1321 1322 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */ 1323 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); 1324 1325 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */ 1326 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); 1327 1328 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */ 1329 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); 1330 1331 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */ 1332 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz); 1333 1334 /* Video driver cannot know in advance which sample rate will 1335 be used by HD Audio driver 1336 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is 1337 programmed below in interruppt callback */ 1338 1339 /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK & 1340 AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */ 1341 REG_UPDATE_2(AFMT_60958_0, 1342 AFMT_60958_CS_CHANNEL_NUMBER_L, 1, 1343 AFMT_60958_CS_CLOCK_ACCURACY, 0); 1344 1345 /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */ 1346 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1347 1348 /*AFMT_60958_2 now keep this settings until 1349 * Programming guide comes out*/ 1350 REG_UPDATE_6(AFMT_60958_2, 1351 AFMT_60958_CS_CHANNEL_NUMBER_2, 3, 1352 AFMT_60958_CS_CHANNEL_NUMBER_3, 4, 1353 AFMT_60958_CS_CHANNEL_NUMBER_4, 5, 1354 AFMT_60958_CS_CHANNEL_NUMBER_5, 6, 1355 AFMT_60958_CS_CHANNEL_NUMBER_6, 7, 1356 AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1357 } 1358 1359 static void dce110_se_setup_dp_audio( 1360 struct stream_encoder *enc) 1361 { 1362 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1363 1364 /* --- DP Audio packet configurations --- */ 1365 1366 /* ATP Configuration */ 1367 REG_SET(DP_SEC_AUD_N, 0, 1368 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT); 1369 1370 /* Async/auto-calc timestamp mode */ 1371 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE, 1372 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC); 1373 1374 /* --- The following are the registers 1375 * copied from the SetupHDMI --- */ 1376 1377 /* AFMT_AUDIO_PACKET_CONTROL */ 1378 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1379 1380 /* AFMT_AUDIO_PACKET_CONTROL2 */ 1381 /* Program the ATP and AIP next */ 1382 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 1383 AFMT_AUDIO_LAYOUT_OVRD, 0, 1384 AFMT_60958_OSF_OVRD, 0); 1385 1386 /* AFMT_INFOFRAME_CONTROL0 */ 1387 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1388 1389 /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */ 1390 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0); 1391 } 1392 1393 static void dce110_se_enable_audio_clock( 1394 struct stream_encoder *enc, 1395 bool enable) 1396 { 1397 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1398 1399 if (REG(AFMT_CNTL) == 0) 1400 return; /* DCE8/10 does not have this register */ 1401 1402 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable); 1403 1404 /* wait for AFMT clock to turn on, 1405 * expectation: this should complete in 1-2 reads 1406 * 1407 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10); 1408 * 1409 * TODO: wait for clock_on does not work well. May need HW 1410 * program sequence. But audio seems work normally even without wait 1411 * for clock_on status change 1412 */ 1413 } 1414 1415 static void dce110_se_enable_dp_audio( 1416 struct stream_encoder *enc) 1417 { 1418 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1419 1420 /* Enable Audio packets */ 1421 REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); 1422 1423 /* Program the ATP and AIP next */ 1424 REG_UPDATE_2(DP_SEC_CNTL, 1425 DP_SEC_ATP_ENABLE, 1, 1426 DP_SEC_AIP_ENABLE, 1); 1427 1428 /* Program STREAM_ENABLE after all the other enables. */ 1429 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1430 } 1431 1432 static void dce110_se_disable_dp_audio( 1433 struct stream_encoder *enc) 1434 { 1435 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1436 uint32_t value = 0; 1437 1438 /* Disable Audio packets */ 1439 REG_UPDATE_5(DP_SEC_CNTL, 1440 DP_SEC_ASP_ENABLE, 0, 1441 DP_SEC_ATP_ENABLE, 0, 1442 DP_SEC_AIP_ENABLE, 0, 1443 DP_SEC_ACM_ENABLE, 0, 1444 DP_SEC_STREAM_ENABLE, 0); 1445 1446 /* This register shared with encoder info frame. Therefore we need to 1447 keep master enabled if at least on of the fields is not 0 */ 1448 value = REG_READ(DP_SEC_CNTL); 1449 if (value != 0) 1450 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1451 1452 } 1453 1454 void dce110_se_audio_mute_control( 1455 struct stream_encoder *enc, 1456 bool mute) 1457 { 1458 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1459 1460 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute); 1461 } 1462 1463 void dce110_se_dp_audio_setup( 1464 struct stream_encoder *enc, 1465 unsigned int az_inst, 1466 struct audio_info *info) 1467 { 1468 dce110_se_audio_setup(enc, az_inst, info); 1469 } 1470 1471 void dce110_se_dp_audio_enable( 1472 struct stream_encoder *enc) 1473 { 1474 dce110_se_enable_audio_clock(enc, true); 1475 dce110_se_setup_dp_audio(enc); 1476 dce110_se_enable_dp_audio(enc); 1477 } 1478 1479 void dce110_se_dp_audio_disable( 1480 struct stream_encoder *enc) 1481 { 1482 dce110_se_disable_dp_audio(enc); 1483 dce110_se_enable_audio_clock(enc, false); 1484 } 1485 1486 void dce110_se_hdmi_audio_setup( 1487 struct stream_encoder *enc, 1488 unsigned int az_inst, 1489 struct audio_info *info, 1490 struct audio_crtc_info *audio_crtc_info) 1491 { 1492 dce110_se_enable_audio_clock(enc, true); 1493 dce110_se_setup_hdmi_audio(enc, audio_crtc_info); 1494 dce110_se_audio_setup(enc, az_inst, info); 1495 } 1496 1497 void dce110_se_hdmi_audio_disable( 1498 struct stream_encoder *enc) 1499 { 1500 dce110_se_enable_audio_clock(enc, false); 1501 } 1502 1503 1504 static void setup_stereo_sync( 1505 struct stream_encoder *enc, 1506 int tg_inst, bool enable) 1507 { 1508 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1509 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); 1510 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable); 1511 } 1512 1513 static void dig_connect_to_otg( 1514 struct stream_encoder *enc, 1515 int tg_inst) 1516 { 1517 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1518 1519 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); 1520 } 1521 1522 static unsigned int dig_source_otg( 1523 struct stream_encoder *enc) 1524 { 1525 uint32_t tg_inst = 0; 1526 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1527 1528 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); 1529 1530 return tg_inst; 1531 } 1532 1533 static const struct stream_encoder_funcs dce110_str_enc_funcs = { 1534 .dp_set_stream_attribute = 1535 dce110_stream_encoder_dp_set_stream_attribute, 1536 .hdmi_set_stream_attribute = 1537 dce110_stream_encoder_hdmi_set_stream_attribute, 1538 .dvi_set_stream_attribute = 1539 dce110_stream_encoder_dvi_set_stream_attribute, 1540 .lvds_set_stream_attribute = 1541 dce110_stream_encoder_lvds_set_stream_attribute, 1542 .set_throttled_vcp_size = 1543 dce110_stream_encoder_set_throttled_vcp_size, 1544 .update_hdmi_info_packets = 1545 dce110_stream_encoder_update_hdmi_info_packets, 1546 .stop_hdmi_info_packets = 1547 dce110_stream_encoder_stop_hdmi_info_packets, 1548 .update_dp_info_packets = 1549 dce110_stream_encoder_update_dp_info_packets, 1550 .stop_dp_info_packets = 1551 dce110_stream_encoder_stop_dp_info_packets, 1552 .dp_blank = 1553 dce110_stream_encoder_dp_blank, 1554 .dp_unblank = 1555 dce110_stream_encoder_dp_unblank, 1556 .audio_mute_control = dce110_se_audio_mute_control, 1557 1558 .dp_audio_setup = dce110_se_dp_audio_setup, 1559 .dp_audio_enable = dce110_se_dp_audio_enable, 1560 .dp_audio_disable = dce110_se_dp_audio_disable, 1561 1562 .hdmi_audio_setup = dce110_se_hdmi_audio_setup, 1563 .hdmi_audio_disable = dce110_se_hdmi_audio_disable, 1564 .setup_stereo_sync = setup_stereo_sync, 1565 .set_avmute = dce110_stream_encoder_set_avmute, 1566 .dig_connect_to_otg = dig_connect_to_otg, 1567 .hdmi_reset_stream_attribute = dce110_reset_hdmi_stream_attribute, 1568 .dig_source_otg = dig_source_otg, 1569 }; 1570 1571 void dce110_stream_encoder_construct( 1572 struct dce110_stream_encoder *enc110, 1573 struct dc_context *ctx, 1574 struct dc_bios *bp, 1575 enum engine_id eng_id, 1576 const struct dce110_stream_enc_registers *regs, 1577 const struct dce_stream_encoder_shift *se_shift, 1578 const struct dce_stream_encoder_mask *se_mask) 1579 { 1580 enc110->base.funcs = &dce110_str_enc_funcs; 1581 enc110->base.ctx = ctx; 1582 enc110->base.id = eng_id; 1583 enc110->base.bp = bp; 1584 enc110->regs = regs; 1585 enc110->se_shift = se_shift; 1586 enc110->se_mask = se_mask; 1587 } 1588